229 lines
6.0 KiB
C
229 lines
6.0 KiB
C
/*
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* Copyright © 2014 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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*/
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#include "igt.h"
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#include <errno.h>
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#include <limits.h>
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#include <stdbool.h>
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#include <stdio.h>
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#include <string.h>
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IGT_TEST_DESCRIPTION("Exercises full ppgtt fence pin_count leak in the "
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"kernel.");
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typedef struct {
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int drm_fd;
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uint32_t devid;
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drm_intel_bufmgr *bufmgr;
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igt_display_t display;
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drm_intel_bo *bos[64]; /* >= num fence registers */
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} data_t;
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static void exec_nop(data_t *data, uint32_t handle, drm_intel_context *context)
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{
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drm_intel_bo *dst;
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struct intel_batchbuffer *batch;
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dst = gem_handle_to_libdrm_bo(data->bufmgr, data->drm_fd, "", handle);
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igt_assert(dst);
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batch = intel_batchbuffer_alloc(data->bufmgr, data->devid);
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igt_assert(batch);
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/* add the reloc to make sure the kernel will think we write to dst */
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BEGIN_BATCH(4, 1);
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OUT_BATCH(MI_BATCH_BUFFER_END);
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OUT_BATCH(MI_NOOP);
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OUT_RELOC(dst, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
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OUT_BATCH(MI_NOOP);
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ADVANCE_BATCH();
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intel_batchbuffer_flush_with_context(batch, context);
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intel_batchbuffer_free(batch);
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drm_intel_bo_unreference(dst);
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}
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static void alloc_fence_objs(data_t *data)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(data->bos); i++) {
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drm_intel_bo *bo;
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bo = drm_intel_bo_alloc(data->bufmgr, "fence bo", 4096, 4096);
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igt_assert(bo);
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gem_set_tiling(data->drm_fd, bo->handle, I915_TILING_X, 512);
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data->bos[i] = bo;
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}
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}
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static void touch_fences(data_t *data)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(data->bos); i++) {
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uint32_t handle = data->bos[i]->handle;
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void *ptr;
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ptr = gem_mmap__gtt(data->drm_fd, handle, 4096, PROT_WRITE);
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gem_set_domain(data->drm_fd, handle, I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
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memset(ptr, 0, 4);
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munmap(ptr, 4096);
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}
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}
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static void free_fence_objs(data_t *data)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(data->bos); i++)
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drm_intel_bo_unreference(data->bos[i]);
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}
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static void run_single_test(data_t *data, enum pipe pipe, igt_output_t *output)
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{
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igt_display_t *display = &data->display;
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drmModeModeInfo *mode;
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igt_plane_t *primary;
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struct igt_fb fb[2];
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int i;
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igt_output_set_pipe(output, pipe);
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mode = igt_output_get_mode(output);
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primary = igt_output_get_plane_type(output, DRM_PLANE_TYPE_PRIMARY);
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igt_create_color_fb(data->drm_fd, mode->hdisplay, mode->vdisplay,
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DRM_FORMAT_XRGB8888,
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LOCAL_I915_FORMAT_MOD_X_TILED , /* need a fence so must be tiled */
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0.0, 0.0, 0.0,
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&fb[0]);
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igt_create_color_fb(data->drm_fd, mode->hdisplay, mode->vdisplay,
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DRM_FORMAT_XRGB8888,
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LOCAL_I915_FORMAT_MOD_X_TILED, /* need a fence so must be tiled */
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0.0, 0.0, 0.0,
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&fb[1]);
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igt_plane_set_fb(primary, &fb[0]);
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igt_display_commit(display);
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for (i = 0; i < 64; i++) {
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drm_intel_context *ctx;
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/*
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* Link fb.gem_handle to the ppgtt vm of ctx so that the context
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* destruction will unbind the obj from the ppgtt vm in question.
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*/
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ctx = drm_intel_gem_context_create(data->bufmgr);
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igt_assert(ctx);
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exec_nop(data, fb[i&1].gem_handle, ctx);
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drm_intel_gem_context_destroy(ctx);
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/* Force a context switch to make sure ctx gets destroyed for real. */
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exec_nop(data, fb[i&1].gem_handle, NULL);
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gem_sync(data->drm_fd, fb[i&1].gem_handle);
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/*
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* Make only the current fb has a fence and
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* the next fb will pick a new fence. Assuming
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* all fences are associated with an object, the
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* kernel will always pick a fence with pin_count==0.
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*/
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touch_fences(data);
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/*
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* Pin the new buffer and unpin the old buffer from display. If
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* the kernel is buggy the ppgtt unbind will have dropped the
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* fence for the old buffer, and now the display code will try
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* to unpin only to find no fence there. So the pin_count will leak.
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*/
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igt_plane_set_fb(primary, &fb[!(i&1)]);
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igt_display_commit(display);
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igt_print_activity();
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}
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igt_plane_set_fb(primary, NULL);
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igt_output_set_pipe(output, PIPE_ANY);
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igt_display_commit(display);
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igt_remove_fb(data->drm_fd, &fb[1]);
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igt_remove_fb(data->drm_fd, &fb[0]);
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igt_info("\n");
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}
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static void run_test(data_t *data)
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{
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igt_display_t *display = &data->display;
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igt_output_t *output;
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enum pipe p;
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for_each_pipe_with_valid_output(display, p, output) {
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run_single_test(data, p, output);
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return; /* one time ought to be enough */
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}
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igt_skip("no valid crtc/connector combinations found\n");
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}
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igt_simple_main
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{
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drm_intel_context *ctx;
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data_t data = {};
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igt_skip_on_simulation();
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data.drm_fd = drm_open_driver_master(DRIVER_INTEL);
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igt_require_gem(data.drm_fd);
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data.devid = intel_get_drm_devid(data.drm_fd);
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kmstest_set_vt_graphics_mode();
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data.bufmgr = drm_intel_bufmgr_gem_init(data.drm_fd, 4096);
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igt_assert(data.bufmgr);
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drm_intel_bufmgr_gem_enable_reuse(data.bufmgr);
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igt_display_require(&data.display, data.drm_fd);
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ctx = drm_intel_gem_context_create(data.bufmgr);
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igt_require(ctx);
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drm_intel_gem_context_destroy(ctx);
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alloc_fence_objs(&data);
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run_test(&data);
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free_fence_objs(&data);
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drm_intel_bufmgr_destroy(data.bufmgr);
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igt_display_fini(&data.display);
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}
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