599 lines
14 KiB
ArmAsm
599 lines
14 KiB
ArmAsm
@/*****************************************************************************
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@*
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@* Copyright (C) 2012 Ittiam Systems Pvt Ltd, Bangalore
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@*
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@* Licensed under the Apache License, Version 2.0 (the "License");
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@* you may not use this file except in compliance with the License.
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@* You may obtain a copy of the License at:
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@*
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@* http://www.apache.org/licenses/LICENSE-2.0
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@*
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@* Unless required by applicable law or agreed to in writing, software
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@* distributed under the License is distributed on an "AS IS" BASIS,
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@* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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@* See the License for the specific language governing permissions and
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@* limitations under the License.
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@*
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@*****************************************************************************/
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@/**
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@/*******************************************************************************
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@* @file
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@* ihevc_deblk_luma_vert.s
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@*
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@* @brief
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@* contains function definitions for inter prediction interpolation.
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@* functions are coded using neon intrinsics and can be compiled using
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@* rvct
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@*
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@* @author
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@* anand s
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@*
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@* @par list of functions:
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@*
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@*
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@* @remarks
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@* none
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@*
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@*******************************************************************************/
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.equ qp_q_offset, 44
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.equ beta_offset_div2_offset, 48
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.equ tc_offset_div2_offset, 52
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.equ filter_p_offset, 56
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.equ filter_q_offset, 60
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.text
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.align 4
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.extern gai4_ihevc_tc_table
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.extern gai4_ihevc_beta_table
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.globl ihevc_deblk_luma_vert_a9q
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gai4_ihevc_tc_table_addr:
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.long gai4_ihevc_tc_table - ulbl1 - 8
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gai4_ihevc_beta_table_addr:
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.long gai4_ihevc_beta_table - ulbl2 - 8
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.type ihevc_deblk_luma_vert_a9q, %function
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ihevc_deblk_luma_vert_a9q:
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push {r3-r12,lr}
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ldr r4,[sp,#qp_q_offset]
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ldr r5,[sp,#beta_offset_div2_offset]
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add r3,r3,r4
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add r3,r3,#1
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ldr r6, [sp,#tc_offset_div2_offset]
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asr r3,r3,#1
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add r7,r3,r5,lsl #1
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add r3,r3,r6,lsl #1
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cmp r7,#0x33
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movgt r7,#0x33
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bgt l1.56
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cmp r7,#0x0
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movlt r7,#0x0 @ r7 has the beta_index value
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l1.56:
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@ bic r2,r2,#1
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asr r2,r2,#1
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add r3,r3,r2,lsl #1
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cmp r3,#0x35
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movgt r3,#0x35
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bgt l1.88
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cmp r3,#0x0
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movlt r3,#0x0 @ r3 has the tc_index value
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@ qp_luma = (quant_param_p + quant_param_q + 1) >> 1@
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@ beta_indx = clip3(qp_luma + (beta_offset_div2 << 1), 0, 51)@
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@ tc_indx = clip3(qp_luma + (2 * (bs >> 1)) + (tc_offset_div2 << 1), 0, 53)@
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l1.88:
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ldr r2,gai4_ihevc_beta_table_addr
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ulbl2:
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add r2,r2,pc
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vmov.i8 d18,#0x2
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ldr r4,gai4_ihevc_tc_table_addr
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ulbl1:
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add r4,r4,pc
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ldr r5,[r2,r7,lsl #2] @ beta
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vmov.i16 q8,#0x2
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ldr r6,[r4,r3,lsl #2] @ tc
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lsl r8,r6,#1
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cmp r6,#0
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vdup.8 d19,r8
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sub r7,r0,#4
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vmov.i8 d23,#0x3
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beq l1.964
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vld1.8 {d24},[r7],r1
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ldrb r8,[r0,#-3] @ -3 value
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vld1.8 {d1},[r7],r1
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ldrb r10,[r0,#-2] @-2 value
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vld1.8 {d2},[r7],r1
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ldrb r11,[r0,#-1] @-1 value
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vld1.8 {d0},[r7]
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ldrb r12,[r0,#0] @ 0 value
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ldrb r9,[r0,#1] @ 1 value
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vtrn.8 d24,d1
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ldrb r2,[r0,#2] @ 2 value
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vtrn.8 d2,d0
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add r12,r12,r2
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subs r9,r12,r9,lsl #1 @ dq0 value is stored in r9
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rsbmi r9,r9,#0
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@dq0 = abs( pu1_src[2] - 2 * pu1_src[1] + pu1_src[0] )@
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vtrn.16 d24,d2
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add r8,r8,r11
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vtrn.16 d1,d0
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subs r8,r8,r10,lsl #1
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rsbmi r8,r8,#0 @ dp0 value is stored in r8
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@ dp0 = abs( pu1_src[-3] - 2 * pu1_src[-2] + pu1_src[-1] )@
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add r14,r1,r1,lsl #1
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add r14,r0,r14
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vdup.32 d4,d24[1]
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ldrb r2,[r14,#-3] @ -2 value
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vdup.32 d7,d2[1]
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ldrb r10,[r14,#-2] @ -2 value
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vdup.32 d3,d2[0]
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ldrb r11,[r14,#-1] @ -1 value
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vdup.32 d5,d1[1]
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ldrb r12,[r14,#0] @ 0 value
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vdup.32 d6,d1[0]
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ldrb r3,[r14,#1] @ 1 value
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vdup.32 d2,d0[0]
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ldrb r4,[r14,#2] @ 2 value
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add r12,r12,r4
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subs r12,r12,r3,lsl #1 @ dq3value is stored in r12
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rsbmi r12,r12,#0
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@ dq3 = abs( pu1_src[3 * src_strd + 2] - 2 * pu1_src[3 * src_strd + 1]+ pu1_src[3 * src_strd + 0] )@
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add r2,r2,r11
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subs r11,r2,r10,lsl #1
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rsbmi r11,r11,#0 @ dp3 value is stored in r8
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@ dp3 = abs( pu1_src[3 * src_strd - 3] - 2 * pu1_src[3 * src_strd - 2] + pu1_src[3 * src_strd - 1] )@
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add r3,r8,r9 @ r3 has the d0 value
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add r4,r11,r12 @ r4 has the d3 value
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@ d0 = dp0 + dq0@
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@ d3 = dp3 + dq3@
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add r14,r8,r11 @ r13 has the value dp
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add r12,r12,r9 @ r12 has the value dq
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@ dp = dp0 + dp3@
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@ dq = dq0 + dq3@
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add r11, r3, r4 @ r3 has the value d
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@ d = d0 + d3@
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cmp r11,r5
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vdup.32 d22,d0[1]
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bge l1.964
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@ if(d < beta)
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@ registers which cannont be altered : r3,r4 r5,r6,r12,r13,r0,r1,r11
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@ registers for use: r2,r7,r8,r9,r10,
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vqsub.u8 d30,d7,d19
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asr r10,r5,#2
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vqadd.u8 d31,d7,d19
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cmp r10,r3,lsl #1
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vaddl.u8 q0,d5,d4
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ble l1.336
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ldrb r2,[r0,#-4]
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vaddw.u8 q0,q0,d2
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ldrb r7,[r0,#-1]
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vmull.u8 q10,d7,d23
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ldrb r3,[r0,#0]
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vmlal.u8 q10,d22,d18
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ldrb r8,[r0,#3]
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@ ubfx r7,r2,#24,#8 @ has the -1 value
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@ and r2,#0xff @ has the -4 value
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@ ubfx r8,r3,#24,#8 @ has the 3 value
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@ and r3,#0xff @ r4 has the 0 value
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vadd.i16 q10,q10,q0
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subs r8,r8,r3
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vrshrn.i16 d22,q10,#3
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rsbmi r8,r8,#0
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subs r2,r2,r7
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vmin.u8 d21,d22,d31
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rsbmi r2,r2,#0
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vmax.u8 d22,d21,d30
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add r8,r8,r2
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vaddl.u8 q10,d7,d3
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cmp r8,r5,asr #3
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vmla.i16 q10,q0,q8
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bge l1.336
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vaddw.u8 q0,q0,d7
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subs r7,r3,r7
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vrshrn.i16 d20,q10,#3
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rsbmi r7,r7,#0
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vrshrn.i16 d0,q0,#2
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mov r10,#5
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vqadd.u8 d30,d5,d19
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mul r10,r10,r6
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vqsub.u8 d31,d5,d19
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add r10,#1
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cmp r7,r10,asr #1
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bge l1.336
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@ if( (2 * d3 < (beta >> 2)&& ( abs(pu1_src[3] - pu1_src[0]) + abs(pu1_src[-1] - pu1_src[-4]) < (beta >> 3) )
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@ && abs(pu1_src[0] - pu1_src[-1]) < ( (5 * tc + 1) >> 1 ) )
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asr r10,r5,#2
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vqsub.u8 d25,d4,d19
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cmp r10,r4,lsl #1
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vqadd.u8 d21,d4,d19
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ble l1.336
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vmin.u8 d26,d20,d21
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add r4,r1,r1,lsl #1
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add r4,r4,r0
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vmax.u8 d20,d26,d25
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ldrb r2,[r4,#-4]
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vmin.u8 d19,d0,d30
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ldrb r7,[r4,#-1]
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vmax.u8 d21,d19,d31
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ldrb r3,[r4,#0]
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lsl r10,r6,#1
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ldrb r8,[r4,#3]
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@ ubfx r7,r2,#24,#8 @ has the -1 value
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@ and r2,#0xff @ has the -4 value
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@ ubfx r8,r3,#24,#8 @ has the 3 value
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@ and r3,#0xff @ r4 has the 0 value
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vaddl.u8 q0,d2,d3
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vdup.8 d19,r10
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subs r8,r8,r3
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vaddw.u8 q0,q0,d4
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rsbmi r8,r8,#0
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vqadd.u8 d30,d2,d19
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subs r2,r2,r7
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vqsub.u8 d31,d2,d19
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rsbmi r2,r2,#0
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vaddl.u8 q13,d5,d6
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add r8,r8,r2
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vmla.i16 q13,q0,q8
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cmp r8,r5,asr #3
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bge l1.336
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vrshrn.i16 d26,q13,#3
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subs r7,r3,r7
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vqadd.u8 d27,d3,d19
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rsbmi r7,r7,#0
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vqsub.u8 d28,d3,d19
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mov r10,#5
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vmin.u8 d16,d26,d30
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mul r10,r10,r6
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add r10,#1
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cmp r7,r10,asr #1
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vmax.u8 d26,d16,d31
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bge l1.336
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vqadd.u8 d30,d6,d19
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mov r2,#2
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ldr r4,[sp,#filter_p_offset] @ loading the filter_flag_p
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vqsub.u8 d31,d6,d19
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ldr r5,[sp,#filter_q_offset] @ loading the filter_flag_q
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b end_dep_deq_decision
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@ r2 has the value of de
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@ r6 has teh value of tc
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@ r5 has the value of beta
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@ r14 has the value of dp
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@ r12 has the value of dq
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@ r0 has the value of source address
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@ r1 has the src stride
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l1.336:
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mov r2,#1
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l1.424:
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mov r11,r5
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ldr r4,[sp,#filter_p_offset] @ loading the filter_flag_p
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ldr r5,[sp,#filter_q_offset] @ loading the filter_flag_q
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cmp r6,#1
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moveq r9,#0
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moveq r10,#0
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beq end_dep_deq_decision
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and r7,r4,r5
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cmp r7,#1
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beq both_flags_set
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cmp r4,#0
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beq set_flag_dep_zero
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add r8,r11,r11,asr #1
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mov r10,#0
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asr r8,#3
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cmp r8,r14
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movgt r9,#1
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movle r9,#0
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b end_dep_deq_decision
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set_flag_dep_zero:
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add r8,r11,r11,asr #1
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mov r9,#0
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asr r8,#3
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cmp r8,r12
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movgt r10,#1
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movle r10,#0
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b end_dep_deq_decision
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both_flags_set:
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add r8,r11,r11,asr #1
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asr r8,#3
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cmp r8,r14
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movgt r9,#1
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movle r9,#0
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cmp r8,r12
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movgt r10,#1
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movle r10,#0
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end_dep_deq_decision:
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@r0=source address
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@r1=stride
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@ r2 =de
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@ r4=flag p
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@r5= flag q
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@r6 =tc
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@ r9 =dep
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@ r10=deq
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@ b l1.964
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cmp r2,#2
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@ r4 has the value of de
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bne l1.968
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cmp r5,#0
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beq l1.780
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@ r5 has the flag of q
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add r3,r0,#2
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vst1.8 {d22[0]},[r3],r1
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vst1.8 {d22[1]},[r3],r1
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vst1.8 {d22[2]},[r3],r1
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vst1.8 {d22[3]},[r3]
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add r3,r0,r1
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vtrn.8 d20,d21
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vst1.16 {d20[0]},[r0]
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vst1.16 {d21[0]},[r3],r1
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vst1.16 {d20[1]},[r3],r1
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vst1.16 {d21[1]},[r3]
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l1.780:
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cmp r4,#0
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beq l1.964
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@ r5 has the flag p
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vdup.32 d7,d24[0]
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sub r3,r0,#1
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vaddw.u8 q8,q0,d6
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add r7,r3,r1
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vrshrn.i16 d2,q8,#2
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vst1.8 {d26[0]},[r3]
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sub r0,r0,#3
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vmin.u8 d16,d2,d27
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vst1.8 {d26[1]},[r7],r1
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vmull.u8 q1,d6,d23
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vmlal.u8 q1,d7,d18
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vst1.8 {d26[2]},[r7],r1
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vmax.u8 d5,d16,d28
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vst1.8 {d26[3]},[r7]
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vadd.i16 q0,q1,q0
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vrshrn.i16 d0,q0,#3
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vmin.u8 d1,d0,d30
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vmax.u8 d0,d1,d31
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vtrn.8 d0,d5
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vst1.16 {d0[0]},[r0],r1
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vst1.16 {d5[0]},[r0],r1
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vst1.16 {d0[1]},[r0],r1
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vst1.16 {d5[1]},[r0]
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l1.964:
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pop {r3-r12,pc}
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l1.968:
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vmov.i16 q0,#0x9
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rsb r11,r6,#0
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cmp r4,#0
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@ checks for the flag p
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vmov.i16 q8,#0x3
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vmov.i8 d24,#0x1
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vdup.8 d30,r11
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and r11,r6,#0xff
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vdup.8 d31,r11
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vsubl.u8 q9,d4,d2
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vmul.i16 q9,q9,q0
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vsubl.u8 q0,d5,d3
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vmul.i16 q8,q0,q8
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vsub.i16 q8,q9,q8
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vrshr.s16 q8,q8,#4
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@ delta = ( 9 * (pu1_src[0] - pu1_src[-1]) - 3 * (pu1_src[1] - pu1_src[-2]) + 8 ) >> 4@
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vabs.s16 q0,q8
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vmovn.i16 d0,q0
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@ storing the absolute values of delta in d0
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vqmovn.s16 d16,q8
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@ storing the clipped values of delta in d16
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vmov.i8 d1,#0xa
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vdup.8 d21,r11
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vmul.i8 d1,d1,d21
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@ d1 stores the value (10 * tc)
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@if(abs(delta) < 10 * tc)
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vmin.s8 d18,d16,d31
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vmax.s8 d20,d18,d30
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@ delta = clip3(delta, -tc, tc)@
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vmovl.s8 q8,d20
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vmovl.u8 q9,d2
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vadd.i16 q9,q9,q8
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vqmovun.s16 d22,q9
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vmovl.u8 q9,d4
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vsub.i16 q8,q9,q8
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vqmovun.s16 d23,q8
|
|
@ tmp_p0 = clip_u8(pu1_src[-1] + delta)@
|
|
@ tmp_q0 = clip_u8(pu1_src[0] - delta)@
|
|
beq l1.1272
|
|
|
|
|
|
|
|
cmp r9,#1
|
|
bne l1.1212
|
|
@ checks for the flag dep
|
|
|
|
asr r3,r6,#1
|
|
|
|
|
|
vaddl.u8 q8,d6,d2
|
|
vaddw.u8 q8,q8,d24
|
|
vdup.8 d18,r3
|
|
rsb r3,r3,#0
|
|
vdup.8 d19,r3
|
|
vshr.u16 q8,q8,#1
|
|
vmovn.i16 d16,q8
|
|
|
|
vsubl.u8 q8,d16,d3
|
|
vaddw.s8 q8,q8,d20
|
|
vshr.s16 q8,q8,#1
|
|
vqmovn.s16 d16,q8
|
|
|
|
vmin.s8 d17,d16,d18
|
|
vmax.s8 d16,d19,d17
|
|
|
|
|
|
|
|
|
|
vmovl.u8 q9,d3
|
|
vmovl.s8 q8,d16
|
|
vadd.i16 q8,q9,q8
|
|
|
|
vqmovun.s16 d16,q8
|
|
vmov d30,d3
|
|
vcge.u8 d3,d0,d1
|
|
|
|
|
|
vbsl d3,d30,d16
|
|
l1.1212:
|
|
vdup.8 d16,r11
|
|
sub r12,r0,#3
|
|
sub r3,r0,#1
|
|
@ vmul.i8 d16,d16,d1
|
|
vtrn.8 d6,d3
|
|
vst1.16 {d6[0]},[r12],r1
|
|
vcge.u8 d16,d0,d1
|
|
vst1.16 {d3[0]},[r12],r1
|
|
vbsl d16,d2,d22
|
|
vst1.8 {d16[0]},[r3],r1
|
|
vst1.8 {d16[1]},[r3],r1
|
|
vst1.16 {d6[1]},[r12],r1
|
|
vst1.8 {d16[2]},[r3],r1
|
|
vst1.16 {d3[1]},[r12]
|
|
vst1.8 {d16[3]},[r3]
|
|
l1.1272:
|
|
cmp r5,#0
|
|
beq l1.964
|
|
@ checks for the flag q
|
|
cmp r10,#1
|
|
bne l1.1412
|
|
@ checks for the flag deq
|
|
vmov d2,d7
|
|
asr r3,r6,#1
|
|
|
|
vdup.8 d6,r3
|
|
rsb r3,r3,#0
|
|
vdup.8 d16,r3
|
|
vaddl.u8 q1,d2,d4
|
|
vaddw.u8 q1,q1,d24
|
|
vshr.u16 q1,q1,#1
|
|
vmovn.i16 d2,q1
|
|
|
|
vsubl.u8 q1,d2,d5
|
|
vsubw.s8 q1,q1,d20
|
|
vshr.s16 q1,q1,#1
|
|
vqmovn.s16 d3,q1
|
|
|
|
vmin.s8 d2,d3,d6
|
|
vmax.s8 d3,d16,d2
|
|
@ vdup.8 d6,r2
|
|
@ vmul.i8 d6,d6,d1
|
|
|
|
|
|
|
|
vmovl.u8 q8,d5
|
|
vmovl.s8 q1,d3
|
|
vadd.i16 q1,q8,q1
|
|
vqmovun.s16 d3,q1
|
|
vmov d30,d5
|
|
vcge.u8 d5,d0,d1
|
|
|
|
|
|
vbsl d5,d30,d3
|
|
l1.1412:
|
|
@ vdup.8 d2,r2
|
|
add r3,r0,#2
|
|
add r11,r3,r1
|
|
@ vmul.i8 d1,d2,d1
|
|
vst1.8 {d7[0]},[r3]
|
|
vst1.8 {d7[1]},[r11],r1
|
|
vst1.8 {d7[2]},[r11],r1
|
|
vcge.u8 d0,d0,d1
|
|
vst1.8 {d7[3]},[r11]
|
|
vbsl d0,d4,d23
|
|
vtrn.8 d0,d5
|
|
vst1.16 {d0[0]},[r0],r1
|
|
vst1.16 {d5[0]},[r0],r1
|
|
vst1.16 {d0[1]},[r0],r1
|
|
vst1.16 {d5[1]},[r0]
|
|
pop {r3-r12,pc}
|
|
|
|
|
|
|