313 lines
7.5 KiB
ArmAsm
313 lines
7.5 KiB
ArmAsm
///*****************************************************************************
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//*
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//* Copyright (C) 2012 Ittiam Systems Pvt Ltd, Bangalore
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//*
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//* Licensed under the Apache License, Version 2.0 (the "License");
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//* you may not use this file except in compliance with the License.
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//* You may obtain a copy of the License at:
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//*
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//* http://www.apache.org/licenses/LICENSE-2.0
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//*
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//* Unless required by applicable law or agreed to in writing, software
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//* distributed under the License is distributed on an "AS IS" BASIS,
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//* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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//* See the License for the specific language governing permissions and
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//* limitations under the License.
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//*
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//*****************************************************************************/
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///**
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//*******************************************************************************
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//* @file
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//* ihevc_intra_pred_luma_mode2_neon.s
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//*
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//* @brief
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//* contains function definitions for intra prediction dc filtering.
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//* functions are coded using neon intrinsics and can be compiled using
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//* rvct
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//*
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//* @author
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//* yogeswaran rs
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//*
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//* @par list of functions:
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//*
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//*
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//* @remarks
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//* none
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//*
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//*******************************************************************************
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//*/
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///**
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//*******************************************************************************
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//*
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//* @brief
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//* luma intraprediction filter for dc input
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//*
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//* @par description:
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//*
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//* @param[in] pu1_ref
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//* uword8 pointer to the source
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//*
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//* @param[out] pu1_dst
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//* uword8 pointer to the destination
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//*
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//* @param[in] src_strd
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//* integer source stride
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//*
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//* @param[in] dst_strd
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//* integer destination stride
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//*
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//* @param[in] pi1_coeff
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//* word8 pointer to the planar coefficients
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//*
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//* @param[in] nt
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//* size of tranform block
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//*
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//* @param[in] mode
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//* type of filtering
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//*
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//* @returns
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//*
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//* @remarks
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//* none
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//*
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//*******************************************************************************
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//*/
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//void ihevc_intra_pred_luma_mode2(uword8 *pu1_ref,
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// word32 src_strd,
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// uword8 *pu1_dst,
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// word32 dst_strd,
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// word32 nt,
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// word32 mode)
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//
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//**************variables vs registers*****************************************
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//x0 => *pu1_ref
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//x1 => src_strd
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//x2 => *pu1_dst
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//x3 => dst_strd
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//stack contents from #40
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// nt
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// mode
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// pi1_coeff
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.text
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.align 4
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.include "ihevc_neon_macros.s"
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.globl ihevc_intra_pred_chroma_mode2_av8
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.type ihevc_intra_pred_chroma_mode2_av8, %function
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ihevc_intra_pred_chroma_mode2_av8:
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// stmfd sp!, {x4-x12, x14} //stack stores the values of the arguments
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push_v_regs
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stp x19, x20,[sp,#-16]!
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mov x8,#-4
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cmp x4,#4
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beq mode2_4
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add x0,x0,x4,lsl #2
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sub x0,x0,#0x12 //src[1]
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sub x10,x0,#2
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prologue_cpy_32:
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ld2 {v0.8b, v1.8b},[x0],x8
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mov x11,x4
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rev64 v16.8b, v0.8b
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rev64 v17.8b, v1.8b
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ld2 {v2.8b, v3.8b},[x10],x8
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mov x6, x2
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ld2 {v4.8b, v5.8b},[x0],x8
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ld2 {v6.8b, v7.8b},[x10],x8
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lsr x1, x4, #3
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ld2 {v8.8b, v9.8b},[x0],x8
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ld2 {v10.8b, v11.8b},[x10],x8
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ld2 {v12.8b, v13.8b},[x0],x8
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mul x1, x4, x1
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ld2 {v14.8b, v15.8b},[x10],x8
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add x7,x6,x3
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rev64 v18.8b, v2.8b
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rev64 v19.8b, v3.8b
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lsl x5, x3, #2
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rev64 v20.8b, v4.8b
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rev64 v21.8b, v5.8b
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add x9,x7,x3
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rev64 v22.8b, v6.8b
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rev64 v23.8b, v7.8b
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rev64 v24.8b, v8.8b
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rev64 v25.8b, v9.8b
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rev64 v26.8b, v10.8b
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subs x1,x1,#8
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rev64 v27.8b, v11.8b
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rev64 v28.8b, v12.8b
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rev64 v29.8b, v13.8b
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rev64 v30.8b, v14.8b
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add x14,x9,x3
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rev64 v31.8b, v15.8b
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beq epilogue_mode2
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sub x12,x4,#8
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kernel_mode2:
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st2 {v16.8b, v17.8b},[x6],x5
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st2 {v18.8b, v19.8b},[x7],x5
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subs x11,x11,#8
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st2 {v20.8b, v21.8b},[x9],x5
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st2 {v22.8b, v23.8b},[x14],x5
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st2 {v24.8b, v25.8b},[x6],x5
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add x20,x2,#16
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csel x2, x20, x2,gt
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st2 {v26.8b, v27.8b},[x7],x5
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st2 {v28.8b, v29.8b},[x9],x5
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st2 {v30.8b, v31.8b},[x14],x5
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ld2 {v0.8b, v1.8b},[x0],x8
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csel x11, x4, x11,le
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ld2 {v2.8b, v3.8b},[x10],x8
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ld2 {v4.8b, v5.8b},[x0],x8
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add x20, x2, x3, lsl #2
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csel x2, x20, x2,le
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ld2 {v6.8b, v7.8b},[x10],x8
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rev64 v16.8b, v0.8b
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ld2 {v8.8b, v9.8b},[x0],x8
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ld2 {v10.8b, v11.8b},[x10],x8
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sub x20, x6,#16
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csel x2, x20, x2,le
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ld2 {v12.8b, v13.8b},[x0],x8
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rev64 v17.8b, v1.8b
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ld2 {v14.8b, v15.8b},[x10],x8
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subs x12,x12,#8
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mov x6, x2
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add x20, x0, x4,lsl #1
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csel x0, x20, x0,le
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add x7, x6, x3
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rev64 v18.8b, v2.8b
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sub x20, x0, #16
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csel x0, x20, x0,le
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rev64 v19.8b, v3.8b
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rev64 v20.8b, v4.8b
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csel x12, x4, x12,le
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rev64 v21.8b, v5.8b
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rev64 v22.8b, v6.8b
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add x9, x7, x3
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rev64 v23.8b, v7.8b
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rev64 v24.8b, v8.8b
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sub x10,x0,#2
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rev64 v25.8b, v9.8b
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rev64 v26.8b, v10.8b
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subs x1, x1, #8
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rev64 v27.8b, v11.8b
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rev64 v28.8b, v12.8b
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rev64 v29.8b, v13.8b
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rev64 v30.8b, v14.8b
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add x14, x9, x3
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rev64 v31.8b, v15.8b
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bne kernel_mode2
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epilogue_mode2:
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st2 {v16.8b, v17.8b},[x6],x5
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st2 {v18.8b, v19.8b},[x7],x5
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st2 {v20.8b, v21.8b},[x9],x5
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st2 {v22.8b, v23.8b},[x14],x5
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st2 {v24.8b, v25.8b},[x6],x5
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st2 {v26.8b, v27.8b},[x7],x5
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st2 {v28.8b, v29.8b},[x9],x5
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st2 {v30.8b, v31.8b},[x14],x5
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b end_func
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mode2_4:
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lsl x12,x4,#1
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add x0,x0,x12
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sub x0,x0,#2
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ld2 {v12.8b, v13.8b},[x0],x8
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shl d0, d12,#32
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add x10,x0,#2
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shl d1, d13,#32
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rev64 v0.8b, v0.8b
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ld2 {v14.8b, v15.8b},[x10],x8
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shl d2, d14,#32
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rev64 v1.8b, v1.8b
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shl d3, d15,#32
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zip1 v0.8b, v0.8b, v1.8b
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zip2 v1.8b, v0.8b, v1.8b
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st1 {v0.8b},[x2],x3
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rev64 v2.8b, v2.8b
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ld2 {v16.8b, v17.8b},[x0],x8
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shl d4, d16,#32
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rev64 v3.8b, v3.8b
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shl d5, d17,#32
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zip1 v2.8b, v2.8b, v3.8b
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zip2 v3.8b, v2.8b, v3.8b
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rev64 v4.8b, v4.8b
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rev64 v5.8b, v5.8b
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st1 {v2.8b},[x2],x3
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ld2 {v18.8b, v19.8b},[x10],x8
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shl d6, d18,#32
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zip1 v4.8b, v4.8b, v5.8b
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zip2 v5.8b, v4.8b, v5.8b
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shl d7, d19,#32
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rev64 v6.8b, v6.8b
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st1 {v4.8b},[x2],x3
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rev64 v7.8b, v7.8b
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zip1 v6.8b, v6.8b, v7.8b
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zip2 v7.8b, v6.8b, v7.8b
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st1 {v6.8b},[x2],x3
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end_func:
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// ldmfd sp!,{x4-x12,x15} //reload the registers from sp
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ldp x19, x20,[sp],#16
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pop_v_regs
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ret
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