433 lines
11 KiB
ArmAsm
433 lines
11 KiB
ArmAsm
///*****************************************************************************
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//*
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//* Copyright (C) 2012 Ittiam Systems Pvt Ltd, Bangalore
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//*
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//* Licensed under the Apache License, Version 2.0 (the "License");
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//* you may not use this file except in compliance with the License.
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//* You may obtain a copy of the License at:
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//*
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//* http://www.apache.org/licenses/LICENSE-2.0
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//*
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//* Unless required by applicable law or agreed to in writing, software
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//* distributed under the License is distributed on an "AS IS" BASIS,
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//* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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//* See the License for the specific language governing permissions and
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//* limitations under the License.
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//*
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//*****************************************************************************/
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///**
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//*******************************************************************************
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//* @file
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//* ihevc_intra_pred_filters_vert.s
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//*
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//* @brief
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//* contains function definitions for intra prediction dc filtering.
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//* functions are coded using neon intrinsics and can be compiled using
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//* rvct
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//*
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//* @author
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//* akshaya mukund
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//*
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//* @par list of functions:
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//*
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//*
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//* @remarks
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//* none
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//*
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//*******************************************************************************
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//*/
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///**
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//*******************************************************************************
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//*
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//* @brief
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//* luma intraprediction filter for dc input
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//*
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//* @par description:
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//*
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//* @param[in] pu1_ref
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//* uword8 pointer to the source
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//*
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//* @param[out] pu1_dst
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//* uword8 pointer to the destination
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//*
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//* @param[in] src_strd
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//* integer source stride
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//*
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//* @param[in] dst_strd
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//* integer destination stride
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//*
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//* @param[in] nt
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//* size of tranform block
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//*
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//* @param[in] mode
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//* type of filtering
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//*
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//* @returns
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//*
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//* @remarks
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//* none
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//*
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//*******************************************************************************
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//*/
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//void ihevc_intra_pred_luma_ver(uword8* pu1_ref,
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// word32 src_strd,
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// uword8* pu1_dst,
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// word32 dst_strd,
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// word32 nt,
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// word32 mode)
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//
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//**************variables vs registers*****************************************
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//x0 => *pu1_ref
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//x1 => src_strd
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//x2 => *pu1_dst
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//x3 => dst_strd
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//stack contents from #40
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// nt
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// mode
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.text
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.align 4
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.include "ihevc_neon_macros.s"
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.globl ihevc_intra_pred_luma_ver_av8
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.type ihevc_intra_pred_luma_ver_av8, %function
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ihevc_intra_pred_luma_ver_av8:
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// stmfd sp!, {x4-x12, x14} //stack stores the values of the arguments
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stp x19, x20,[sp,#-16]!
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lsl x5, x4, #1 //2nt
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cmp x4, #16
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beq blk_16
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blt blk_4_8
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add x5, x5, #1 //2nt+1
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add x6, x0, x5 //&src[2nt+1]
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copy_32:
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add x5, x2, x3
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ld1 {v20.8b, v21.8b}, [x6],#16 //16 loads (col 0:15)
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add x8, x5, x3
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add x10, x8, x3
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ld1 {v22.8b, v23.8b}, [x6] //16 loads (col 16:31)
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lsl x11, x3, #2
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sub x11, x11, #16
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st1 {v20.8b, v21.8b}, [x2],#16
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st1 {v20.8b, v21.8b}, [x5],#16
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st1 {v20.8b, v21.8b}, [x8],#16
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st1 {v20.8b, v21.8b}, [x10],#16
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st1 {v22.8b, v23.8b}, [x2], x11
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st1 {v22.8b, v23.8b}, [x5], x11
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st1 {v22.8b, v23.8b}, [x8], x11
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st1 {v22.8b, v23.8b}, [x10], x11
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subs x4, x4, #8
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kernel_copy_32:
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st1 {v20.8b, v21.8b}, [x2],#16
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st1 {v20.8b, v21.8b}, [x5],#16
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st1 {v20.8b, v21.8b}, [x8],#16
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st1 {v20.8b, v21.8b}, [x10],#16
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st1 {v22.8b, v23.8b}, [x2], x11
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st1 {v22.8b, v23.8b}, [x5], x11
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st1 {v22.8b, v23.8b}, [x8], x11
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st1 {v22.8b, v23.8b}, [x10], x11
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subs x4, x4, #8
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st1 {v20.8b, v21.8b}, [x2],#16
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st1 {v20.8b, v21.8b}, [x5],#16
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st1 {v20.8b, v21.8b}, [x8],#16
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st1 {v20.8b, v21.8b}, [x10],#16
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st1 {v22.8b, v23.8b}, [x2], x11
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st1 {v22.8b, v23.8b}, [x5], x11
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st1 {v22.8b, v23.8b}, [x8], x11
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st1 {v22.8b, v23.8b}, [x10], x11
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bne kernel_copy_32
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st1 {v20.8b, v21.8b}, [x2],#16
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st1 {v20.8b, v21.8b}, [x5],#16
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st1 {v20.8b, v21.8b}, [x8],#16
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st1 {v20.8b, v21.8b}, [x10],#16
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st1 {v22.8b, v23.8b}, [x2], x11
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st1 {v22.8b, v23.8b}, [x5], x11
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st1 {v22.8b, v23.8b}, [x8], x11
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st1 {v22.8b, v23.8b}, [x10], x11
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b end_func
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blk_16:
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add x6, x0, x5 //&src[2nt]
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ldrb w11, [x6], #1 //src[2nt]
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sxtw x11,w11
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dup v22.16b,w11 //src[2nt]
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ldrb w12, [x6] //src[2nt+1]
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sxtw x12,w12
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ld1 {v16.8b, v17.8b}, [x6] //ld for repl to cols src[2nt+1+col(0:15)] (0 ignored for stores)
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sub x6, x6, #17 //subtract -9 to take it to src[2nt-1-row(15)]
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dup v24.16b,w12 //src[2nt+1]
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dup v30.8h,w12
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lsl x5, x3, #3 //8*stride
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ld1 {v26.16b}, [x6],#16 //load src[2nt-1-row](rows 0:15)
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add x5, x2, x5 //x5 ->
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movi d18, #0x00000000000000ff
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uhsub v26.16b, v26.16b , v22.16b //(src[2nt-1-row] - src[2nt])>>1
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//vsubl.u8 q0, d26, d22
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//vsubl.u8 q14, d27, d22
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//vshr.s16 q0, q0, #1
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//vshr.s16 q14, q14, #1
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mov v19.d[0],v17.d[0]
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//vaddl.s8 q0, d24, d26
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sxtl v0.8h, v26.8b
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sxtl2 v28.8h, v26.16b
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sqadd v0.8h, v0.8h , v30.8h
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sqadd v28.8h, v28.8h , v30.8h
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movi d3, #0x00000000000000ff
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//vaddl.s8 q1, d25, d27
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sqxtun v24.8b, v28.8h
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sqxtun2 v24.16b, v0.8h
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//vmovn.u16 d25, q0
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//vmovn.u16 d24, q1
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rev64 v24.16b, v24.16b
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mov v25.d[0], v24.d[1]
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mov v4.d[0],v17.d[0]
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bsl v18.8b, v24.8b , v16.8b //only select row values from q12(predpixel)
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bsl v3.8b, v25.8b , v16.8b
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movi d1, #0x00000000000000ff
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mov v2.d[0],v17.d[0]
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movi d6, #0x00000000000000ff
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mov v7.d[0],v17.d[0]
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st1 {v18.8b, v19.8b}, [x2], x3
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sshr d24, d24,#8
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st1 {v3.8b, v4.8b}, [x5], x3
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sshr d25, d25,#8
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bsl v1.8b, v24.8b , v16.8b
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bsl v6.8b, v25.8b , v16.8b
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st1 {v1.8b, v2.8b}, [x2], x3
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sshr d24, d24,#8
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st1 {v6.8b, v7.8b}, [x5], x3
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sshr d25, d25,#8
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subs x4, x4,#8
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movi d18, #0x00000000000000ff
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//vmov.i64 d19, d17
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movi d3, #0x00000000000000ff
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//vmov.i64 d11, d17
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loop_16:
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movi d1, #0x00000000000000ff
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movi d6, #0x00000000000000ff
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bsl v18.8b, v24.8b , v16.8b //only select row values from q12(predpixel)
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bsl v3.8b, v25.8b , v16.8b
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st1 {v18.8b, v19.8b}, [x2], x3
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sshr d24, d24,#8
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st1 {v3.8b, v4.8b}, [x5], x3
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sshr d25, d25,#8
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movi d18, #0x00000000000000ff
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movi d3, #0x00000000000000ff
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bsl v1.8b, v24.8b , v16.8b
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bsl v6.8b, v25.8b , v16.8b
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st1 {v1.8b, v2.8b}, [x2], x3
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sshr d24, d24,#8
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st1 {v6.8b, v7.8b}, [x5], x3
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sshr d25, d25,#8
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subs x4, x4, #4
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bne loop_16
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movi d1, #0x00000000000000ff
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movi d6, #0x00000000000000ff
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bsl v18.8b, v24.8b , v16.8b //only select row values from q12(predpixel)
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bsl v3.8b, v25.8b , v16.8b
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st1 {v18.8b, v19.8b}, [x2], x3
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sshr d24, d24,#8
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st1 {v3.8b, v4.8b}, [x5], x3
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sshr d25, d25,#8
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bsl v1.8b, v24.8b , v16.8b
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bsl v6.8b, v25.8b , v16.8b
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st1 {v1.8b, v2.8b}, [x2], x3
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st1 {v6.8b, v7.8b}, [x5], x3
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b end_func
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blk_4_8:
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movi d4, #0x00000000000000ff
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add x6, x0, x5 //&src[2nt]
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movi d3, #0x00000000000000ff
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ldrb w11, [x6], #1 //src[2nt]
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sxtw x11,w11
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dup v22.8b,w11 //src[2nt]
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ldrb w12, [x6] //src[2nt+1]
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sxtw x12,w12
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ld1 {v16.8b},[x6] //ld for repl to cols src[2nt+1+col(0:3 or 0:7)](0 ignored for st)
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sub x6, x6, #9 //subtract -9 to take it to src[2nt-1-row(15)]
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dup v24.8b,w12 //src[2nt+1]
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dup v30.8h,w12
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ld1 {v26.8b},[x6],#8 //load src[2nt-1-row](rows 0:15)
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movi d18, #0x00000000000000ff
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uhsub v26.8b, v26.8b , v22.8b //(src[2nt-1-row] - src[2nt])>>1
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//vsubl.u8 q13, d26, d22
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//vshr.s16 q13, q13, #1
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movi d19, #0x00000000000000ff
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sxtl v26.8h, v26.8b
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//vaddl.s8 q0, d24, d26
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sqadd v0.8h, v26.8h , v30.8h
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sqxtun v24.8b, v0.8h
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//vmovn.s16 d24, q0
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rev64 v24.8b, v24.8b
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cmp x4, #4
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beq blk_4
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bsl v18.8b, v24.8b , v16.8b //only select row values from q12(predpixel)
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st1 {v18.8b},[x2], x3
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sshr d24, d24,#8
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movi d18, #0x00000000000000ff
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bsl v19.8b, v24.8b , v16.8b
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st1 {v19.8b},[x2], x3
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sshr d24, d24,#8
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movi d19, #0x00000000000000ff
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bsl v3.8b, v24.8b , v16.8b
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st1 {v3.8b},[x2], x3
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sshr d24, d24,#8
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movi d3, #0x00000000000000ff
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bsl v4.8b, v24.8b , v16.8b
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st1 {v4.8b},[x2], x3
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sshr d24, d24,#8
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movi d4, #0x00000000000000ff
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bsl v18.8b, v24.8b , v16.8b //only select row values from q12(predpixel)
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st1 {v18.8b},[x2], x3
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sshr d24, d24,#8
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bsl v19.8b, v24.8b , v16.8b
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st1 {v19.8b},[x2], x3
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sshr d24, d24,#8
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bsl v3.8b, v24.8b , v16.8b
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st1 {v3.8b},[x2], x3
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sshr d24, d24,#8
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bsl v4.8b, v24.8b , v16.8b
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st1 {v4.8b},[x2], x3
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sshr d24, d24,#8
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b end_func
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blk_4:
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bsl v18.8b, v24.8b , v16.8b //only select row values from q12(predpixel)
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st1 {v18.s}[0],[x2], x3
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sshr d24, d24,#8
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bsl v19.8b, v24.8b , v16.8b
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st1 {v19.s}[0],[x2], x3
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sshr d24, d24,#8
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bsl v3.8b, v24.8b , v16.8b
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st1 {v3.s}[0],[x2], x3
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sshr d24, d24,#8
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bsl v4.8b, v24.8b , v16.8b
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st1 {v4.s}[0],[x2], x3
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end_func:
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// ldmfd sp!,{x4-x12,x15} //reload the registers from sp
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ldp x19, x20,[sp],#16
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ret
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