304 lines
6.4 KiB
ArmAsm
304 lines
6.4 KiB
ArmAsm
@/*****************************************************************************
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@*
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@* Copyright (C) 2012 Ittiam Systems Pvt Ltd, Bangalore
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@*
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@* Licensed under the Apache License, Version 2.0 (the "License");
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@* you may not use this file except in compliance with the License.
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@* You may obtain a copy of the License at:
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@*
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@* http://www.apache.org/licenses/LICENSE-2.0
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@*
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@* Unless required by applicable law or agreed to in writing, software
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@* distributed under the License is distributed on an "AS IS" BASIS,
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@* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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@* See the License for the specific language governing permissions and
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@* limitations under the License.
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@*
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@*****************************************************************************/
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@/**
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@*******************************************************************************
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@* @file
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@* ihevc_intra_pred_luma_mode2_neon.s
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@*
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@* @brief
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@* contains function definitions for intra prediction dc filtering.
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@* functions are coded using neon intrinsics and can be compiled using
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@* rvct
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@*
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@* @author
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@* yogeswaran rs
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@*
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@* @par list of functions:
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@*
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@*
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@* @remarks
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@* none
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@*
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@*******************************************************************************
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@*/
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@/**
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@*******************************************************************************
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@*
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@* @brief
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@* luma intraprediction filter for dc input
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@*
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@* @par description:
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@*
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@* @param[in] pu1_ref
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@* uword8 pointer to the source
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@*
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@* @param[out] pu1_dst
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@* uword8 pointer to the destination
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@*
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@* @param[in] src_strd
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@* integer source stride
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@*
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@* @param[in] dst_strd
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@* integer destination stride
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@*
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@* @param[in] pi1_coeff
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@* word8 pointer to the planar coefficients
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@*
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@* @param[in] nt
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@* size of tranform block
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@*
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@* @param[in] mode
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@* type of filtering
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@*
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@* @returns
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@*
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@* @remarks
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@* none
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@*
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@*******************************************************************************
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@*/
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@void ihevc_intra_pred_luma_mode2(uword8 *pu1_ref,
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@ word32 src_strd,
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@ uword8 *pu1_dst,
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@ word32 dst_strd,
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@ word32 nt,
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@ word32 mode)
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@
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@**************variables vs registers*****************************************
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@r0 => *pu1_ref
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@r1 => src_strd
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@r2 => *pu1_dst
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@r3 => dst_strd
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@stack contents from #104
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@ nt
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@ mode
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@ pi1_coeff
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.equ nt_offset, 104
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.text
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.align 4
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.globl ihevc_intra_pred_chroma_mode2_a9q
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.type ihevc_intra_pred_chroma_mode2_a9q, %function
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ihevc_intra_pred_chroma_mode2_a9q:
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stmfd sp!, {r4-r12, r14} @stack stores the values of the arguments
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vpush {d8 - d15}
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ldr r4,[sp,#nt_offset] @loads nt
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mov r8,#-4
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cmp r4,#4
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beq mode2_4
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add r0,r0,r4,lsl #2
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sub r0,r0,#0x12 @src[1]
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add r10,r0,#-2
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prologue_cpy_32:
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vld2.8 {d0,d1},[r0],r8
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mov r11,r4
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vrev64.8 d16,d0
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vrev64.8 d17,d1
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vld2.8 {d2,d3},[r10],r8
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mov r6, r2
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vld2.8 {d4,d5},[r0],r8
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vld2.8 {d6,d7},[r10],r8
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lsr r1, r4, #3
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vld2.8 {d8,d9},[r0],r8
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vld2.8 {d10,d11},[r10],r8
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vld2.8 {d12,d13},[r0],r8
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mul r1, r4, r1
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vld2.8 {d14,d15},[r10],r8
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add r7,r6,r3
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vrev64.8 d18,d2
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vrev64.8 d19,d3
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lsl r5, r3, #2
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vrev64.8 d20,d4
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vrev64.8 d21,d5
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add r9,r7,r3
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vrev64.8 d22,d6
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vrev64.8 d23,d7
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vrev64.8 d24,d8
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vrev64.8 d25,d9
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vrev64.8 d26,d10
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subs r1,r1,#8
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vrev64.8 d27,d11
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vrev64.8 d28,d12
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vrev64.8 d29,d13
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vrev64.8 d30,d14
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add r14,r9,r3
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vrev64.8 d31,d15
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beq epilogue_mode2
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sub r12,r4,#8
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kernel_mode2:
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vst2.8 {d16,d17},[r6],r5
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vst2.8 {d18,d19},[r7],r5
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subs r11,r11,#8
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vst2.8 {d20,d21},[r9],r5
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vst2.8 {d22,d23},[r14],r5
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vst2.8 {d24,d25},[r6],r5
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addgt r2,r2,#16
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vst2.8 {d26,d27},[r7],r5
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vst2.8 {d28,d29},[r9],r5
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vst2.8 {d30,d31},[r14],r5
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vld2.8 {d0,d1},[r0],r8
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movle r11,r4
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vld2.8 {d2,d3},[r10],r8
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vld2.8 {d4,d5},[r0],r8
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addle r2, r2, r3, lsl #2
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vld2.8 {d6,d7},[r10],r8
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vrev64.8 d16,d0
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vld2.8 {d8,d9},[r0],r8
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vld2.8 {d10,d11},[r10],r8
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suble r2, r6,#16
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vld2.8 {d12,d13},[r0],r8
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vrev64.8 d17,d1
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vld2.8 {d14,d15},[r10],r8
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subs r12,r12,#8
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mov r6, r2
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addle r0, r0, r4,lsl #1
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add r7, r6, r3
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vrev64.8 d18,d2
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suble r0, r0, #16
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vrev64.8 d19,d3
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vrev64.8 d20,d4
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movle r12,r4
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vrev64.8 d21,d5
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vrev64.8 d22,d6
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add r9, r7, r3
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vrev64.8 d23,d7
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vrev64.8 d24,d8
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add r10,r0,#-2
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vrev64.8 d25,d9
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vrev64.8 d26,d10
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subs r1, r1, #8
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vrev64.8 d27,d11
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vrev64.8 d28,d12
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vrev64.8 d29,d13
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vrev64.8 d30,d14
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add r14, r9, r3
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vrev64.8 d31,d15
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bne kernel_mode2
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epilogue_mode2:
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vst2.8 {d16,d17},[r6],r5
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vst2.8 {d18,d19},[r7],r5
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vst2.8 {d20,d21},[r9],r5
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vst2.8 {d22,d23},[r14],r5
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vst2.8 {d24,d25},[r6],r5
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vst2.8 {d26,d27},[r7],r5
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vst2.8 {d28,d29},[r9],r5
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vst2.8 {d30,d31},[r14],r5
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b end_func
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mode2_4:
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lsl r12,r4,#1
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add r0,r0,r12
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sub r0,r0,#2
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vld2.8 {d12,d13},[r0],r8
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vshl.i64 d0,d12,#32
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add r10,r0,#2
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vshl.i64 d1,d13,#32
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vrev64.8 d0,d0
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vld2.8 {d14,d15},[r10],r8
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vshl.i64 d2,d14,#32
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vrev64.8 d1,d1
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vshl.i64 d3,d15,#32
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vzip.8 d0,d1
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vst1.8 {d0},[r2],r3
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vrev64.8 d2,d2
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vld2.8 {d16,d17},[r0],r8
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vshl.i64 d4,d16,#32
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vrev64.8 d3,d3
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vshl.i64 d5,d17,#32
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vzip.8 d2,d3
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vrev64.8 d4,d4
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vrev64.8 d5,d5
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vst1.8 {d2},[r2],r3
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vld2.8 {d18,d19},[r10],r8
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vshl.i64 d6,d18,#32
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vzip.8 d4,d5
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vshl.i64 d7,d19,#32
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vrev64.8 d6,d6
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vst1.8 {d4},[r2],r3
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vrev64.8 d7,d7
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vzip.8 d6,d7
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vst1.8 {d6},[r2],r3
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end_func:
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vpop {d8 - d15}
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ldmfd sp!,{r4-r12,r15} @reload the registers from sp
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