1143 lines
26 KiB
ArmAsm
1143 lines
26 KiB
ArmAsm
@/*****************************************************************************
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@*
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@* Copyright (C) 2012 Ittiam Systems Pvt Ltd, Bangalore
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@*
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@* Licensed under the Apache License, Version 2.0 (the "License");
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@* you may not use this file except in compliance with the License.
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@* You may obtain a copy of the License at:
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@*
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@* http://www.apache.org/licenses/LICENSE-2.0
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@*
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@* Unless required by applicable law or agreed to in writing, software
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@* distributed under the License is distributed on an "AS IS" BASIS,
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@* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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@* See the License for the specific language governing permissions and
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@* limitations under the License.
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@*
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@*****************************************************************************/
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@/**
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@ *******************************************************************************
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@ * @file
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@ * ihevc_itrans_recon_8x8_neon.s
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@ *
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@ * @brief
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@ * contains function definitions for single stage inverse transform
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@ *
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@ * @author
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@ * anand s
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@ *
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@ * @par list of functions:
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@ * - ihevc_itrans_recon_16x16()
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@ *
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@ * @remarks
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@ * none
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@ *
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@ *******************************************************************************
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@*/
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@/**
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@ *******************************************************************************
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@ *
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@ * @brief
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@ * this function performs inverse transform and reconstruction for 8x8
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@ * input block
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@ *
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@ * @par description:
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@ * performs inverse transform and adds the prediction data and clips output
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@ * to 8 bit
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@ *
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@ * @param[in] pi2_src
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@ * input 16x16 coefficients
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@ *
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@ * @param[in] pi2_tmp
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@ * temporary 16x16 buffer for storing inverse
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@ *
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@ * transform
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@ * 1st stage output
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@ *
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@ * @param[in] pu1_pred
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@ * prediction 16x16 block
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@ *
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@ * @param[out] pu1_dst
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@ * output 8x8 block
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@ *
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@ * @param[in] src_strd
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@ * input stride
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@ *
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@ * @param[in] pred_strd
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@ * prediction stride
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@ *
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@ * @param[in] dst_strd
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@ * output stride
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@ *
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@ * @param[in] shift
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@ * output shift
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@ *
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@ * @param[in] r12
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@ * zero columns in pi2_src
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@ *
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@ * @returns void
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@ *
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@ * @remarks
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@ * none
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@ *
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@ *******************************************************************************
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@ */
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@void ihevc_itrans_recon_16x16(word16 *pi2_src,
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@ word16 *pi2_tmp,
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@ uword8 *pu1_pred,
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@ uword8 *pu1_dst,
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@ word32 src_strd,
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@ word32 pred_strd,
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@ word32 dst_strd,
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@ word32 r12
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@ word32 r11 )
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@**************variables vs registers*************************
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@ r0 => *pi2_src
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@ r1 => *pi2_tmp
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@ r2 => *pu1_pred
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@ r3 => *pu1_dst
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@ src_strd
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@ pred_strd
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@ dst_strd
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@ r12
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@ r11
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.equ src_stride_offset, 104
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.equ pred_stride_offset, 108
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.equ out_stride_offset, 112
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.equ zero_cols_offset, 116
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.equ zero_rows_offset, 120
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.text
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.align 4
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.set shift_stage1_idct , 7
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.set shift_stage2_idct , 12
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@#define zero_cols r12
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@#define zero_rows r11
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.globl ihevc_itrans_recon_16x16_a9q
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.extern g_ai2_ihevc_trans_16_transpose
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g_ai2_ihevc_trans_16_transpose_addr:
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.long g_ai2_ihevc_trans_16_transpose - ulbl1 - 8
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.type ihevc_itrans_recon_16x16_a9q, %function
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ihevc_itrans_recon_16x16_a9q:
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stmfd sp!,{r4-r12,lr}
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vpush {d8 - d15}
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ldr r6,[sp,#src_stride_offset] @ src stride
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ldr r12,[sp,#zero_cols_offset]
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ldr r11,[sp,#zero_rows_offset]
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ldr r14,g_ai2_ihevc_trans_16_transpose_addr
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ulbl1:
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add r14,r14,pc
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vld1.16 {d0,d1,d2,d3},[r14] @//d0,d1 are used for storing the constant data
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movw r7,#0xffff
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and r12,r12,r7
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and r11,r11,r7
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mov r6,r6,lsl #1 @ x sizeof(word16)
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add r9,r0,r6, lsl #1 @ 2 rows
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add r10,r6,r6, lsl #1 @ 3 rows
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add r5,r6,r6,lsl #2
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movw r7,#0xfff0
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cmp r12,r7
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bge zero_12cols_decision
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cmp r12,#0xff00
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bge zero_8cols_decision
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mov r14,#4
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cmp r11,r7
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rsbge r10,r6,#0
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cmp r11,#0xff00
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movge r8,r5
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rsbge r8,r8,#0
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movlt r8,r10
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add r5,r5,r6,lsl #3
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rsb r5,r5,#0
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b first_stage_top_four_bottom_four
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zero_12cols_decision:
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mov r14,#1
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cmp r11,#0xff00
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movge r8,r5
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movlt r8,r10
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add r5,r5,r6,lsl #3
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rsb r5,r5,#0
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b first_stage_top_four_bottom_four
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zero_8cols_decision:
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mov r14,#2
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mov r8,r5
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rsb r8,r8,#0
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cmp r11,#0xff00
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movlt r8,r10
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add r5,r5,r6,lsl #3
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rsb r5,r5,#0
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cmp r11,r7
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rsbge r10,r6,#0
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b first_stage_top_four_bottom_four
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@d0[0]= 64 d2[0]=64
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@d0[1]= 90 d2[1]=57
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@d0[2]= 89 d2[2]=50
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@d0[3]= 87 d2[3]=43
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@d1[0]= 83 d3[0]=36
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@d1[1]= 80 d3[1]=25
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@d1[2]= 75 d3[2]=18
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@d1[3]= 70 d3[3]=9
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first_stage:
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add r0,r0,#8
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add r9,r9,#8
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first_stage_top_four_bottom_four:
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vld1.16 d10,[r0],r6
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vld1.16 d11,[r9],r6
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vld1.16 d6,[r0],r10
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vld1.16 d7,[r9],r10
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cmp r11,r7
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bge skip_load4rows
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vld1.16 d4,[r0],r6
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vld1.16 d5,[r9],r6
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vld1.16 d8,[r0],r8
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vld1.16 d9,[r9],r8
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@ registers used: q0,q1,q3,q5,q2,q4
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@ d10 =r0
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@d6= r1
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@d11=r2
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@d7=r3
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skip_load4rows:
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vmull.s16 q12,d6,d0[1] @// y1 * cos1(part of b0)
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vmull.s16 q13,d6,d0[3] @// y1 * cos3(part of b1)
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vmull.s16 q14,d6,d1[1] @// y1 * sin3(part of b2)
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vmull.s16 q15,d6,d1[3] @// y1 * sin1(part of b3)
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vmlal.s16 q12,d7,d0[3] @// y1 * cos1 + y3 * cos3(part of b0)
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vmlal.s16 q13,d7,d2[1] @// y1 * cos3 - y3 * sin1(part of b1)
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vmlal.s16 q14,d7,d3[3] @// y1 * sin3 - y3 * cos1(part of b2)
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vmlsl.s16 q15,d7,d2[3] @// y1 * sin1 - y3 * sin3(part of b3)
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vmull.s16 q6,d10,d0[0]
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vmlal.s16 q6,d11,d0[2]
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vmull.s16 q7,d10,d0[0]
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vmlal.s16 q7,d11,d1[2]
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vmull.s16 q8,d10,d0[0]
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vmlal.s16 q8,d11,d2[2]
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vmull.s16 q9,d10,d0[0]
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vmlal.s16 q9,d11,d3[2]
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bge skip_last12rows_kernel1
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vmlal.s16 q12,d8,d1[1]
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vmlal.s16 q13,d8,d3[3]
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vmlsl.s16 q14,d8,d1[3]
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vmlsl.s16 q15,d8,d0[3]
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vmlal.s16 q12,d9,d1[3]
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vmlsl.s16 q13,d9,d2[3]
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vmlsl.s16 q14,d9,d0[3]
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vmlal.s16 q15,d9,d3[3]
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vmlal.s16 q6,d4,d1[0]
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vmlal.s16 q6,d5,d1[2]
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vmlal.s16 q7,d4,d3[0]
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vmlsl.s16 q7,d5,d3[2]
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vmlsl.s16 q8,d4,d3[0]
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vmlsl.s16 q8,d5,d0[2]
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vmlsl.s16 q9,d4,d1[0]
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vmlsl.s16 q9,d5,d2[2]
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@d0[0]= 64 d2[0]=64
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@d0[1]= 90 d2[1]=57
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@d0[2]= 89 d2[2]=50
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@d0[3]= 87 d2[3]=43
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@d1[0]= 83 d3[0]=36
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@d1[1]= 80 d3[1]=25
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@d1[2]= 75 d3[2]=18
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@d1[3]= 70 d3[3]=9
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cmp r11,#0xff00
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bge skip_last12rows_kernel1
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vld1.16 d10,[r0],r6
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vld1.16 d11,[r9],r6
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vld1.16 d6,[r0],r10
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vld1.16 d7,[r9],r10
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vld1.16 d4,[r0],r6
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vld1.16 d5,[r9],r6
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vld1.16 d8,[r0],r5
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vld1.16 d9,[r9],r5
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vmlal.s16 q12,d6,d2[1] @// y1 * cos1(part of b0)
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vmlsl.s16 q13,d6,d1[1] @// y1 * cos3(part of b1)
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vmlsl.s16 q14,d6,d3[1] @// y1 * sin3(part of b2)
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vmlal.s16 q15,d6,d0[1] @// y1 * sin1(part of b3)
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vmlal.s16 q12,d7,d2[3] @// y1 * cos1 + y3 * cos3(part of b0)
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vmlsl.s16 q13,d7,d0[1] @// y1 * cos3 - y3 * sin1(part of b1)
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vmlal.s16 q14,d7,d2[1] @// y1 * sin3 - y3 * cos1(part of b2)
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vmlal.s16 q15,d7,d3[1] @// y1 * sin1 - y3 * sin3(part of b3)
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vmlal.s16 q12,d8,d3[1]
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vmlsl.s16 q13,d8,d1[3]
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vmlal.s16 q14,d8,d0[1]
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vmlsl.s16 q15,d8,d1[1]
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vmlal.s16 q12,d9,d3[3]
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vmlsl.s16 q13,d9,d3[1]
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vmlal.s16 q14,d9,d2[3]
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vmlsl.s16 q15,d9,d2[1]
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vmlal.s16 q6,d10,d0[0]
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vmlal.s16 q6,d11,d2[2]
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vmlal.s16 q6,d4,d3[0]
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vmlal.s16 q6,d5,d3[2]
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vmlsl.s16 q7,d10,d0[0]
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vmlsl.s16 q7,d11,d0[2]
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vmlsl.s16 q7,d4,d1[0]
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vmlsl.s16 q7,d5,d2[2]
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vmlsl.s16 q8,d10,d0[0]
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vmlal.s16 q8,d11,d3[2]
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vmlal.s16 q8,d4,d1[0]
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vmlal.s16 q8,d5,d1[2]
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vmlal.s16 q9,d10,d0[0]
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vmlal.s16 q9,d11,d1[2]
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vmlsl.s16 q9,d4,d3[0]
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vmlsl.s16 q9,d5,d0[2]
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skip_last12rows_kernel1:
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vadd.s32 q10,q6,q12
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vsub.s32 q11,q6,q12
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vadd.s32 q6,q7,q13
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vsub.s32 q12,q7,q13
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vadd.s32 q7,q8,q14
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vsub.s32 q13,q8,q14
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vadd.s32 q8,q9,q15
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vsub.s32 q14,q9,q15
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vqrshrn.s32 d30,q10,#shift_stage1_idct @// r0 = (a0 + b0 + rnd) >> 7(shift_stage1_idct)
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vqrshrn.s32 d19,q11,#shift_stage1_idct @// r7 = (a0 - b0 + rnd) >> 7(shift_stage1_idct)
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vqrshrn.s32 d31,q7,#shift_stage1_idct @// r2 = (a2 + b2 + rnd) >> 7(shift_stage1_idct)
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vqrshrn.s32 d18,q13,#shift_stage1_idct @// r5 = (a2 - b2 + rnd) >> 7(shift_stage1_idct)
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vqrshrn.s32 d12,q6,#shift_stage1_idct @// r1 = (a1 + b1 + rnd) >> 7(shift_stage1_idct)
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vqrshrn.s32 d15,q12,#shift_stage1_idct @// r6 = (a1 - b1 + rnd) >> 7(shift_stage1_idct)
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vqrshrn.s32 d13,q8,#shift_stage1_idct @// r3 = (a3 + b3 + rnd) >> 7(shift_stage1_idct)
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vqrshrn.s32 d14,q14,#shift_stage1_idct @// r4 = (a3 - b3 + rnd) >> 7(shift_stage1_idct)
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vst1.16 {d30,d31},[r1]!
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vst1.16 {d18,d19},[r1]!
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sub r1,r1,#32
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bge skip_stage1_kernel_load
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first_stage_middle_eight:
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vld1.16 d10,[r0],r6
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vld1.16 d11,[r9],r6
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vld1.16 d6,[r0],r10
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vld1.16 d7,[r9],r10
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vld1.16 d4,[r0],r6
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vld1.16 d5,[r9],r6
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vld1.16 d8,[r0],r8
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vld1.16 d9,[r9],r8
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skip_stage1_kernel_load:
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vmull.s16 q12,d6,d2[1] @// y1 * cos1(part of b0)
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vmull.s16 q13,d6,d2[3] @// y1 * cos3(part of b1)
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vmull.s16 q14,d6,d3[1] @// y1 * sin3(part of b2)
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vmull.s16 q15,d6,d3[3] @// y1 * sin1(part of b3)
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vmlsl.s16 q12,d7,d1[1] @// y1 * cos1 + y3 * cos3(part of b0)
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vmlsl.s16 q13,d7,d0[1] @// y1 * cos3 - y3 * sin1(part of b1)
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vmlsl.s16 q14,d7,d1[3] @// y1 * sin3 - y3 * cos1(part of b2)
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vmlsl.s16 q15,d7,d3[1] @// y1 * sin1 - y3 * sin3(part of b3)
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vmull.s16 q11,d10,d0[0]
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vmlsl.s16 q11,d11,d3[2]
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vmull.s16 q10,d10,d0[0]
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vmlsl.s16 q10,d11,d2[2]
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vmull.s16 q8,d10,d0[0]
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vmlsl.s16 q8,d11,d1[2]
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vmull.s16 q9,d10,d0[0]
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vmlsl.s16 q9,d11,d0[2]
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cmp r11,r7
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bge skip_last12rows_kernel2
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vmlsl.s16 q12,d8,d3[1]
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vmlal.s16 q13,d8,d2[1]
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vmlal.s16 q14,d8,d0[1]
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vmlal.s16 q15,d8,d2[3]
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vmlal.s16 q12,d9,d0[1]
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vmlal.s16 q13,d9,d3[1]
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vmlsl.s16 q14,d9,d1[1]
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vmlsl.s16 q15,d9,d2[1]
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vmlsl.s16 q11,d4,d1[0]
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vmlal.s16 q11,d5,d2[2]
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vmlsl.s16 q10,d4,d3[0]
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vmlal.s16 q10,d5,d0[2]
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vmlal.s16 q8,d4,d3[0]
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vmlal.s16 q8,d5,d3[2]
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vmlal.s16 q9,d4,d1[0]
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vmlsl.s16 q9,d5,d1[2]
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@d0[0]= 64 d2[0]=64
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@d0[1]= 90 d2[1]=57
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@d0[2]= 89 d2[2]=50
|
|
@d0[3]= 87 d2[3]=43
|
|
@d1[0]= 83 d3[0]=36
|
|
@d1[1]= 80 d3[1]=25
|
|
@d1[2]= 75 d3[2]=18
|
|
@d1[3]= 70 d3[3]=9
|
|
cmp r11,#0xff00
|
|
bge skip_last12rows_kernel2
|
|
|
|
vld1.16 d10,[r0],r6
|
|
vld1.16 d11,[r9],r6
|
|
vld1.16 d6,[r0],r10
|
|
vld1.16 d7,[r9],r10
|
|
vld1.16 d4,[r0],r6
|
|
vld1.16 d5,[r9],r6
|
|
vld1.16 d8,[r0],r5
|
|
vld1.16 d9,[r9],r5
|
|
|
|
|
|
vmlsl.s16 q12,d6,d3[3] @// y1 * cos1(part of b0)
|
|
vmlsl.s16 q13,d6,d0[3] @// y1 * cos3(part of b1)
|
|
vmlal.s16 q14,d6,d2[3] @// y1 * sin3(part of b2)
|
|
vmlal.s16 q15,d6,d1[3] @// y1 * sin1(part of b3)
|
|
|
|
vmlsl.s16 q12,d7,d0[3] @// y1 * cos1 + y3 * cos3(part of b0)
|
|
vmlal.s16 q13,d7,d1[3] @// y1 * cos3 - y3 * sin1(part of b1)
|
|
vmlal.s16 q14,d7,d3[3] @// y1 * sin3 - y3 * cos1(part of b2)
|
|
vmlsl.s16 q15,d7,d1[1] @// y1 * sin1 - y3 * sin3(part of b3)
|
|
|
|
|
|
vmlal.s16 q12,d8,d2[3]
|
|
vmlal.s16 q13,d8,d3[3]
|
|
vmlsl.s16 q14,d8,d2[1]
|
|
vmlal.s16 q15,d8,d0[3]
|
|
|
|
|
|
vmlal.s16 q12,d9,d1[3]
|
|
vmlsl.s16 q13,d9,d1[1]
|
|
vmlal.s16 q14,d9,d0[3]
|
|
vmlsl.s16 q15,d9,d0[1]
|
|
|
|
|
|
|
|
|
|
vmlal.s16 q11,d10,d0[0]
|
|
vmlsl.s16 q11,d11,d1[2]
|
|
vmlsl.s16 q11,d4,d3[0]
|
|
vmlal.s16 q11,d5,d0[2]
|
|
|
|
|
|
|
|
vmlsl.s16 q10,d10,d0[0]
|
|
vmlsl.s16 q10,d11,d3[2]
|
|
vmlal.s16 q10,d4,d1[0]
|
|
vmlsl.s16 q10,d5,d1[2]
|
|
|
|
|
|
vmlsl.s16 q8,d10,d0[0]
|
|
vmlal.s16 q8,d11,d0[2]
|
|
vmlsl.s16 q8,d4,d1[0]
|
|
vmlal.s16 q8,d5,d2[2]
|
|
|
|
|
|
|
|
vmlal.s16 q9,d10,d0[0]
|
|
vmlsl.s16 q9,d11,d2[2]
|
|
vmlal.s16 q9,d4,d3[0]
|
|
vmlsl.s16 q9,d5,d3[2]
|
|
|
|
skip_last12rows_kernel2:
|
|
|
|
vadd.s32 q2,q11,q12
|
|
vsub.s32 q11,q11,q12
|
|
|
|
vadd.s32 q3,q10,q13
|
|
vsub.s32 q12,q10,q13
|
|
|
|
vadd.s32 q5,q8,q14
|
|
vsub.s32 q13,q8,q14
|
|
|
|
|
|
vadd.s32 q8,q9,q15
|
|
vsub.s32 q14,q9,q15
|
|
|
|
|
|
vqrshrn.s32 d18,q2,#shift_stage1_idct @// r0 = (a0 + b0 + rnd) >> 7(shift_stage1_idct)
|
|
vqrshrn.s32 d31,q11,#shift_stage1_idct @// r7 = (a0 - b0 + rnd) >> 7(shift_stage1_idct)
|
|
vqrshrn.s32 d19,q5,#shift_stage1_idct @// r2 = (a2 + b2 + rnd) >> 7(shift_stage1_idct)
|
|
vqrshrn.s32 d30,q13,#shift_stage1_idct @// r5 = (a2 - b2 + rnd) >> 7(shift_stage1_idct)
|
|
vqrshrn.s32 d20,q3,#shift_stage1_idct @// r1 = (a1 + b1 + rnd) >> 7(shift_stage1_idct)
|
|
vqrshrn.s32 d23,q12,#shift_stage1_idct @// r6 = (a1 - b1 + rnd) >> 7(shift_stage1_idct)
|
|
vqrshrn.s32 d21,q8,#shift_stage1_idct @// r3 = (a3 + b3 + rnd) >> 7(shift_stage1_idct)
|
|
vqrshrn.s32 d22,q14,#shift_stage1_idct @// r4 = (a3 - b3 + rnd) >> 7(shift_stage1_idct)
|
|
|
|
|
|
@ registers used: {q2,q4,q6,q7}, {q9,q15,q10,q11}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
vld1.16 {d4,d5},[r1]!
|
|
vld1.16 {d8,d9},[r1]!
|
|
sub r1,r1,#32
|
|
|
|
@d4=r0
|
|
@d12=r1
|
|
@d5=r2
|
|
@d13=r3
|
|
|
|
@d18=r4
|
|
@d20=r5
|
|
@d19=r6
|
|
@d21=r7
|
|
|
|
@d22=r8
|
|
@d30=r9
|
|
@d23=r10
|
|
@d31=r11
|
|
|
|
@d14=r12
|
|
@d8=r13
|
|
@d15=r14
|
|
@d9=r15
|
|
|
|
|
|
vtrn.16 q2,q6
|
|
vtrn.16 q9,q10
|
|
vtrn.16 q11,q15
|
|
vtrn.16 q7,q4
|
|
|
|
|
|
|
|
vtrn.32 d4,d5
|
|
vtrn.32 d12,d13
|
|
|
|
vtrn.32 d18,d19
|
|
vtrn.32 d20,d21
|
|
|
|
vtrn.32 d22,d23
|
|
vtrn.32 d30,d31
|
|
|
|
vtrn.32 d14,d15
|
|
vtrn.32 d8,d9
|
|
|
|
|
|
@ d4 =r0 1- 4 values
|
|
@ d5 =r2 1- 4 values
|
|
@ d12=r1 1- 4 values
|
|
@ d13=r3 1- 4 values
|
|
|
|
@ d18 =r0 5- 8 values
|
|
@ d19 =r2 5- 8 values
|
|
@ d20=r1 5- 8 values
|
|
@ d21=r3 5- 8 values
|
|
|
|
@ d22 =r0 9- 12 values
|
|
@ d23 =r2 9- 12 values
|
|
@ d30=r1 9- 12 values
|
|
@ d31=r3 9- 12 values
|
|
|
|
@ d14 =r0 13-16 values
|
|
@ d15 =r2 13- 16 values
|
|
@ d8=r1 13- 16 values
|
|
@ d9=r3 13- 16 values
|
|
|
|
|
|
vst1.16 {q2},[r1]!
|
|
vst1.16 {q6},[r1]!
|
|
|
|
vst1.16 {q9},[r1]!
|
|
vst1.16 {q10},[r1]!
|
|
vst1.16 {q11},[r1]!
|
|
vst1.16 {q15},[r1]!
|
|
vst1.16 {q7},[r1]!
|
|
vst1.16 {q4},[r1]!
|
|
|
|
|
|
subs r14,r14,#1
|
|
bne first_stage
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
mov r6,r7
|
|
|
|
ldr r8,[sp,#pred_stride_offset] @ prediction stride
|
|
ldr r7,[sp,#out_stride_offset] @ destination stride
|
|
|
|
mov r10,#16
|
|
|
|
cmp r12,r6
|
|
subge r1,r1,#128
|
|
bge label1
|
|
|
|
cmp r12,#0xff00
|
|
subge r1,r1,#256
|
|
bge label_2
|
|
|
|
sub r1,r1,#512
|
|
rsb r10,r10,#0
|
|
|
|
label_2:
|
|
add r9,r1,#128
|
|
add r11,r9,#128
|
|
add r0,r11,#128
|
|
|
|
|
|
|
|
label1:
|
|
@ mov r6,r1
|
|
|
|
|
|
mov r14,#4
|
|
add r4,r2,r8, lsl #1 @ r4 = r2 + pred_strd * 2 => r4 points to 3rd row of pred data
|
|
add r5,r8,r8, lsl #1 @
|
|
@ add r0,r3,r7, lsl #1 @ r0 points to 3rd row of dest data
|
|
@ add r10,r7,r7, lsl #1 @
|
|
|
|
|
|
|
|
|
|
second_stage:
|
|
vld1.16 {d10,d11},[r1]!
|
|
vld1.16 {d6,d7},[r1],r10
|
|
cmp r12,r6
|
|
bge second_stage_process
|
|
vld1.16 {d4,d5},[r9]!
|
|
vld1.16 {d8,d9},[r9],r10
|
|
|
|
second_stage_process:
|
|
|
|
|
|
vmull.s16 q12,d6,d0[1] @// y1 * cos1(part of b0)
|
|
vmull.s16 q13,d6,d0[3] @// y1 * cos3(part of b1)
|
|
vmull.s16 q14,d6,d1[1] @// y1 * sin3(part of b2)
|
|
vmull.s16 q15,d6,d1[3] @// y1 * sin1(part of b3)
|
|
|
|
vmlal.s16 q12,d7,d0[3] @// y1 * cos1 + y3 * cos3(part of b0)
|
|
vmlal.s16 q13,d7,d2[1] @// y1 * cos3 - y3 * sin1(part of b1)
|
|
vmlal.s16 q14,d7,d3[3] @// y1 * sin3 - y3 * cos1(part of b2)
|
|
vmlsl.s16 q15,d7,d2[3] @// y1 * sin1 - y3 * sin3(part of b3)
|
|
|
|
|
|
vmull.s16 q6,d10,d0[0]
|
|
vmlal.s16 q6,d11,d0[2]
|
|
vmull.s16 q7,d10,d0[0]
|
|
vmlal.s16 q7,d11,d1[2]
|
|
vmull.s16 q8,d10,d0[0]
|
|
vmlal.s16 q8,d11,d2[2]
|
|
vmull.s16 q9,d10,d0[0]
|
|
vmlal.s16 q9,d11,d3[2]
|
|
|
|
bge skip_last8rows_stage2_kernel1
|
|
|
|
vmlal.s16 q12,d8,d1[1]
|
|
vmlal.s16 q13,d8,d3[3]
|
|
vmlsl.s16 q14,d8,d1[3]
|
|
vmlsl.s16 q15,d8,d0[3]
|
|
|
|
|
|
vmlal.s16 q12,d9,d1[3]
|
|
vmlsl.s16 q13,d9,d2[3]
|
|
vmlsl.s16 q14,d9,d0[3]
|
|
vmlal.s16 q15,d9,d3[3]
|
|
|
|
|
|
vmlal.s16 q6,d4,d1[0]
|
|
vmlal.s16 q6,d5,d1[2]
|
|
vmlal.s16 q7,d4,d3[0]
|
|
vmlsl.s16 q7,d5,d3[2]
|
|
vmlsl.s16 q8,d4,d3[0]
|
|
vmlsl.s16 q8,d5,d0[2]
|
|
vmlsl.s16 q9,d4,d1[0]
|
|
vmlsl.s16 q9,d5,d2[2]
|
|
|
|
cmp r12,#0xff00
|
|
bge skip_last8rows_stage2_kernel1
|
|
|
|
|
|
vld1.16 {d10,d11},[r11]!
|
|
vld1.16 {d6,d7},[r11],r10
|
|
vld1.16 {d4,d5},[r0]!
|
|
vld1.16 {d8,d9},[r0],r10
|
|
|
|
|
|
|
|
|
|
|
|
vmlal.s16 q12,d6,d2[1] @// y1 * cos1(part of b0)
|
|
vmlsl.s16 q13,d6,d1[1] @// y1 * cos3(part of b1)
|
|
vmlsl.s16 q14,d6,d3[1] @// y1 * sin3(part of b2)
|
|
vmlal.s16 q15,d6,d0[1] @// y1 * sin1(part of b3)
|
|
|
|
vmlal.s16 q12,d7,d2[3] @// y1 * cos1 + y3 * cos3(part of b0)
|
|
vmlsl.s16 q13,d7,d0[1] @// y1 * cos3 - y3 * sin1(part of b1)
|
|
vmlal.s16 q14,d7,d2[1] @// y1 * sin3 - y3 * cos1(part of b2)
|
|
vmlal.s16 q15,d7,d3[1] @// y1 * sin1 - y3 * sin3(part of b3)
|
|
|
|
|
|
|
|
vmlal.s16 q12,d8,d3[1]
|
|
vmlsl.s16 q13,d8,d1[3]
|
|
vmlal.s16 q14,d8,d0[1]
|
|
vmlsl.s16 q15,d8,d1[1]
|
|
|
|
|
|
vmlal.s16 q12,d9,d3[3]
|
|
vmlsl.s16 q13,d9,d3[1]
|
|
vmlal.s16 q14,d9,d2[3]
|
|
vmlsl.s16 q15,d9,d2[1]
|
|
|
|
|
|
|
|
|
|
|
|
vmlal.s16 q6,d10,d0[0]
|
|
vmlal.s16 q6,d11,d2[2]
|
|
vmlal.s16 q6,d4,d3[0]
|
|
vmlal.s16 q6,d5,d3[2]
|
|
|
|
|
|
|
|
|
|
vmlsl.s16 q7,d10,d0[0]
|
|
vmlsl.s16 q7,d11,d0[2]
|
|
vmlsl.s16 q7,d4,d1[0]
|
|
vmlsl.s16 q7,d5,d2[2]
|
|
|
|
|
|
vmlsl.s16 q8,d10,d0[0]
|
|
vmlal.s16 q8,d11,d3[2]
|
|
vmlal.s16 q8,d4,d1[0]
|
|
vmlal.s16 q8,d5,d1[2]
|
|
|
|
|
|
vmlal.s16 q9,d10,d0[0]
|
|
vmlal.s16 q9,d11,d1[2]
|
|
vmlsl.s16 q9,d4,d3[0]
|
|
vmlsl.s16 q9,d5,d0[2]
|
|
|
|
|
|
|
|
|
|
|
|
|
|
skip_last8rows_stage2_kernel1:
|
|
|
|
|
|
|
|
vadd.s32 q10,q6,q12
|
|
vsub.s32 q11,q6,q12
|
|
|
|
vadd.s32 q6,q7,q13
|
|
vsub.s32 q12,q7,q13
|
|
|
|
vadd.s32 q7,q8,q14
|
|
vsub.s32 q13,q8,q14
|
|
|
|
|
|
vadd.s32 q8,q9,q15
|
|
vsub.s32 q14,q9,q15
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
vqrshrn.s32 d30,q10,#shift_stage2_idct @// r0 = (a0 + b0 + rnd) >> 7(shift_stage1_idct)
|
|
vqrshrn.s32 d19,q11,#shift_stage2_idct @// r7 = (a0 - b0 + rnd) >> 7(shift_stage1_idct)
|
|
vqrshrn.s32 d31,q7,#shift_stage2_idct @// r2 = (a2 + b2 + rnd) >> 7(shift_stage1_idct)
|
|
vqrshrn.s32 d18,q13,#shift_stage2_idct @// r5 = (a2 - b2 + rnd) >> 7(shift_stage1_idct)
|
|
vqrshrn.s32 d12,q6,#shift_stage2_idct @// r1 = (a1 + b1 + rnd) >> 7(shift_stage1_idct)
|
|
vqrshrn.s32 d15,q12,#shift_stage2_idct @// r6 = (a1 - b1 + rnd) >> 7(shift_stage1_idct)
|
|
vqrshrn.s32 d13,q8,#shift_stage2_idct @// r3 = (a3 + b3 + rnd) >> 7(shift_stage1_idct)
|
|
vqrshrn.s32 d14,q14,#shift_stage2_idct @// r4 = (a3 - b3 + rnd) >> 7(shift_stage1_idct)
|
|
|
|
bge skip_stage2_kernel_load
|
|
|
|
@q2,q4,q6,q7 is used
|
|
vld1.16 {d10,d11},[r1]!
|
|
vld1.16 {d6,d7},[r1]!
|
|
vld1.16 {d4,d5},[r9]!
|
|
vld1.16 {d8,d9},[r9]!
|
|
skip_stage2_kernel_load:
|
|
sub r1,r1,#32
|
|
vst1.16 {d30,d31},[r1]!
|
|
vst1.16 {d18,d19},[r1]!
|
|
sub r1,r1,#32
|
|
|
|
vmull.s16 q12,d6,d2[1] @// y1 * cos1(part of b0)
|
|
vmull.s16 q13,d6,d2[3] @// y1 * cos3(part of b1)
|
|
vmull.s16 q14,d6,d3[1] @// y1 * sin3(part of b2)
|
|
vmull.s16 q15,d6,d3[3] @// y1 * sin1(part of b3)
|
|
|
|
vmlsl.s16 q12,d7,d1[1] @// y1 * cos1 + y3 * cos3(part of b0)
|
|
vmlsl.s16 q13,d7,d0[1] @// y1 * cos3 - y3 * sin1(part of b1)
|
|
vmlsl.s16 q14,d7,d1[3] @// y1 * sin3 - y3 * cos1(part of b2)
|
|
vmlsl.s16 q15,d7,d3[1] @// y1 * sin1 - y3 * sin3(part of b3)
|
|
|
|
|
|
vmull.s16 q11,d10,d0[0]
|
|
vmlsl.s16 q11,d11,d3[2]
|
|
vmull.s16 q10,d10,d0[0]
|
|
vmlsl.s16 q10,d11,d2[2]
|
|
vmull.s16 q8,d10,d0[0]
|
|
vmlsl.s16 q8,d11,d1[2]
|
|
vmull.s16 q9,d10,d0[0]
|
|
vmlsl.s16 q9,d11,d0[2]
|
|
|
|
|
|
|
|
cmp r12,r6
|
|
bge skip_last8rows_stage2_kernel2
|
|
|
|
|
|
vmlsl.s16 q12,d8,d3[1]
|
|
vmlal.s16 q13,d8,d2[1]
|
|
vmlal.s16 q14,d8,d0[1]
|
|
vmlal.s16 q15,d8,d2[3]
|
|
|
|
|
|
vmlal.s16 q12,d9,d0[1]
|
|
vmlal.s16 q13,d9,d3[1]
|
|
vmlsl.s16 q14,d9,d1[1]
|
|
vmlsl.s16 q15,d9,d2[1]
|
|
|
|
|
|
|
|
vmlsl.s16 q11,d4,d1[0]
|
|
vmlal.s16 q11,d5,d2[2]
|
|
vmlsl.s16 q10,d4,d3[0]
|
|
vmlal.s16 q10,d5,d0[2]
|
|
vmlal.s16 q8,d4,d3[0]
|
|
vmlal.s16 q8,d5,d3[2]
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vmlal.s16 q9,d4,d1[0]
|
|
vmlsl.s16 q9,d5,d1[2]
|
|
cmp r12,#0xff00
|
|
bge skip_last8rows_stage2_kernel2
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|
|
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vld1.16 {d10,d11},[r11]!
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vld1.16 {d6,d7},[r11]!
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vld1.16 {d4,d5},[r0]!
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vld1.16 {d8,d9},[r0]!
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vmlsl.s16 q12,d6,d3[3] @// y1 * cos1(part of b0)
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vmlsl.s16 q13,d6,d0[3] @// y1 * cos3(part of b1)
|
|
vmlal.s16 q14,d6,d2[3] @// y1 * sin3(part of b2)
|
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vmlal.s16 q15,d6,d1[3] @// y1 * sin1(part of b3)
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|
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vmlsl.s16 q12,d7,d0[3] @// y1 * cos1 + y3 * cos3(part of b0)
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vmlal.s16 q13,d7,d1[3] @// y1 * cos3 - y3 * sin1(part of b1)
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vmlal.s16 q14,d7,d3[3] @// y1 * sin3 - y3 * cos1(part of b2)
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vmlsl.s16 q15,d7,d1[1] @// y1 * sin1 - y3 * sin3(part of b3)
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vmlal.s16 q12,d8,d2[3]
|
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vmlal.s16 q13,d8,d3[3]
|
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vmlsl.s16 q14,d8,d2[1]
|
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vmlal.s16 q15,d8,d0[3]
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|
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|
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vmlal.s16 q12,d9,d1[3]
|
|
vmlsl.s16 q13,d9,d1[1]
|
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vmlal.s16 q14,d9,d0[3]
|
|
vmlsl.s16 q15,d9,d0[1]
|
|
|
|
|
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|
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vmlal.s16 q11,d10,d0[0]
|
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vmlsl.s16 q11,d11,d1[2]
|
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vmlsl.s16 q11,d4,d3[0]
|
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vmlal.s16 q11,d5,d0[2]
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|
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|
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vmlsl.s16 q10,d10,d0[0]
|
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vmlsl.s16 q10,d11,d3[2]
|
|
vmlal.s16 q10,d4,d1[0]
|
|
vmlsl.s16 q10,d5,d1[2]
|
|
|
|
|
|
vmlsl.s16 q8,d10,d0[0]
|
|
vmlal.s16 q8,d11,d0[2]
|
|
vmlsl.s16 q8,d4,d1[0]
|
|
vmlal.s16 q8,d5,d2[2]
|
|
|
|
|
|
|
|
vmlal.s16 q9,d10,d0[0]
|
|
vmlsl.s16 q9,d11,d2[2]
|
|
vmlal.s16 q9,d4,d3[0]
|
|
vmlsl.s16 q9,d5,d3[2]
|
|
|
|
|
|
skip_last8rows_stage2_kernel2:
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|
|
|
|
|
|
|
vadd.s32 q2,q11,q12
|
|
vsub.s32 q11,q11,q12
|
|
|
|
vadd.s32 q3,q10,q13
|
|
vsub.s32 q12,q10,q13
|
|
|
|
vadd.s32 q5,q8,q14
|
|
vsub.s32 q13,q8,q14
|
|
|
|
|
|
vadd.s32 q8,q9,q15
|
|
vsub.s32 q14,q9,q15
|
|
|
|
|
|
vqrshrn.s32 d18,q2,#shift_stage2_idct @// r0 = (a0 + b0 + rnd) >> 7(shift_stage1_idct)
|
|
vqrshrn.s32 d31,q11,#shift_stage2_idct @// r7 = (a0 - b0 + rnd) >> 7(shift_stage1_idct)
|
|
vqrshrn.s32 d19,q5,#shift_stage2_idct @// r2 = (a2 + b2 + rnd) >> 7(shift_stage1_idct)
|
|
vqrshrn.s32 d30,q13,#shift_stage2_idct @// r5 = (a2 - b2 + rnd) >> 7(shift_stage1_idct)
|
|
vqrshrn.s32 d20,q3,#shift_stage2_idct @// r1 = (a1 + b1 + rnd) >> 7(shift_stage1_idct)
|
|
vqrshrn.s32 d23,q12,#shift_stage2_idct @// r6 = (a1 - b1 + rnd) >> 7(shift_stage1_idct)
|
|
vqrshrn.s32 d21,q8,#shift_stage2_idct @// r3 = (a3 + b3 + rnd) >> 7(shift_stage1_idct)
|
|
vqrshrn.s32 d22,q14,#shift_stage2_idct @// r4 = (a3 - b3 + rnd) >> 7(shift_stage1_idct)
|
|
|
|
vld1.16 {d4,d5},[r1]!
|
|
vld1.16 {d8,d9},[r1]!
|
|
|
|
|
|
|
|
@ registers used: {q2,q4,q6,q7}, {q9,q15,q10,q11}
|
|
|
|
@d4=r0
|
|
@d12=r1
|
|
@d5=r2
|
|
@d13=r3
|
|
|
|
@d18=r4
|
|
@d20=r5
|
|
@d19=r6
|
|
@d21=r7
|
|
|
|
@d22=r8
|
|
@d30=r9
|
|
@d23=r10
|
|
@d31=r11
|
|
|
|
@d14=r12
|
|
@d8=r13
|
|
@d15=r14
|
|
@d9=r15
|
|
|
|
|
|
vtrn.16 q2,q6
|
|
vtrn.16 q9,q10
|
|
vtrn.16 q11,q15
|
|
vtrn.16 q7,q4
|
|
|
|
|
|
|
|
vtrn.32 d4,d5
|
|
vtrn.32 d12,d13
|
|
|
|
vtrn.32 d18,d19
|
|
vtrn.32 d20,d21
|
|
|
|
vtrn.32 d22,d23
|
|
vtrn.32 d30,d31
|
|
|
|
vtrn.32 d14,d15
|
|
vtrn.32 d8,d9
|
|
|
|
@ d4 =r0 1- 4 values
|
|
@ d5 =r2 1- 4 values
|
|
@ d12=r1 1- 4 values
|
|
@ d13=r3 1- 4 values
|
|
|
|
@ d18 =r0 5- 8 values
|
|
@ d19 =r2 5- 8 values
|
|
@ d20=r1 5- 8 values
|
|
@ d21=r3 5- 8 values
|
|
|
|
@ d22 =r0 9- 12 values
|
|
@ d23 =r2 9- 12 values
|
|
@ d30=r1 9- 12 values
|
|
@ d31=r3 9- 12 values
|
|
|
|
@ d14 =r0 13-16 values
|
|
@ d15 =r2 13- 16 values
|
|
@ d8=r1 13- 16 values
|
|
@ d9=r3 13- 16 values
|
|
|
|
|
|
vswp d5,d18
|
|
vswp d23,d14
|
|
vswp d13,d20
|
|
vswp d31,d8
|
|
|
|
@ q2: r0 1-8 values
|
|
@ q11: r0 9-16 values
|
|
@ q9 : r2 1-8 values
|
|
@ q7 : r2 9-16 values
|
|
@ q6 : r1 1- 8 values
|
|
@ q10: r3 1-8 values
|
|
@ q15: r1 9-16 values
|
|
@ q4: r3 9-16 values
|
|
|
|
|
|
@ registers free: q8,q14,q12,q13
|
|
|
|
|
|
vld1.8 {d16,d17},[r2],r8
|
|
vld1.8 {d28,d29},[r2],r5
|
|
vld1.8 {d24,d25},[r4],r8
|
|
vld1.8 {d26,d27},[r4],r5
|
|
|
|
|
|
|
|
|
|
vaddw.u8 q2,q2,d16
|
|
vaddw.u8 q11,q11,d17
|
|
vaddw.u8 q6,q6,d28
|
|
vaddw.u8 q15,q15,d29
|
|
vaddw.u8 q9,q9,d24
|
|
vaddw.u8 q7,q7,d25
|
|
vaddw.u8 q10,q10,d26
|
|
vaddw.u8 q4,q4,d27
|
|
|
|
|
|
vqmovun.s16 d16,q2
|
|
vqmovun.s16 d17,q11
|
|
vqmovun.s16 d28,q6
|
|
vqmovun.s16 d29,q15
|
|
vqmovun.s16 d24,q9
|
|
vqmovun.s16 d25,q7
|
|
vqmovun.s16 d26,q10
|
|
vqmovun.s16 d27,q4
|
|
|
|
|
|
|
|
vst1.8 {d16,d17},[r3],r7
|
|
vst1.8 {d28,d29},[r3],r7
|
|
vst1.8 {d24,d25},[r3],r7
|
|
vst1.8 {d26,d27},[r3],r7
|
|
|
|
subs r14,r14,#1
|
|
|
|
|
|
|
|
bne second_stage
|
|
|
|
|
|
vpop {d8 - d15}
|
|
ldmfd sp!,{r4-r12,pc}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|