570 lines
19 KiB
ArmAsm
570 lines
19 KiB
ArmAsm
///*****************************************************************************
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//*
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//* Copyright (C) 2012 Ittiam Systems Pvt Ltd, Bangalore
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//*
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//* Licensed under the Apache License, Version 2.0 (the "License");
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//* you may not use this file except in compliance with the License.
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//* You may obtain a copy of the License at:
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//*
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//* http://www.apache.org/licenses/LICENSE-2.0
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//*
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//* Unless required by applicable law or agreed to in writing, software
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//* distributed under the License is distributed on an "AS IS" BASIS,
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//* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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//* See the License for the specific language governing permissions and
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//* limitations under the License.
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//*
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//*****************************************************************************/
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///**
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//*******************************************************************************
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//* @file
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//* ihevc_intra_pred_filters_planar.s
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//*
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//* @brief
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//* contains function definitions for inter prediction interpolation.
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//* functions are coded using neon intrinsics and can be compiled using
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//* rvct
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//*
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//* @author
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//* akshaya mukund
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//*
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//* @par list of functions:
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//*
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//*
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//* @remarks
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//* none
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//*
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//*******************************************************************************
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//*/
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///**
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//*******************************************************************************
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//*
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//* @brief
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//* luma intraprediction filter for planar input
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//*
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//* @par description:
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//*
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//* @param[in] pu1_ref
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//* uword8 pointer to the source
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//*
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//* @param[out] pu1_dst
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//* uword8 pointer to the destination
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//*
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//* @param[in] src_strd
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//* integer source stride
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//*
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//* @param[in] dst_strd
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//* integer destination stride
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//*
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//* @param[in] pi1_coeff
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//* word8 pointer to the planar coefficients
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//*
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//* @param[in] nt
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//* size of tranform block
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//*
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//* @param[in] mode
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//* type of filtering
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//*
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//* @returns
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//*
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//* @remarks
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//* none
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//*
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//*******************************************************************************
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//*/
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//void ihevc_intra_pred_luma_planar(uword8* pu1_ref,
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// word32 src_strd,
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// uword8* pu1_dst,
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// word32 dst_strd,
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// word32 nt,
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// word32 mode,
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// word32 pi1_coeff)
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//**************variables vs registers*****************************************
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//x0 => *pu1_ref
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//x1 => src_strd
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//x2 => *pu1_dst
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//x3 => dst_strd
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//stack contents from #40
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// nt
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// mode
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// pi1_coeff
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.text
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.align 4
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.include "ihevc_neon_macros.s"
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.globl ihevc_intra_pred_luma_planar_av8
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.extern gau1_ihevc_planar_factor
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.extern gau1_ihevc_planar_factor_1
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.type ihevc_intra_pred_luma_planar_av8, %function
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ihevc_intra_pred_luma_planar_av8:
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// stmfd sp!, {x4-x12, x14} //stack stores the values of the arguments
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stp x19, x20,[sp,#-16]!
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adrp x11, :got:gau1_ihevc_planar_factor //loads table of coeffs
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ldr x11, [x11, #:got_lo12:gau1_ihevc_planar_factor]
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clz w5,w4
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sub x20, x5, #32
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neg x5, x20
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dup v29.8h,w5
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neg v29.8h, v29.8h //shr value (so vneg)
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dup v2.8b,w4 //nt
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dup v16.8h,w4 //nt
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sub x6, x4, #1 //nt-1
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add x6, x6, x0
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ldr w7, [x6]
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sxtw x7,w7
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dup v0.8b,w7 //src[nt-1]
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add x6, x4, x4,lsl #1 //3nt
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add x6, x6, #1 //3nt + 1
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add x6, x6, x0
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ldr w7, [x6]
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sxtw x7,w7
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dup v1.8b,w7 //src[3nt+1]
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add x6, x4, x4 //2nt
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add x14, x6, #1 //2nt+1
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sub x6, x6, #1 //2nt-1
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add x6, x6, x0 //&src[2nt-1]
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add x14, x14, x0 //&src[2nt+1]
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mov x8, #1 //row+1 (row is first 0)
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sub x9, x4, x8 //nt-1-row (row is first 0)
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dup v5.8b,w8 //row + 1
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dup v6.8b,w9 //nt - 1 - row
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mov v7.8b, v5.8b //mov #1 to d7 to used for inc for row+1 and dec for nt-1-row
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add x12, x11, #1 //coeffs (to be reloaded after every row)
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mov x1, x4 //nt (row counter) (dec after every row)
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mov x5, x2 //dst (to be reloaded after every row and inc by dst_strd)
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mov x10, #8 //increment for the coeffs
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mov x0, x14 //&src[2nt+1] (to be reloaded after every row)
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cmp x4, #4
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beq tf_sz_4
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//@ ========== ***************** =====================
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prolog:
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tf_sz_8_16_32:
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mov x7, x4 //column counter (set to no of cols)
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lsr x9, x4, #3 //divide nt by 8
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mul x7, x7, x9 //multiply width * height
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adrp x5, :got:gau1_ihevc_planar_factor_1 //loads table of coeffs
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ldr x5, [x5, #:got_lo12:gau1_ihevc_planar_factor_1]
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sub x6, x6, #7
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mov x8, x2
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lsl x9, x3, #3 //4*stride
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sub x20, x9, #8 //8-4*stride
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neg x9, x20
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mov x10, x4 //nt
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sub x10, x10, #8 //nt - 8
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col_loop_8_16_32:
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ld1 {v17.8b},[x12] //(1-8)load 8 coeffs [col+1]
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dup v27.8h,w4 //(1)
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ld1 {v4.8b},[x6] //(1-8)src[2nt-1-row]
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sub v19.8b, v2.8b , v17.8b //(1-8)[nt-1-col]
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umlal v27.8h, v5.8b, v0.8b //(1)(row+1) * src[nt-1]
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ld1 {v3.8b},[x14] //(1-8)load 8 src[2nt+1+col]
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umlal v27.8h, v17.8b, v1.8b //(1)(col+1) * src[3nt+1]
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dup v20.8b, v4.b[7] //(1)
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umlal v27.8h, v6.8b, v3.8b //(1)(nt-1-row) * src[2nt+1+col]
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dup v21.8b, v4.b[6] //(2)
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umlal v27.8h, v19.8b, v20.8b //(1)(nt-1-col) * src[2nt-1-row]
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dup v30.8h,w4 //(2)
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add v5.8b, v5.8b , v7.8b //(1)
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sub v6.8b, v6.8b , v7.8b //(1)
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dup v22.8b, v4.b[5] //(3)
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umlal v30.8h, v5.8b, v0.8b //(2)
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dup v28.8h,w4 //(3)
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umlal v30.8h, v17.8b, v1.8b //(2)
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umlal v30.8h, v6.8b, v3.8b //(2)
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umlal v30.8h, v19.8b, v21.8b //(2)
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sshl v27.8h, v27.8h, v29.8h //(1)shr
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add v5.8b, v5.8b , v7.8b //(2)
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sub v6.8b, v6.8b , v7.8b //(2)
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xtn v27.8b, v27.8h //(1)
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umlal v28.8h, v5.8b, v0.8b //(3)
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dup v23.8b, v4.b[4] //(4)
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umlal v28.8h, v17.8b, v1.8b //(3)
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dup v25.8h,w4 //(4)
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umlal v28.8h, v6.8b, v3.8b //(3)
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st1 {v27.8b},[x2], x3 //(1)str 8 values
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umlal v28.8h, v19.8b, v22.8b //(3)
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sshl v30.8h, v30.8h, v29.8h //(2)shr
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add v5.8b, v5.8b , v7.8b //(3)
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sub v6.8b, v6.8b , v7.8b //(3)
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xtn v30.8b, v30.8h //(2)
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umlal v25.8h, v5.8b, v0.8b //(4)
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dup v20.8b, v4.b[3] //(5)
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umlal v25.8h, v17.8b, v1.8b //(4)
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dup v16.8h,w4 //(5)
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umlal v25.8h, v6.8b, v3.8b //(4)
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st1 {v30.8b},[x2], x3 //(2)str 8 values
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umlal v25.8h, v19.8b, v23.8b //(4)
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sshl v28.8h, v28.8h, v29.8h //(3)shr
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add v5.8b, v5.8b , v7.8b //(4)
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sub v6.8b, v6.8b , v7.8b //(4)
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xtn v28.8b, v28.8h //(3)
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umlal v16.8h, v5.8b, v0.8b //(5)
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dup v21.8b, v4.b[2] //(6)
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umlal v16.8h, v17.8b, v1.8b //(5)
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dup v18.8h,w4 //(6)
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umlal v16.8h, v6.8b, v3.8b //(5)
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st1 {v28.8b},[x2], x3 //(3)str 8 values
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umlal v16.8h, v19.8b, v20.8b //(5)
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sshl v25.8h, v25.8h, v29.8h //(4)shr
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add v5.8b, v5.8b , v7.8b //(5)
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sub v6.8b, v6.8b , v7.8b //(5)
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xtn v25.8b, v25.8h //(4)
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umlal v18.8h, v5.8b, v0.8b //(6)
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dup v22.8b, v4.b[1] //(7)
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umlal v18.8h, v17.8b, v1.8b //(6)
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dup v26.8h,w4 //(7)
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umlal v18.8h, v6.8b, v3.8b //(6)
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st1 {v25.8b},[x2], x3 //(4)str 8 values
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umlal v18.8h, v19.8b, v21.8b //(6)
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sshl v16.8h, v16.8h, v29.8h //(5)shr
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add v5.8b, v5.8b , v7.8b //(6)
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sub v6.8b, v6.8b , v7.8b //(6)
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xtn v16.8b, v16.8h //(5)
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umlal v26.8h, v5.8b, v0.8b //(7)
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dup v23.8b, v4.b[0] //(8)
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umlal v26.8h, v17.8b, v1.8b //(7)
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dup v24.8h,w4 //(8)
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umlal v26.8h, v6.8b, v3.8b //(7)
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st1 {v16.8b},[x2], x3 //(5)str 8 values
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umlal v26.8h, v19.8b, v22.8b //(7)
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sshl v18.8h, v18.8h, v29.8h //(6)shr
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add v5.8b, v5.8b , v7.8b //(7)
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sub v6.8b, v6.8b , v7.8b //(7)
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xtn v18.8b, v18.8h //(6)
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umlal v24.8h, v5.8b, v0.8b //(8)
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umlal v24.8h, v17.8b, v1.8b //(8)
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umlal v24.8h, v6.8b, v3.8b //(8)
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st1 {v18.8b},[x2], x3 //(6)str 8 values
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umlal v24.8h, v19.8b, v23.8b //(8)
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sshl v26.8h, v26.8h, v29.8h //(7)shr
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subs x7, x7, #8
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beq epilog
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subs x1, x1, #8 //row counter
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add x20, x12, #8 //col inc
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csel x12, x20, x12,gt
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add x20, x14, #8 //also for col inc
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csel x14, x20, x14,gt
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csel x1, x4, x1,le //nt reloaded (refresh the value)
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add x20, x11, #1 //x12 reset
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csel x12, x20, x12,le
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csel x14, x0, x14,le //x14 reset
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ld1 {v17.8b},[x12] //(1n)(1-8)load 8 coeffs [col+1]
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sub x20, x6, #8 //for next set of rows
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csel x6, x20, x6,le
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ld1 {v3.8b},[x14] //(1n)(1-8)load 8 src[2nt+1+col]
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add x20, x5, #8
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csel x5, x20, x5,le
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dup v27.8h,w4 //(1n)(1)
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ld1 {v5.8b},[x5]
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ld1 {v4.8b},[x6] //(1n)(1-8)src[2nt-1-row]
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sub v19.8b, v2.8b , v17.8b //(1n)(1-8)[nt-1-col]
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dup v20.8b, v4.b[7] //(1n)(1)
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sub v6.8b, v2.8b , v5.8b
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beq epilog
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kernel_plnr:
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cmp x1, #0 // (cond loop)
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sshl v24.8h, v24.8h, v29.8h //(8)shr
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xtn v26.8b, v26.8h //(7)
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umlal v27.8h, v5.8b, v0.8b //(1)(row+1) * src[nt-1]
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xtn v24.8b, v24.8h //(8)
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umlal v27.8h, v17.8b, v1.8b //(1)(col+1) * src[3nt+1]
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dup v21.8b, v4.b[6] //(2)
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umlal v27.8h, v6.8b, v3.8b //(1)(nt-1-row) * src[2nt+1+col]
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dup v30.8h,w4 //(2)
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umlal v27.8h, v19.8b, v20.8b //(1)(nt-1-col) * src[2nt-1-row]
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st1 {v26.8b},[x2], x3 //(7)str 8 values
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add v5.8b, v5.8b , v7.8b //(1)
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st1 {v24.8b},[x2], x3 //(8)str 8 values
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sub v6.8b, v6.8b , v7.8b //(1)
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add x20, x2, x9 //since more cols to fill, dst + 8 - 6*strd (cond loop)
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csel x2, x20, x2,gt
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umlal v30.8h, v5.8b, v0.8b //(2)
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sub x20, x2, x10 //else go to next set of rows, dst - (nt-8) (cond loop)
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csel x2, x20, x2,le
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umlal v30.8h, v17.8b, v1.8b //(2)
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dup v22.8b, v4.b[5] //(3)
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umlal v30.8h, v6.8b, v3.8b //(2)
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dup v28.8h,w4 //(3)
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umlal v30.8h, v19.8b, v21.8b //(2)
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sshl v27.8h, v27.8h, v29.8h //(1)shr
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add v5.8b, v5.8b , v7.8b //(2)
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csel x1, x4, x1,le //nt reloaded (refresh the value) (cond loop)
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sub v6.8b, v6.8b , v7.8b //(2)
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subs x1, x1, #8 //row counter (loop)
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xtn v27.8b, v27.8h //(1)
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umlal v28.8h, v5.8b, v0.8b //(3)
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dup v23.8b, v4.b[4] //(4)
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umlal v28.8h, v17.8b, v1.8b //(3)
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dup v25.8h,w4 //(4)
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umlal v28.8h, v6.8b, v3.8b //(3)
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st1 {v27.8b},[x2], x3 //(1)str 8 values
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umlal v28.8h, v19.8b, v22.8b //(3)
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sshl v30.8h, v30.8h, v29.8h //(2)shr
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add v5.8b, v5.8b , v7.8b //(3)
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sub v6.8b, v6.8b , v7.8b //(3)
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xtn v30.8b, v30.8h //(2)
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umlal v25.8h, v5.8b, v0.8b //(4)
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dup v20.8b, v4.b[3] //(5)
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umlal v25.8h, v17.8b, v1.8b //(4)
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dup v16.8h,w4 //(5)
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umlal v25.8h, v6.8b, v3.8b //(4)
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st1 {v30.8b},[x2], x3 //(2)str 8 values
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umlal v25.8h, v19.8b, v23.8b //(4)
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sshl v28.8h, v28.8h, v29.8h //(3)shr
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add v5.8b, v5.8b , v7.8b //(4)
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sub v6.8b, v6.8b , v7.8b //(4)
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xtn v28.8b, v28.8h //(3)
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umlal v16.8h, v5.8b, v0.8b //(5)
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dup v21.8b, v4.b[2] //(6)
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umlal v16.8h, v17.8b, v1.8b //(5)
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dup v18.8h,w4 //(6)
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umlal v16.8h, v6.8b, v3.8b //(5)
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st1 {v28.8b},[x2], x3 //(3)str 8 values
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umlal v16.8h, v19.8b, v20.8b //(5)
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add x20, x11, #1 //x12 reset (cond loop)
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csel x12, x20, x12,le
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sshl v25.8h, v25.8h, v29.8h //(4)shr
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add x20, x12, #8 //col inc (cond loop)
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csel x12, x20, x12,gt
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add v5.8b, v5.8b , v7.8b //(5)
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add x20, x14, #8 //also for col inc (cond loop)
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csel x14, x20, x14,gt
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sub v6.8b, v6.8b , v7.8b //(5)
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xtn v25.8b, v25.8h //(4)
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umlal v18.8h, v5.8b, v0.8b //(6)
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dup v22.8b, v4.b[1] //(7)
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umlal v18.8h, v17.8b, v1.8b //(6)
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dup v26.8h,w4 //(7)
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umlal v18.8h, v6.8b, v3.8b //(6)
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st1 {v25.8b},[x2], x3 //(4)str 8 values
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umlal v18.8h, v19.8b, v21.8b //(6)
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csel x14, x0, x14,le //x14 reset (cond loop)
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sshl v16.8h, v16.8h, v29.8h //(5)shr
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sub x20, x6, #8 //for next set of rows (cond loop)
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csel x6, x20, x6,le
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add v5.8b, v5.8b , v7.8b //(6)
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add x20, x5, #8 // (cond loop)
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csel x5, x20, x5,le
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sub v6.8b, v6.8b , v7.8b //(6)
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xtn v16.8b, v16.8h //(5)
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umlal v26.8h, v5.8b, v0.8b //(7)
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dup v23.8b, v4.b[0] //(8)
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umlal v26.8h, v17.8b, v1.8b //(7)
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dup v24.8h,w4 //(8)
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umlal v26.8h, v6.8b, v3.8b //(7)
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st1 {v16.8b},[x2], x3 //(5)str 8 values
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umlal v26.8h, v19.8b, v22.8b //(7)
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ld1 {v4.8b},[x6] //(1n)(1-8)src[2nt-1-row]
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sshl v18.8h, v18.8h, v29.8h //(6)shr
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add v5.8b, v5.8b , v7.8b //(7)
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sub v6.8b, v6.8b , v7.8b //(7)
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xtn v18.8b, v18.8h //(6)
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umlal v24.8h, v5.8b, v0.8b //(8)
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ld1 {v5.8b},[x5] //(row+1 value)
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umlal v24.8h, v17.8b, v1.8b //(8)
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dup v20.8b, v4.b[7] //(1n)(1)
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umlal v24.8h, v6.8b, v3.8b //(8)
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st1 {v18.8b},[x2], x3 //(6)str 8 values
|
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umlal v24.8h, v19.8b, v23.8b //(8)
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|
|
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ld1 {v17.8b},[x12] //(1n)(1-8)load 8 coeffs [col+1]
|
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sub v6.8b, v2.8b , v5.8b //(nt-1-row) value
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subs x7, x7, #8 //col counter
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|
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ld1 {v3.8b},[x14] //(1n)(1-8)load 8 src[2nt+1+col]
|
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sshl v26.8h, v26.8h, v29.8h //(7)shr
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|
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dup v27.8h,w4 //(1n)(1)
|
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sub v19.8b, v2.8b , v17.8b //(1n)(1-8)[nt-1-col]
|
|
|
|
bne kernel_plnr
|
|
|
|
epilog:
|
|
|
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xtn v26.8b, v26.8h //(7)
|
|
st1 {v26.8b},[x2], x3 //(7)str 8 values
|
|
|
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sshl v24.8h, v24.8h, v29.8h //(8)shr
|
|
xtn v24.8b, v24.8h //(8)
|
|
st1 {v24.8b},[x2], x3 //(8)str 8 values
|
|
|
|
//@ ========== ***************** =====================
|
|
|
|
beq end_loop
|
|
|
|
tf_sz_4:
|
|
ld1 {v25.8b},[x14] //load src[2nt+1+col]
|
|
ld1 {v17.8b},[x12], x10 //load 8 coeffs [col+1]
|
|
loop_sz_4:
|
|
mov x10, #4 //reduce inc to #4 for 4x4
|
|
ldr w7, [x6], #-1 //src[2nt-1-row] (dec to take into account row)
|
|
sxtw x7,w7
|
|
dup v4.8b,w7 //src[2nt-1-row]
|
|
|
|
sub v19.8b, v2.8b , v17.8b //[nt-1-col]
|
|
|
|
umull v27.8h, v5.8b, v0.8b //(row+1) * src[nt-1]
|
|
umlal v27.8h, v6.8b, v25.8b //(nt-1-row) * src[2nt+1+col]
|
|
umlal v27.8h, v17.8b, v1.8b //(col+1) * src[3nt+1]
|
|
umlal v27.8h, v19.8b, v4.8b //(nt-1-col) * src[2nt-1-row]
|
|
// vadd.i16 q6, q6, q8 @add (nt)
|
|
// vshl.s16 q6, q6, q7 @shr
|
|
// vmovn.i16 d12, q6
|
|
rshrn v27.8b, v27.8h,#3
|
|
st1 {v27.s}[0],[x2], x3
|
|
|
|
add v5.8b, v5.8b , v7.8b //row++ [(row+1)++]
|
|
sub v6.8b, v6.8b , v7.8b //[nt-1-row]--
|
|
subs x1, x1, #1
|
|
|
|
bne loop_sz_4
|
|
|
|
end_loop:
|
|
// ldmfd sp!,{x4-x12,x15} //reload the registers from sp
|
|
ldp x19, x20,[sp],#16
|
|
|
|
ret
|
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