100 lines
2.8 KiB
Plaintext
100 lines
2.8 KiB
Plaintext
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OpenRISC Linux
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==============
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This is a port of Linux to the OpenRISC class of microprocessors; the initial
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target architecture, specifically, is the 32-bit OpenRISC 1000 family (or1k).
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For information about OpenRISC processors and ongoing development:
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website http://openrisc.io
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For more information about Linux on OpenRISC, please contact South Pole AB.
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email: info@southpole.se
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website: http://southpole.se
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http://southpoleconsulting.com
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---------------------------------------------------------------------
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Build instructions for OpenRISC toolchain and Linux
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===================================================
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In order to build and run Linux for OpenRISC, you'll need at least a basic
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toolchain and, perhaps, the architectural simulator. Steps to get these bits
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in place are outlined here.
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1) The toolchain can be obtained from openrisc.io. Instructions for building
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a toolchain can be found at:
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https://github.com/openrisc/tutorials
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2) or1ksim (optional)
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or1ksim is the architectural simulator which will allow you to actually run
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your OpenRISC Linux kernel if you don't have an OpenRISC processor at hand.
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git clone https://github.com/openrisc/or1ksim.git
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cd or1ksim
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./configure --prefix=$OPENRISC_PREFIX
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make
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make install
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3) Linux kernel
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Build the kernel as usual
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make ARCH=openrisc defconfig
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make ARCH=openrisc
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4) Run in architectural simulator
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Grab the or1ksim platform configuration file (from the or1ksim source) and
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together with your freshly built vmlinux, run your kernel with the following
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incantation:
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sim -f arch/openrisc/or1ksim.cfg vmlinux
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---------------------------------------------------------------------
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Terminology
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===========
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In the code, the following particles are used on symbols to limit the scope
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to more or less specific processor implementations:
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openrisc: the OpenRISC class of processors
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or1k: the OpenRISC 1000 family of processors
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or1200: the OpenRISC 1200 processor
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---------------------------------------------------------------------
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History
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========
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18. 11. 2003 Matjaz Breskvar (phoenix@bsemi.com)
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initial port of linux to OpenRISC/or32 architecture.
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all the core stuff is implemented and seams usable.
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08. 12. 2003 Matjaz Breskvar (phoenix@bsemi.com)
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complete change of TLB miss handling.
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rewrite of exceptions handling.
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fully functional sash-3.6 in default initrd.
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a much improved version with changes all around.
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10. 04. 2004 Matjaz Breskvar (phoenix@bsemi.com)
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alot of bugfixes all over.
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ethernet support, functional http and telnet servers.
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running many standard linux apps.
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26. 06. 2004 Matjaz Breskvar (phoenix@bsemi.com)
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port to 2.6.x
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30. 11. 2004 Matjaz Breskvar (phoenix@bsemi.com)
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lots of bugfixes and enhancments.
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added opencores framebuffer driver.
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09. 10. 2010 Jonas Bonn (jonas@southpole.se)
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major rewrite to bring up to par with upstream Linux 2.6.36
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