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linux_old1/drivers/pci/controller/pcie-rockchip.c

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PCI: Add SPDX GPL-2.0+ to replace GPL v2 or later boilerplate Add SPDX GPL-2.0+ to all PCI files that specified the GPL and allowed either GPL version 2 or any later version. Remove the boilerplate GPL version 2 or later language, relying on the assertion in b24413180f56 ("License cleanup: add SPDX GPL-2.0 license identifier to files with no license") that the SPDX identifier may be used instead of the full boilerplate text. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-01-27 04:22:04 +08:00
// SPDX-License-Identifier: GPL-2.0+
PCI: rockchip: Add Rockchip PCIe controller support Add support for the Rockchip PCIe controller found on RK3399 SoC platform. [bhelgaas: fold in Brian's rockchip_pcie_client_irq_handler() OR fix, other fixes and cleanups from Guenter Roeck <linux@roeck-us.net> and me, uninitialized variable fix from Arnd Bergmann <arnd@arndb.de>] Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org>
2016-09-04 00:41:09 +08:00
/*
* Rockchip AXI PCIe host controller driver
*
* Copyright (c) 2016 Rockchip, Inc.
*
* Author: Shawn Lin <shawn.lin@rock-chips.com>
* Wenrui Li <wenrui.li@rock-chips.com>
*
PCI: Fix typos and whitespace errors Fix various typos and whitespace errors: s/Synopsis/Synopsys/ s/Designware/DesignWare/ s/Keystine/Keystone/ s/gpio/GPIO/ s/pcie/PCIe/ s/phy/PHY/ s/confgiruation/configuration/ No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-09-02 05:35:50 +08:00
* Bits taken from Synopsys DesignWare Host controller driver and
PCI: rockchip: Add Rockchip PCIe controller support Add support for the Rockchip PCIe controller found on RK3399 SoC platform. [bhelgaas: fold in Brian's rockchip_pcie_client_irq_handler() OR fix, other fixes and cleanups from Guenter Roeck <linux@roeck-us.net> and me, uninitialized variable fix from Arnd Bergmann <arnd@arndb.de>] Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org>
2016-09-04 00:41:09 +08:00
* ARM PCI Host generic driver.
*/
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/gpio/consumer.h>
#include <linux/of_pci.h>
#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/reset.h>
PCI: Move private DT related functions into private header The functions in linux/of_pci.h are primarily used by host bridge drivers, so they can be private to drivers/pci/. The remaining functions are still used mostly in host bridge drivers that still live in arch specific code. Hopefully someday, those will get moved into drivers/pci as well. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Jingoo Han <jingoohan1@gmail.com>
2018-05-12 01:15:30 +08:00
#include "../pci.h"
PCI: rockchip: Separate common code from RC driver In preparation for introducing EP driver for Rockchip PCIe controller, rename the RC driver from pcie-rockchip.c to pcie-rockchip-host.c, and only leave some common functions in pcie-rockchip.c in order to be reused for both of RC driver and EP driver. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com>
2018-05-09 09:11:49 +08:00
#include "pcie-rockchip.h"
PCI: Move private DT related functions into private header The functions in linux/of_pci.h are primarily used by host bridge drivers, so they can be private to drivers/pci/. The remaining functions are still used mostly in host bridge drivers that still live in arch specific code. Hopefully someday, those will get moved into drivers/pci as well. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Jingoo Han <jingoohan1@gmail.com>
2018-05-12 01:15:30 +08:00
PCI: rockchip: Split out rockchip_pcie_parse_dt() to parse DT Most of the DT properties are used for both of RC driver and EP driver, so split them out in a new function, rockchip_pcie_parse_dt(), in pcie-rockchip.c and rename the original function to rockchip_pcie_parse_host_dt() to avoid confusion. No functional changed intended. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com>
2018-05-09 09:12:05 +08:00
int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip)
PCI: rockchip: Add Rockchip PCIe controller support Add support for the Rockchip PCIe controller found on RK3399 SoC platform. [bhelgaas: fold in Brian's rockchip_pcie_client_irq_handler() OR fix, other fixes and cleanups from Guenter Roeck <linux@roeck-us.net> and me, uninitialized variable fix from Arnd Bergmann <arnd@arndb.de>] Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org>
2016-09-04 00:41:09 +08:00
{
PCI: rockchip: Split out rockchip_pcie_parse_dt() to parse DT Most of the DT properties are used for both of RC driver and EP driver, so split them out in a new function, rockchip_pcie_parse_dt(), in pcie-rockchip.c and rename the original function to rockchip_pcie_parse_host_dt() to avoid confusion. No functional changed intended. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com>
2018-05-09 09:12:05 +08:00
struct device *dev = rockchip->dev;
struct platform_device *pdev = to_platform_device(dev);
struct device_node *node = dev->of_node;
struct resource *regs;
int err;
PCI: rockchip: Add Rockchip PCIe controller support Add support for the Rockchip PCIe controller found on RK3399 SoC platform. [bhelgaas: fold in Brian's rockchip_pcie_client_irq_handler() OR fix, other fixes and cleanups from Guenter Roeck <linux@roeck-us.net> and me, uninitialized variable fix from Arnd Bergmann <arnd@arndb.de>] Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org>
2016-09-04 00:41:09 +08:00
PCI: rockchip: Add EP driver for Rockchip PCIe controller Add support for the Rockchip PCIe controller in endpoint mode; it currently supports up to 32 regions with each region spanning at least 1MB as per TRM. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> [lorenzo.pieralisi@arm.com: updated commit log] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2018-05-09 09:12:59 +08:00
if (rockchip->is_rc) {
regs = platform_get_resource_byname(pdev,
IORESOURCE_MEM,
"axi-base");
rockchip->reg_base = devm_pci_remap_cfg_resource(dev, regs);
if (IS_ERR(rockchip->reg_base))
return PTR_ERR(rockchip->reg_base);
PCI: rockchip: Add Rockchip PCIe controller support Add support for the Rockchip PCIe controller found on RK3399 SoC platform. [bhelgaas: fold in Brian's rockchip_pcie_client_irq_handler() OR fix, other fixes and cleanups from Guenter Roeck <linux@roeck-us.net> and me, uninitialized variable fix from Arnd Bergmann <arnd@arndb.de>] Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org>
2016-09-04 00:41:09 +08:00
} else {
PCI: rockchip: Add EP driver for Rockchip PCIe controller Add support for the Rockchip PCIe controller in endpoint mode; it currently supports up to 32 regions with each region spanning at least 1MB as per TRM. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> [lorenzo.pieralisi@arm.com: updated commit log] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2018-05-09 09:12:59 +08:00
rockchip->mem_res =
platform_get_resource_byname(pdev, IORESOURCE_MEM,
"mem-base");
if (!rockchip->mem_res)
return -EINVAL;
PCI: rockchip: Add Rockchip PCIe controller support Add support for the Rockchip PCIe controller found on RK3399 SoC platform. [bhelgaas: fold in Brian's rockchip_pcie_client_irq_handler() OR fix, other fixes and cleanups from Guenter Roeck <linux@roeck-us.net> and me, uninitialized variable fix from Arnd Bergmann <arnd@arndb.de>] Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org>
2016-09-04 00:41:09 +08:00
}
PCI: rockchip: Add EP driver for Rockchip PCIe controller Add support for the Rockchip PCIe controller in endpoint mode; it currently supports up to 32 regions with each region spanning at least 1MB as per TRM. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> [lorenzo.pieralisi@arm.com: updated commit log] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2018-05-09 09:12:59 +08:00
regs = platform_get_resource_byname(pdev, IORESOURCE_MEM,
PCI: rockchip: Split out rockchip_pcie_parse_dt() to parse DT Most of the DT properties are used for both of RC driver and EP driver, so split them out in a new function, rockchip_pcie_parse_dt(), in pcie-rockchip.c and rename the original function to rockchip_pcie_parse_host_dt() to avoid confusion. No functional changed intended. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com>
2018-05-09 09:12:05 +08:00
"apb-base");
rockchip->apb_base = devm_ioremap_resource(dev, regs);
if (IS_ERR(rockchip->apb_base))
return PTR_ERR(rockchip->apb_base);
PCI: rockchip: Add Rockchip PCIe controller support Add support for the Rockchip PCIe controller found on RK3399 SoC platform. [bhelgaas: fold in Brian's rockchip_pcie_client_irq_handler() OR fix, other fixes and cleanups from Guenter Roeck <linux@roeck-us.net> and me, uninitialized variable fix from Arnd Bergmann <arnd@arndb.de>] Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org>
2016-09-04 00:41:09 +08:00
PCI: rockchip: Split out rockchip_pcie_parse_dt() to parse DT Most of the DT properties are used for both of RC driver and EP driver, so split them out in a new function, rockchip_pcie_parse_dt(), in pcie-rockchip.c and rename the original function to rockchip_pcie_parse_host_dt() to avoid confusion. No functional changed intended. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com>
2018-05-09 09:12:05 +08:00
err = rockchip_pcie_get_phys(rockchip);
if (err)
return err;
PCI: rockchip: Add Rockchip PCIe controller support Add support for the Rockchip PCIe controller found on RK3399 SoC platform. [bhelgaas: fold in Brian's rockchip_pcie_client_irq_handler() OR fix, other fixes and cleanups from Guenter Roeck <linux@roeck-us.net> and me, uninitialized variable fix from Arnd Bergmann <arnd@arndb.de>] Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org>
2016-09-04 00:41:09 +08:00
PCI: rockchip: Split out rockchip_pcie_parse_dt() to parse DT Most of the DT properties are used for both of RC driver and EP driver, so split them out in a new function, rockchip_pcie_parse_dt(), in pcie-rockchip.c and rename the original function to rockchip_pcie_parse_host_dt() to avoid confusion. No functional changed intended. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com>
2018-05-09 09:12:05 +08:00
rockchip->lanes = 1;
err = of_property_read_u32(node, "num-lanes", &rockchip->lanes);
if (!err && (rockchip->lanes == 0 ||
rockchip->lanes == 3 ||
rockchip->lanes > 4)) {
dev_warn(dev, "invalid num-lanes, default to use one lane\n");
rockchip->lanes = 1;
PCI: rockchip: Add Rockchip PCIe controller support Add support for the Rockchip PCIe controller found on RK3399 SoC platform. [bhelgaas: fold in Brian's rockchip_pcie_client_irq_handler() OR fix, other fixes and cleanups from Guenter Roeck <linux@roeck-us.net> and me, uninitialized variable fix from Arnd Bergmann <arnd@arndb.de>] Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org>
2016-09-04 00:41:09 +08:00
}
PCI: rockchip: Split out rockchip_pcie_parse_dt() to parse DT Most of the DT properties are used for both of RC driver and EP driver, so split them out in a new function, rockchip_pcie_parse_dt(), in pcie-rockchip.c and rename the original function to rockchip_pcie_parse_host_dt() to avoid confusion. No functional changed intended. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com>
2018-05-09 09:12:05 +08:00
rockchip->link_gen = of_pci_get_max_link_speed(node);
if (rockchip->link_gen < 0 || rockchip->link_gen > 2)
rockchip->link_gen = 2;
PCI: rockchip: Add Rockchip PCIe controller support Add support for the Rockchip PCIe controller found on RK3399 SoC platform. [bhelgaas: fold in Brian's rockchip_pcie_client_irq_handler() OR fix, other fixes and cleanups from Guenter Roeck <linux@roeck-us.net> and me, uninitialized variable fix from Arnd Bergmann <arnd@arndb.de>] Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org>
2016-09-04 00:41:09 +08:00
PCI: rockchip: Split out rockchip_pcie_parse_dt() to parse DT Most of the DT properties are used for both of RC driver and EP driver, so split them out in a new function, rockchip_pcie_parse_dt(), in pcie-rockchip.c and rename the original function to rockchip_pcie_parse_host_dt() to avoid confusion. No functional changed intended. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com>
2018-05-09 09:12:05 +08:00
rockchip->core_rst = devm_reset_control_get_exclusive(dev, "core");
if (IS_ERR(rockchip->core_rst)) {
if (PTR_ERR(rockchip->core_rst) != -EPROBE_DEFER)
dev_err(dev, "missing core reset property in node\n");
return PTR_ERR(rockchip->core_rst);
PCI: rockchip: Add Rockchip PCIe controller support Add support for the Rockchip PCIe controller found on RK3399 SoC platform. [bhelgaas: fold in Brian's rockchip_pcie_client_irq_handler() OR fix, other fixes and cleanups from Guenter Roeck <linux@roeck-us.net> and me, uninitialized variable fix from Arnd Bergmann <arnd@arndb.de>] Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org>
2016-09-04 00:41:09 +08:00
}
PCI: rockchip: Split out rockchip_pcie_parse_dt() to parse DT Most of the DT properties are used for both of RC driver and EP driver, so split them out in a new function, rockchip_pcie_parse_dt(), in pcie-rockchip.c and rename the original function to rockchip_pcie_parse_host_dt() to avoid confusion. No functional changed intended. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com>
2018-05-09 09:12:05 +08:00
rockchip->mgmt_rst = devm_reset_control_get_exclusive(dev, "mgmt");
if (IS_ERR(rockchip->mgmt_rst)) {
if (PTR_ERR(rockchip->mgmt_rst) != -EPROBE_DEFER)
dev_err(dev, "missing mgmt reset property in node\n");
return PTR_ERR(rockchip->mgmt_rst);
PCI: rockchip: Add Rockchip PCIe controller support Add support for the Rockchip PCIe controller found on RK3399 SoC platform. [bhelgaas: fold in Brian's rockchip_pcie_client_irq_handler() OR fix, other fixes and cleanups from Guenter Roeck <linux@roeck-us.net> and me, uninitialized variable fix from Arnd Bergmann <arnd@arndb.de>] Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org>
2016-09-04 00:41:09 +08:00
}
PCI: rockchip: Split out rockchip_pcie_parse_dt() to parse DT Most of the DT properties are used for both of RC driver and EP driver, so split them out in a new function, rockchip_pcie_parse_dt(), in pcie-rockchip.c and rename the original function to rockchip_pcie_parse_host_dt() to avoid confusion. No functional changed intended. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com>
2018-05-09 09:12:05 +08:00
rockchip->mgmt_sticky_rst = devm_reset_control_get_exclusive(dev,
"mgmt-sticky");
if (IS_ERR(rockchip->mgmt_sticky_rst)) {
if (PTR_ERR(rockchip->mgmt_sticky_rst) != -EPROBE_DEFER)
dev_err(dev, "missing mgmt-sticky reset property in node\n");
return PTR_ERR(rockchip->mgmt_sticky_rst);
PCI: rockchip: Add Rockchip PCIe controller support Add support for the Rockchip PCIe controller found on RK3399 SoC platform. [bhelgaas: fold in Brian's rockchip_pcie_client_irq_handler() OR fix, other fixes and cleanups from Guenter Roeck <linux@roeck-us.net> and me, uninitialized variable fix from Arnd Bergmann <arnd@arndb.de>] Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org>
2016-09-04 00:41:09 +08:00
}
PCI: rockchip: Split out rockchip_pcie_parse_dt() to parse DT Most of the DT properties are used for both of RC driver and EP driver, so split them out in a new function, rockchip_pcie_parse_dt(), in pcie-rockchip.c and rename the original function to rockchip_pcie_parse_host_dt() to avoid confusion. No functional changed intended. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com>
2018-05-09 09:12:05 +08:00
rockchip->pipe_rst = devm_reset_control_get_exclusive(dev, "pipe");
if (IS_ERR(rockchip->pipe_rst)) {
if (PTR_ERR(rockchip->pipe_rst) != -EPROBE_DEFER)
dev_err(dev, "missing pipe reset property in node\n");
return PTR_ERR(rockchip->pipe_rst);
}
PCI: rockchip: Add Rockchip PCIe controller support Add support for the Rockchip PCIe controller found on RK3399 SoC platform. [bhelgaas: fold in Brian's rockchip_pcie_client_irq_handler() OR fix, other fixes and cleanups from Guenter Roeck <linux@roeck-us.net> and me, uninitialized variable fix from Arnd Bergmann <arnd@arndb.de>] Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org>
2016-09-04 00:41:09 +08:00
PCI: rockchip: Split out rockchip_pcie_parse_dt() to parse DT Most of the DT properties are used for both of RC driver and EP driver, so split them out in a new function, rockchip_pcie_parse_dt(), in pcie-rockchip.c and rename the original function to rockchip_pcie_parse_host_dt() to avoid confusion. No functional changed intended. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com>
2018-05-09 09:12:05 +08:00
rockchip->pm_rst = devm_reset_control_get_exclusive(dev, "pm");
if (IS_ERR(rockchip->pm_rst)) {
if (PTR_ERR(rockchip->pm_rst) != -EPROBE_DEFER)
dev_err(dev, "missing pm reset property in node\n");
return PTR_ERR(rockchip->pm_rst);
}
PCI: rockchip: Add Rockchip PCIe controller support Add support for the Rockchip PCIe controller found on RK3399 SoC platform. [bhelgaas: fold in Brian's rockchip_pcie_client_irq_handler() OR fix, other fixes and cleanups from Guenter Roeck <linux@roeck-us.net> and me, uninitialized variable fix from Arnd Bergmann <arnd@arndb.de>] Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org>
2016-09-04 00:41:09 +08:00
PCI: rockchip: Split out rockchip_pcie_parse_dt() to parse DT Most of the DT properties are used for both of RC driver and EP driver, so split them out in a new function, rockchip_pcie_parse_dt(), in pcie-rockchip.c and rename the original function to rockchip_pcie_parse_host_dt() to avoid confusion. No functional changed intended. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com>
2018-05-09 09:12:05 +08:00
rockchip->pclk_rst = devm_reset_control_get_exclusive(dev, "pclk");
if (IS_ERR(rockchip->pclk_rst)) {
if (PTR_ERR(rockchip->pclk_rst) != -EPROBE_DEFER)
dev_err(dev, "missing pclk reset property in node\n");
return PTR_ERR(rockchip->pclk_rst);
}
PCI: rockchip: Add Rockchip PCIe controller support Add support for the Rockchip PCIe controller found on RK3399 SoC platform. [bhelgaas: fold in Brian's rockchip_pcie_client_irq_handler() OR fix, other fixes and cleanups from Guenter Roeck <linux@roeck-us.net> and me, uninitialized variable fix from Arnd Bergmann <arnd@arndb.de>] Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org>
2016-09-04 00:41:09 +08:00
PCI: rockchip: Split out rockchip_pcie_parse_dt() to parse DT Most of the DT properties are used for both of RC driver and EP driver, so split them out in a new function, rockchip_pcie_parse_dt(), in pcie-rockchip.c and rename the original function to rockchip_pcie_parse_host_dt() to avoid confusion. No functional changed intended. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com>
2018-05-09 09:12:05 +08:00
rockchip->aclk_rst = devm_reset_control_get_exclusive(dev, "aclk");
if (IS_ERR(rockchip->aclk_rst)) {
if (PTR_ERR(rockchip->aclk_rst) != -EPROBE_DEFER)
dev_err(dev, "missing aclk reset property in node\n");
return PTR_ERR(rockchip->aclk_rst);
}
PCI: rockchip: Add Rockchip PCIe controller support Add support for the Rockchip PCIe controller found on RK3399 SoC platform. [bhelgaas: fold in Brian's rockchip_pcie_client_irq_handler() OR fix, other fixes and cleanups from Guenter Roeck <linux@roeck-us.net> and me, uninitialized variable fix from Arnd Bergmann <arnd@arndb.de>] Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org>
2016-09-04 00:41:09 +08:00
PCI: rockchip: Split out rockchip_pcie_parse_dt() to parse DT Most of the DT properties are used for both of RC driver and EP driver, so split them out in a new function, rockchip_pcie_parse_dt(), in pcie-rockchip.c and rename the original function to rockchip_pcie_parse_host_dt() to avoid confusion. No functional changed intended. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com>
2018-05-09 09:12:05 +08:00
if (rockchip->is_rc) {
rockchip->ep_gpio = devm_gpiod_get(dev, "ep", GPIOD_OUT_HIGH);
if (IS_ERR(rockchip->ep_gpio)) {
dev_err(dev, "missing ep-gpios property in node\n");
return PTR_ERR(rockchip->ep_gpio);
}
}
PCI: rockchip: Add Rockchip PCIe controller support Add support for the Rockchip PCIe controller found on RK3399 SoC platform. [bhelgaas: fold in Brian's rockchip_pcie_client_irq_handler() OR fix, other fixes and cleanups from Guenter Roeck <linux@roeck-us.net> and me, uninitialized variable fix from Arnd Bergmann <arnd@arndb.de>] Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org>
2016-09-04 00:41:09 +08:00
PCI: rockchip: Split out rockchip_pcie_parse_dt() to parse DT Most of the DT properties are used for both of RC driver and EP driver, so split them out in a new function, rockchip_pcie_parse_dt(), in pcie-rockchip.c and rename the original function to rockchip_pcie_parse_host_dt() to avoid confusion. No functional changed intended. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com>
2018-05-09 09:12:05 +08:00
rockchip->aclk_pcie = devm_clk_get(dev, "aclk");
if (IS_ERR(rockchip->aclk_pcie)) {
dev_err(dev, "aclk clock not found\n");
return PTR_ERR(rockchip->aclk_pcie);
}
PCI: rockchip: Add Rockchip PCIe controller support Add support for the Rockchip PCIe controller found on RK3399 SoC platform. [bhelgaas: fold in Brian's rockchip_pcie_client_irq_handler() OR fix, other fixes and cleanups from Guenter Roeck <linux@roeck-us.net> and me, uninitialized variable fix from Arnd Bergmann <arnd@arndb.de>] Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org>
2016-09-04 00:41:09 +08:00
PCI: rockchip: Split out rockchip_pcie_parse_dt() to parse DT Most of the DT properties are used for both of RC driver and EP driver, so split them out in a new function, rockchip_pcie_parse_dt(), in pcie-rockchip.c and rename the original function to rockchip_pcie_parse_host_dt() to avoid confusion. No functional changed intended. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com>
2018-05-09 09:12:05 +08:00
rockchip->aclk_perf_pcie = devm_clk_get(dev, "aclk-perf");
if (IS_ERR(rockchip->aclk_perf_pcie)) {
dev_err(dev, "aclk_perf clock not found\n");
return PTR_ERR(rockchip->aclk_perf_pcie);
}
PCI: rockchip: Provide captured slot power limit and scale If vpcie3v3 is available, we could provide these information via RC's configure register to make EP able to know the power limit. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-12-08 05:05:58 +08:00
PCI: rockchip: Split out rockchip_pcie_parse_dt() to parse DT Most of the DT properties are used for both of RC driver and EP driver, so split them out in a new function, rockchip_pcie_parse_dt(), in pcie-rockchip.c and rename the original function to rockchip_pcie_parse_host_dt() to avoid confusion. No functional changed intended. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com>
2018-05-09 09:12:05 +08:00
rockchip->hclk_pcie = devm_clk_get(dev, "hclk");
if (IS_ERR(rockchip->hclk_pcie)) {
dev_err(dev, "hclk clock not found\n");
return PTR_ERR(rockchip->hclk_pcie);
}
PCI: rockchip: Provide captured slot power limit and scale If vpcie3v3 is available, we could provide these information via RC's configure register to make EP able to know the power limit. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-12-08 05:05:58 +08:00
PCI: rockchip: Split out rockchip_pcie_parse_dt() to parse DT Most of the DT properties are used for both of RC driver and EP driver, so split them out in a new function, rockchip_pcie_parse_dt(), in pcie-rockchip.c and rename the original function to rockchip_pcie_parse_host_dt() to avoid confusion. No functional changed intended. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com>
2018-05-09 09:12:05 +08:00
rockchip->clk_pcie_pm = devm_clk_get(dev, "pm");
if (IS_ERR(rockchip->clk_pcie_pm)) {
dev_err(dev, "pm clock not found\n");
return PTR_ERR(rockchip->clk_pcie_pm);
PCI: rockchip: Provide captured slot power limit and scale If vpcie3v3 is available, we could provide these information via RC's configure register to make EP able to know the power limit. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-12-08 05:05:58 +08:00
}
PCI: rockchip: Unindent rockchip_pcie_set_power_limit() If regulator_get_current_limit() returns 0 or error, return early so the body of the function doesn't have to be indented as the body of an "if" statement. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-03-24 06:21:26 +08:00
PCI: rockchip: Split out rockchip_pcie_parse_dt() to parse DT Most of the DT properties are used for both of RC driver and EP driver, so split them out in a new function, rockchip_pcie_parse_dt(), in pcie-rockchip.c and rename the original function to rockchip_pcie_parse_host_dt() to avoid confusion. No functional changed intended. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com>
2018-05-09 09:12:05 +08:00
return 0;
PCI: rockchip: Provide captured slot power limit and scale If vpcie3v3 is available, we could provide these information via RC's configure register to make EP able to know the power limit. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-12-08 05:05:58 +08:00
}
PCI: rockchip: Split out rockchip_pcie_parse_dt() to parse DT Most of the DT properties are used for both of RC driver and EP driver, so split them out in a new function, rockchip_pcie_parse_dt(), in pcie-rockchip.c and rename the original function to rockchip_pcie_parse_host_dt() to avoid confusion. No functional changed intended. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com>
2018-05-09 09:12:05 +08:00
EXPORT_SYMBOL_GPL(rockchip_pcie_parse_dt);
PCI: rockchip: Provide captured slot power limit and scale If vpcie3v3 is available, we could provide these information via RC's configure register to make EP able to know the power limit. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-12-08 05:05:58 +08:00
PCI: rockchip: Split out common function to init controller Most of the initialization are used for both of RC driver and EP driver; factor the initialization out to a new function, rockchip_pcie_init_port(), in pcie-rockchip.c and rename the original function to rockchip_pcie_host_init_port() to avoid confusion. No functional changed intended. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com>
2018-05-09 09:12:24 +08:00
int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
PCI: rockchip: Add Rockchip PCIe controller support Add support for the Rockchip PCIe controller found on RK3399 SoC platform. [bhelgaas: fold in Brian's rockchip_pcie_client_irq_handler() OR fix, other fixes and cleanups from Guenter Roeck <linux@roeck-us.net> and me, uninitialized variable fix from Arnd Bergmann <arnd@arndb.de>] Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org>
2016-09-04 00:41:09 +08:00
{
struct device *dev = rockchip->dev;
PCI: rockchip: Add per-lane PHY support We distinguish the legacy PHY from newer per-lane PHYs by adding legacy_phy flag. Note that the legacy PHY is still the first option to be searched in order not to break the backward compatibility of DTB. Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> [bhelgaas: tidy rockchip_pcie_get_phys()] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-08-26 04:59:01 +08:00
int err, i;
PCI: rockchip: Split out common function to init controller Most of the initialization are used for both of RC driver and EP driver; factor the initialization out to a new function, rockchip_pcie_init_port(), in pcie-rockchip.c and rename the original function to rockchip_pcie_host_init_port() to avoid confusion. No functional changed intended. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com>
2018-05-09 09:12:24 +08:00
u32 regs;
PCI: rockchip: Add Rockchip PCIe controller support Add support for the Rockchip PCIe controller found on RK3399 SoC platform. [bhelgaas: fold in Brian's rockchip_pcie_client_irq_handler() OR fix, other fixes and cleanups from Guenter Roeck <linux@roeck-us.net> and me, uninitialized variable fix from Arnd Bergmann <arnd@arndb.de>] Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org>
2016-09-04 00:41:09 +08:00
PCI: rockchip: Add three new resets as required properties pm_rst, aclk_rst, pclk_rst was controlled by ROM code so the software wasn't needed to control it again in theory. But it didn't work properly, so we do need to do it again and add enough delay between the assert of pm_rst and the deassert of pm_rst. The Soc intergrated with this controller, rk3399, is still under MP test internally, so the backward compatibility won't be a big deal. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Rob Herring <robh@kernel.org>
2016-11-11 01:14:37 +08:00
err = reset_control_assert(rockchip->aclk_rst);
if (err) {
dev_err(dev, "assert aclk_rst err %d\n", err);
return err;
}
err = reset_control_assert(rockchip->pclk_rst);
if (err) {
dev_err(dev, "assert pclk_rst err %d\n", err);
return err;
}
err = reset_control_assert(rockchip->pm_rst);
if (err) {
dev_err(dev, "assert pm_rst err %d\n", err);
return err;
}
PCI: rockchip: Add per-lane PHY support We distinguish the legacy PHY from newer per-lane PHYs by adding legacy_phy flag. Note that the legacy PHY is still the first option to be searched in order not to break the backward compatibility of DTB. Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> [bhelgaas: tidy rockchip_pcie_get_phys()] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-08-26 04:59:01 +08:00
for (i = 0; i < MAX_LANE_NUM; i++) {
err = phy_init(rockchip->phys[i]);
if (err) {
dev_err(dev, "init phy%d err %d\n", i, err);
PCI: rockchip: Clean up PHY if driver probe or resume fails We observed that the clk_pciephy_ref is still enabled when we fail to probe the driver. root@linaro-alip:~# grep pcie /sys/kernel/debug/clk/clk_summary clk_pciephy_ref 1 1 24000000 0 0 clk_pcie_pm 0 0 24000000 0 0 clk_pcie_core_cru 0 0 125000000 0 0 clk_pciephy_ref100m 0 0 100000000 0 0 aclk_pcie 0 0 148500000 0 0 aclk_perf_pcie 0 0 148500000 0 0 pclk_pcie 0 0 37125000 0 0 clk_pcie_core 0 0 0 0 0 clk_pciephy_ref is used by the PHY driver and we need to properly disable it for this case. Add error handling in rockchip_pcie_init_port() and rockchip_pcie_resume_noirq() to fix this issue. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-08-23 15:03:07 +08:00
goto err_exit_phy;
PCI: rockchip: Add per-lane PHY support We distinguish the legacy PHY from newer per-lane PHYs by adding legacy_phy flag. Note that the legacy PHY is still the first option to be searched in order not to break the backward compatibility of DTB. Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> [bhelgaas: tidy rockchip_pcie_get_phys()] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-08-26 04:59:01 +08:00
}
PCI: rockchip: Add Rockchip PCIe controller support Add support for the Rockchip PCIe controller found on RK3399 SoC platform. [bhelgaas: fold in Brian's rockchip_pcie_client_irq_handler() OR fix, other fixes and cleanups from Guenter Roeck <linux@roeck-us.net> and me, uninitialized variable fix from Arnd Bergmann <arnd@arndb.de>] Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org>
2016-09-04 00:41:09 +08:00
}
err = reset_control_assert(rockchip->core_rst);
if (err) {
dev_err(dev, "assert core_rst err %d\n", err);
PCI: rockchip: Clean up PHY if driver probe or resume fails We observed that the clk_pciephy_ref is still enabled when we fail to probe the driver. root@linaro-alip:~# grep pcie /sys/kernel/debug/clk/clk_summary clk_pciephy_ref 1 1 24000000 0 0 clk_pcie_pm 0 0 24000000 0 0 clk_pcie_core_cru 0 0 125000000 0 0 clk_pciephy_ref100m 0 0 100000000 0 0 aclk_pcie 0 0 148500000 0 0 aclk_perf_pcie 0 0 148500000 0 0 pclk_pcie 0 0 37125000 0 0 clk_pcie_core 0 0 0 0 0 clk_pciephy_ref is used by the PHY driver and we need to properly disable it for this case. Add error handling in rockchip_pcie_init_port() and rockchip_pcie_resume_noirq() to fix this issue. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-08-23 15:03:07 +08:00
goto err_exit_phy;
PCI: rockchip: Add Rockchip PCIe controller support Add support for the Rockchip PCIe controller found on RK3399 SoC platform. [bhelgaas: fold in Brian's rockchip_pcie_client_irq_handler() OR fix, other fixes and cleanups from Guenter Roeck <linux@roeck-us.net> and me, uninitialized variable fix from Arnd Bergmann <arnd@arndb.de>] Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org>
2016-09-04 00:41:09 +08:00
}
err = reset_control_assert(rockchip->mgmt_rst);
if (err) {
dev_err(dev, "assert mgmt_rst err %d\n", err);
PCI: rockchip: Clean up PHY if driver probe or resume fails We observed that the clk_pciephy_ref is still enabled when we fail to probe the driver. root@linaro-alip:~# grep pcie /sys/kernel/debug/clk/clk_summary clk_pciephy_ref 1 1 24000000 0 0 clk_pcie_pm 0 0 24000000 0 0 clk_pcie_core_cru 0 0 125000000 0 0 clk_pciephy_ref100m 0 0 100000000 0 0 aclk_pcie 0 0 148500000 0 0 aclk_perf_pcie 0 0 148500000 0 0 pclk_pcie 0 0 37125000 0 0 clk_pcie_core 0 0 0 0 0 clk_pciephy_ref is used by the PHY driver and we need to properly disable it for this case. Add error handling in rockchip_pcie_init_port() and rockchip_pcie_resume_noirq() to fix this issue. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-08-23 15:03:07 +08:00
goto err_exit_phy;
PCI: rockchip: Add Rockchip PCIe controller support Add support for the Rockchip PCIe controller found on RK3399 SoC platform. [bhelgaas: fold in Brian's rockchip_pcie_client_irq_handler() OR fix, other fixes and cleanups from Guenter Roeck <linux@roeck-us.net> and me, uninitialized variable fix from Arnd Bergmann <arnd@arndb.de>] Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org>
2016-09-04 00:41:09 +08:00
}
err = reset_control_assert(rockchip->mgmt_sticky_rst);
if (err) {
dev_err(dev, "assert mgmt_sticky_rst err %d\n", err);
PCI: rockchip: Clean up PHY if driver probe or resume fails We observed that the clk_pciephy_ref is still enabled when we fail to probe the driver. root@linaro-alip:~# grep pcie /sys/kernel/debug/clk/clk_summary clk_pciephy_ref 1 1 24000000 0 0 clk_pcie_pm 0 0 24000000 0 0 clk_pcie_core_cru 0 0 125000000 0 0 clk_pciephy_ref100m 0 0 100000000 0 0 aclk_pcie 0 0 148500000 0 0 aclk_perf_pcie 0 0 148500000 0 0 pclk_pcie 0 0 37125000 0 0 clk_pcie_core 0 0 0 0 0 clk_pciephy_ref is used by the PHY driver and we need to properly disable it for this case. Add error handling in rockchip_pcie_init_port() and rockchip_pcie_resume_noirq() to fix this issue. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-08-23 15:03:07 +08:00
goto err_exit_phy;
PCI: rockchip: Add Rockchip PCIe controller support Add support for the Rockchip PCIe controller found on RK3399 SoC platform. [bhelgaas: fold in Brian's rockchip_pcie_client_irq_handler() OR fix, other fixes and cleanups from Guenter Roeck <linux@roeck-us.net> and me, uninitialized variable fix from Arnd Bergmann <arnd@arndb.de>] Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org>
2016-09-04 00:41:09 +08:00
}
err = reset_control_assert(rockchip->pipe_rst);
if (err) {
dev_err(dev, "assert pipe_rst err %d\n", err);
PCI: rockchip: Clean up PHY if driver probe or resume fails We observed that the clk_pciephy_ref is still enabled when we fail to probe the driver. root@linaro-alip:~# grep pcie /sys/kernel/debug/clk/clk_summary clk_pciephy_ref 1 1 24000000 0 0 clk_pcie_pm 0 0 24000000 0 0 clk_pcie_core_cru 0 0 125000000 0 0 clk_pciephy_ref100m 0 0 100000000 0 0 aclk_pcie 0 0 148500000 0 0 aclk_perf_pcie 0 0 148500000 0 0 pclk_pcie 0 0 37125000 0 0 clk_pcie_core 0 0 0 0 0 clk_pciephy_ref is used by the PHY driver and we need to properly disable it for this case. Add error handling in rockchip_pcie_init_port() and rockchip_pcie_resume_noirq() to fix this issue. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-08-23 15:03:07 +08:00
goto err_exit_phy;
PCI: rockchip: Add Rockchip PCIe controller support Add support for the Rockchip PCIe controller found on RK3399 SoC platform. [bhelgaas: fold in Brian's rockchip_pcie_client_irq_handler() OR fix, other fixes and cleanups from Guenter Roeck <linux@roeck-us.net> and me, uninitialized variable fix from Arnd Bergmann <arnd@arndb.de>] Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org>
2016-09-04 00:41:09 +08:00
}
PCI: rockchip: Move the deassert of pm/aclk/pclk after phy_init() Move deassert of pm/aclk/pclk after phy_init() as we want to optimize the logic of reset control and reuse rockchip_pcie_init_port() later which should fully follow the cold boot procedure of ROM code. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org>
2016-11-24 09:54:21 +08:00
udelay(10);
err = reset_control_deassert(rockchip->pm_rst);
if (err) {
dev_err(dev, "deassert pm_rst err %d\n", err);
PCI: rockchip: Clean up PHY if driver probe or resume fails We observed that the clk_pciephy_ref is still enabled when we fail to probe the driver. root@linaro-alip:~# grep pcie /sys/kernel/debug/clk/clk_summary clk_pciephy_ref 1 1 24000000 0 0 clk_pcie_pm 0 0 24000000 0 0 clk_pcie_core_cru 0 0 125000000 0 0 clk_pciephy_ref100m 0 0 100000000 0 0 aclk_pcie 0 0 148500000 0 0 aclk_perf_pcie 0 0 148500000 0 0 pclk_pcie 0 0 37125000 0 0 clk_pcie_core 0 0 0 0 0 clk_pciephy_ref is used by the PHY driver and we need to properly disable it for this case. Add error handling in rockchip_pcie_init_port() and rockchip_pcie_resume_noirq() to fix this issue. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-08-23 15:03:07 +08:00
goto err_exit_phy;
PCI: rockchip: Move the deassert of pm/aclk/pclk after phy_init() Move deassert of pm/aclk/pclk after phy_init() as we want to optimize the logic of reset control and reuse rockchip_pcie_init_port() later which should fully follow the cold boot procedure of ROM code. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org>
2016-11-24 09:54:21 +08:00
}
err = reset_control_deassert(rockchip->aclk_rst);
if (err) {
dev_err(dev, "deassert aclk_rst err %d\n", err);
PCI: rockchip: Clean up PHY if driver probe or resume fails We observed that the clk_pciephy_ref is still enabled when we fail to probe the driver. root@linaro-alip:~# grep pcie /sys/kernel/debug/clk/clk_summary clk_pciephy_ref 1 1 24000000 0 0 clk_pcie_pm 0 0 24000000 0 0 clk_pcie_core_cru 0 0 125000000 0 0 clk_pciephy_ref100m 0 0 100000000 0 0 aclk_pcie 0 0 148500000 0 0 aclk_perf_pcie 0 0 148500000 0 0 pclk_pcie 0 0 37125000 0 0 clk_pcie_core 0 0 0 0 0 clk_pciephy_ref is used by the PHY driver and we need to properly disable it for this case. Add error handling in rockchip_pcie_init_port() and rockchip_pcie_resume_noirq() to fix this issue. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-08-23 15:03:07 +08:00
goto err_exit_phy;
PCI: rockchip: Move the deassert of pm/aclk/pclk after phy_init() Move deassert of pm/aclk/pclk after phy_init() as we want to optimize the logic of reset control and reuse rockchip_pcie_init_port() later which should fully follow the cold boot procedure of ROM code. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org>
2016-11-24 09:54:21 +08:00
}
err = reset_control_deassert(rockchip->pclk_rst);
if (err) {
dev_err(dev, "deassert pclk_rst err %d\n", err);
PCI: rockchip: Clean up PHY if driver probe or resume fails We observed that the clk_pciephy_ref is still enabled when we fail to probe the driver. root@linaro-alip:~# grep pcie /sys/kernel/debug/clk/clk_summary clk_pciephy_ref 1 1 24000000 0 0 clk_pcie_pm 0 0 24000000 0 0 clk_pcie_core_cru 0 0 125000000 0 0 clk_pciephy_ref100m 0 0 100000000 0 0 aclk_pcie 0 0 148500000 0 0 aclk_perf_pcie 0 0 148500000 0 0 pclk_pcie 0 0 37125000 0 0 clk_pcie_core 0 0 0 0 0 clk_pciephy_ref is used by the PHY driver and we need to properly disable it for this case. Add error handling in rockchip_pcie_init_port() and rockchip_pcie_resume_noirq() to fix this issue. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-08-23 15:03:07 +08:00
goto err_exit_phy;
PCI: rockchip: Move the deassert of pm/aclk/pclk after phy_init() Move deassert of pm/aclk/pclk after phy_init() as we want to optimize the logic of reset control and reuse rockchip_pcie_init_port() later which should fully follow the cold boot procedure of ROM code. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org>
2016-11-24 09:54:21 +08:00
}
PCI: rockchip: Specify the link capability rk3399 supports PCIe 2.x link speeds marginally at best, and on some boards, the link won't train at 5 GT/s at all. Rather than sacrifice 500ms waiting for training that will never happen, let's use the helper function, of_pci_get_max_link_speed(), to get the max link speed from DT and specify link capability. Signed-off-by: Brian Norris <briannorris@chromium.org> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-12-08 05:05:59 +08:00
if (rockchip->link_gen == 2)
rockchip_pcie_write(rockchip, PCIE_CLIENT_GEN_SEL_2,
PCIE_CLIENT_CONFIG);
else
rockchip_pcie_write(rockchip, PCIE_CLIENT_GEN_SEL_1,
PCIE_CLIENT_CONFIG);
PCI: rockchip: Split out common function to init controller Most of the initialization are used for both of RC driver and EP driver; factor the initialization out to a new function, rockchip_pcie_init_port(), in pcie-rockchip.c and rename the original function to rockchip_pcie_host_init_port() to avoid confusion. No functional changed intended. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com>
2018-05-09 09:12:24 +08:00
regs = PCIE_CLIENT_LINK_TRAIN_ENABLE | PCIE_CLIENT_ARI_ENABLE |
PCIE_CLIENT_CONF_LANE_NUM(rockchip->lanes);
if (rockchip->is_rc)
regs |= PCIE_CLIENT_CONF_ENABLE | PCIE_CLIENT_MODE_RC;
else
regs |= PCIE_CLIENT_CONF_DISABLE | PCIE_CLIENT_MODE_EP;
rockchip_pcie_write(rockchip, regs, PCIE_CLIENT_CONFIG);
PCI: rockchip: Add Rockchip PCIe controller support Add support for the Rockchip PCIe controller found on RK3399 SoC platform. [bhelgaas: fold in Brian's rockchip_pcie_client_irq_handler() OR fix, other fixes and cleanups from Guenter Roeck <linux@roeck-us.net> and me, uninitialized variable fix from Arnd Bergmann <arnd@arndb.de>] Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org>
2016-09-04 00:41:09 +08:00
PCI: rockchip: Add per-lane PHY support We distinguish the legacy PHY from newer per-lane PHYs by adding legacy_phy flag. Note that the legacy PHY is still the first option to be searched in order not to break the backward compatibility of DTB. Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> [bhelgaas: tidy rockchip_pcie_get_phys()] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-08-26 04:59:01 +08:00
for (i = 0; i < MAX_LANE_NUM; i++) {
err = phy_power_on(rockchip->phys[i]);
if (err) {
dev_err(dev, "power on phy%d err %d\n", i, err);
PCI: rockchip: Clean up PHY if driver probe or resume fails We observed that the clk_pciephy_ref is still enabled when we fail to probe the driver. root@linaro-alip:~# grep pcie /sys/kernel/debug/clk/clk_summary clk_pciephy_ref 1 1 24000000 0 0 clk_pcie_pm 0 0 24000000 0 0 clk_pcie_core_cru 0 0 125000000 0 0 clk_pciephy_ref100m 0 0 100000000 0 0 aclk_pcie 0 0 148500000 0 0 aclk_perf_pcie 0 0 148500000 0 0 pclk_pcie 0 0 37125000 0 0 clk_pcie_core 0 0 0 0 0 clk_pciephy_ref is used by the PHY driver and we need to properly disable it for this case. Add error handling in rockchip_pcie_init_port() and rockchip_pcie_resume_noirq() to fix this issue. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-08-23 15:03:07 +08:00
goto err_power_off_phy;
PCI: rockchip: Add per-lane PHY support We distinguish the legacy PHY from newer per-lane PHYs by adding legacy_phy flag. Note that the legacy PHY is still the first option to be searched in order not to break the backward compatibility of DTB. Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> [bhelgaas: tidy rockchip_pcie_get_phys()] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-08-26 04:59:01 +08:00
}
PCI: rockchip: Add Rockchip PCIe controller support Add support for the Rockchip PCIe controller found on RK3399 SoC platform. [bhelgaas: fold in Brian's rockchip_pcie_client_irq_handler() OR fix, other fixes and cleanups from Guenter Roeck <linux@roeck-us.net> and me, uninitialized variable fix from Arnd Bergmann <arnd@arndb.de>] Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org>
2016-09-04 00:41:09 +08:00
}
PCI: rockchip: Improve the deassert sequence of four reset pins Per TRM, we need to deassert the four reset pins simultaneously. Currently the reset framework doesn't support that so we did it one by one. It seems no side effect found but it does impact the state machine of controller, so sometimes the change speed bit is not set when sending training sequence from recover state. After the silicon RTL review from SoC guys, we don't need to do the sequence recommended by TRM, and could just move the deassert of mgmt_sticky_rst to the first place. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-09-23 10:05:59 +08:00
/*
* Please don't reorder the deassert sequence of the following
* four reset pins.
*/
err = reset_control_deassert(rockchip->mgmt_sticky_rst);
PCI: rockchip: Add Rockchip PCIe controller support Add support for the Rockchip PCIe controller found on RK3399 SoC platform. [bhelgaas: fold in Brian's rockchip_pcie_client_irq_handler() OR fix, other fixes and cleanups from Guenter Roeck <linux@roeck-us.net> and me, uninitialized variable fix from Arnd Bergmann <arnd@arndb.de>] Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org>
2016-09-04 00:41:09 +08:00
if (err) {
PCI: rockchip: Improve the deassert sequence of four reset pins Per TRM, we need to deassert the four reset pins simultaneously. Currently the reset framework doesn't support that so we did it one by one. It seems no side effect found but it does impact the state machine of controller, so sometimes the change speed bit is not set when sending training sequence from recover state. After the silicon RTL review from SoC guys, we don't need to do the sequence recommended by TRM, and could just move the deassert of mgmt_sticky_rst to the first place. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-09-23 10:05:59 +08:00
dev_err(dev, "deassert mgmt_sticky_rst err %d\n", err);
PCI: rockchip: Clean up PHY if driver probe or resume fails We observed that the clk_pciephy_ref is still enabled when we fail to probe the driver. root@linaro-alip:~# grep pcie /sys/kernel/debug/clk/clk_summary clk_pciephy_ref 1 1 24000000 0 0 clk_pcie_pm 0 0 24000000 0 0 clk_pcie_core_cru 0 0 125000000 0 0 clk_pciephy_ref100m 0 0 100000000 0 0 aclk_pcie 0 0 148500000 0 0 aclk_perf_pcie 0 0 148500000 0 0 pclk_pcie 0 0 37125000 0 0 clk_pcie_core 0 0 0 0 0 clk_pciephy_ref is used by the PHY driver and we need to properly disable it for this case. Add error handling in rockchip_pcie_init_port() and rockchip_pcie_resume_noirq() to fix this issue. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-08-23 15:03:07 +08:00
goto err_power_off_phy;
PCI: rockchip: Add Rockchip PCIe controller support Add support for the Rockchip PCIe controller found on RK3399 SoC platform. [bhelgaas: fold in Brian's rockchip_pcie_client_irq_handler() OR fix, other fixes and cleanups from Guenter Roeck <linux@roeck-us.net> and me, uninitialized variable fix from Arnd Bergmann <arnd@arndb.de>] Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org>
2016-09-04 00:41:09 +08:00
}
PCI: rockchip: Improve the deassert sequence of four reset pins Per TRM, we need to deassert the four reset pins simultaneously. Currently the reset framework doesn't support that so we did it one by one. It seems no side effect found but it does impact the state machine of controller, so sometimes the change speed bit is not set when sending training sequence from recover state. After the silicon RTL review from SoC guys, we don't need to do the sequence recommended by TRM, and could just move the deassert of mgmt_sticky_rst to the first place. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-09-23 10:05:59 +08:00
err = reset_control_deassert(rockchip->core_rst);
PCI: rockchip: Add Rockchip PCIe controller support Add support for the Rockchip PCIe controller found on RK3399 SoC platform. [bhelgaas: fold in Brian's rockchip_pcie_client_irq_handler() OR fix, other fixes and cleanups from Guenter Roeck <linux@roeck-us.net> and me, uninitialized variable fix from Arnd Bergmann <arnd@arndb.de>] Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org>
2016-09-04 00:41:09 +08:00
if (err) {
PCI: rockchip: Improve the deassert sequence of four reset pins Per TRM, we need to deassert the four reset pins simultaneously. Currently the reset framework doesn't support that so we did it one by one. It seems no side effect found but it does impact the state machine of controller, so sometimes the change speed bit is not set when sending training sequence from recover state. After the silicon RTL review from SoC guys, we don't need to do the sequence recommended by TRM, and could just move the deassert of mgmt_sticky_rst to the first place. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-09-23 10:05:59 +08:00
dev_err(dev, "deassert core_rst err %d\n", err);
PCI: rockchip: Clean up PHY if driver probe or resume fails We observed that the clk_pciephy_ref is still enabled when we fail to probe the driver. root@linaro-alip:~# grep pcie /sys/kernel/debug/clk/clk_summary clk_pciephy_ref 1 1 24000000 0 0 clk_pcie_pm 0 0 24000000 0 0 clk_pcie_core_cru 0 0 125000000 0 0 clk_pciephy_ref100m 0 0 100000000 0 0 aclk_pcie 0 0 148500000 0 0 aclk_perf_pcie 0 0 148500000 0 0 pclk_pcie 0 0 37125000 0 0 clk_pcie_core 0 0 0 0 0 clk_pciephy_ref is used by the PHY driver and we need to properly disable it for this case. Add error handling in rockchip_pcie_init_port() and rockchip_pcie_resume_noirq() to fix this issue. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-08-23 15:03:07 +08:00
goto err_power_off_phy;
PCI: rockchip: Add Rockchip PCIe controller support Add support for the Rockchip PCIe controller found on RK3399 SoC platform. [bhelgaas: fold in Brian's rockchip_pcie_client_irq_handler() OR fix, other fixes and cleanups from Guenter Roeck <linux@roeck-us.net> and me, uninitialized variable fix from Arnd Bergmann <arnd@arndb.de>] Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org>
2016-09-04 00:41:09 +08:00
}
PCI: rockchip: Improve the deassert sequence of four reset pins Per TRM, we need to deassert the four reset pins simultaneously. Currently the reset framework doesn't support that so we did it one by one. It seems no side effect found but it does impact the state machine of controller, so sometimes the change speed bit is not set when sending training sequence from recover state. After the silicon RTL review from SoC guys, we don't need to do the sequence recommended by TRM, and could just move the deassert of mgmt_sticky_rst to the first place. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-09-23 10:05:59 +08:00
err = reset_control_deassert(rockchip->mgmt_rst);
PCI: rockchip: Add Rockchip PCIe controller support Add support for the Rockchip PCIe controller found on RK3399 SoC platform. [bhelgaas: fold in Brian's rockchip_pcie_client_irq_handler() OR fix, other fixes and cleanups from Guenter Roeck <linux@roeck-us.net> and me, uninitialized variable fix from Arnd Bergmann <arnd@arndb.de>] Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org>
2016-09-04 00:41:09 +08:00
if (err) {
PCI: rockchip: Improve the deassert sequence of four reset pins Per TRM, we need to deassert the four reset pins simultaneously. Currently the reset framework doesn't support that so we did it one by one. It seems no side effect found but it does impact the state machine of controller, so sometimes the change speed bit is not set when sending training sequence from recover state. After the silicon RTL review from SoC guys, we don't need to do the sequence recommended by TRM, and could just move the deassert of mgmt_sticky_rst to the first place. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-09-23 10:05:59 +08:00
dev_err(dev, "deassert mgmt_rst err %d\n", err);
PCI: rockchip: Clean up PHY if driver probe or resume fails We observed that the clk_pciephy_ref is still enabled when we fail to probe the driver. root@linaro-alip:~# grep pcie /sys/kernel/debug/clk/clk_summary clk_pciephy_ref 1 1 24000000 0 0 clk_pcie_pm 0 0 24000000 0 0 clk_pcie_core_cru 0 0 125000000 0 0 clk_pciephy_ref100m 0 0 100000000 0 0 aclk_pcie 0 0 148500000 0 0 aclk_perf_pcie 0 0 148500000 0 0 pclk_pcie 0 0 37125000 0 0 clk_pcie_core 0 0 0 0 0 clk_pciephy_ref is used by the PHY driver and we need to properly disable it for this case. Add error handling in rockchip_pcie_init_port() and rockchip_pcie_resume_noirq() to fix this issue. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-08-23 15:03:07 +08:00
goto err_power_off_phy;
PCI: rockchip: Add Rockchip PCIe controller support Add support for the Rockchip PCIe controller found on RK3399 SoC platform. [bhelgaas: fold in Brian's rockchip_pcie_client_irq_handler() OR fix, other fixes and cleanups from Guenter Roeck <linux@roeck-us.net> and me, uninitialized variable fix from Arnd Bergmann <arnd@arndb.de>] Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org>
2016-09-04 00:41:09 +08:00
}
err = reset_control_deassert(rockchip->pipe_rst);
if (err) {
dev_err(dev, "deassert pipe_rst err %d\n", err);
PCI: rockchip: Clean up PHY if driver probe or resume fails We observed that the clk_pciephy_ref is still enabled when we fail to probe the driver. root@linaro-alip:~# grep pcie /sys/kernel/debug/clk/clk_summary clk_pciephy_ref 1 1 24000000 0 0 clk_pcie_pm 0 0 24000000 0 0 clk_pcie_core_cru 0 0 125000000 0 0 clk_pciephy_ref100m 0 0 100000000 0 0 aclk_pcie 0 0 148500000 0 0 aclk_perf_pcie 0 0 148500000 0 0 pclk_pcie 0 0 37125000 0 0 clk_pcie_core 0 0 0 0 0 clk_pciephy_ref is used by the PHY driver and we need to properly disable it for this case. Add error handling in rockchip_pcie_init_port() and rockchip_pcie_resume_noirq() to fix this issue. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-08-23 15:03:07 +08:00
goto err_power_off_phy;
PCI: rockchip: Add Rockchip PCIe controller support Add support for the Rockchip PCIe controller found on RK3399 SoC platform. [bhelgaas: fold in Brian's rockchip_pcie_client_irq_handler() OR fix, other fixes and cleanups from Guenter Roeck <linux@roeck-us.net> and me, uninitialized variable fix from Arnd Bergmann <arnd@arndb.de>] Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org>
2016-09-04 00:41:09 +08:00
}
PCI: rockchip: Split out common function to init controller Most of the initialization are used for both of RC driver and EP driver; factor the initialization out to a new function, rockchip_pcie_init_port(), in pcie-rockchip.c and rename the original function to rockchip_pcie_host_init_port() to avoid confusion. No functional changed intended. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com>
2018-05-09 09:12:24 +08:00
return 0;
err_power_off_phy:
while (i--)
phy_power_off(rockchip->phys[i]);
i = MAX_LANE_NUM;
err_exit_phy:
while (i--)
phy_exit(rockchip->phys[i]);
return err;
}
EXPORT_SYMBOL_GPL(rockchip_pcie_init_port);
PCI: rockchip: Add Rockchip PCIe controller support Add support for the Rockchip PCIe controller found on RK3399 SoC platform. [bhelgaas: fold in Brian's rockchip_pcie_client_irq_handler() OR fix, other fixes and cleanups from Guenter Roeck <linux@roeck-us.net> and me, uninitialized variable fix from Arnd Bergmann <arnd@arndb.de>] Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org>
2016-09-04 00:41:09 +08:00
PCI: rockchip: Separate common code from RC driver In preparation for introducing EP driver for Rockchip PCIe controller, rename the RC driver from pcie-rockchip.c to pcie-rockchip-host.c, and only leave some common functions in pcie-rockchip.c in order to be reused for both of RC driver and EP driver. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com>
2018-05-09 09:11:49 +08:00
int rockchip_pcie_get_phys(struct rockchip_pcie *rockchip)
PCI: rockchip: Factor out rockchip_pcie_get_phys() We plan to introduce per-lane PHYs, so factor out rockchip_pcie_get_phys() to make it easier in the future. No functional change intended. Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-07-19 17:55:12 +08:00
{
struct device *dev = rockchip->dev;
PCI: rockchip: Add per-lane PHY support We distinguish the legacy PHY from newer per-lane PHYs by adding legacy_phy flag. Note that the legacy PHY is still the first option to be searched in order not to break the backward compatibility of DTB. Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> [bhelgaas: tidy rockchip_pcie_get_phys()] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-08-26 04:59:01 +08:00
struct phy *phy;
char *name;
u32 i;
PCI: rockchip: Add Rockchip PCIe controller support Add support for the Rockchip PCIe controller found on RK3399 SoC platform. [bhelgaas: fold in Brian's rockchip_pcie_client_irq_handler() OR fix, other fixes and cleanups from Guenter Roeck <linux@roeck-us.net> and me, uninitialized variable fix from Arnd Bergmann <arnd@arndb.de>] Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org>
2016-09-04 00:41:09 +08:00
PCI: rockchip: Add per-lane PHY support We distinguish the legacy PHY from newer per-lane PHYs by adding legacy_phy flag. Note that the legacy PHY is still the first option to be searched in order not to break the backward compatibility of DTB. Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> [bhelgaas: tidy rockchip_pcie_get_phys()] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-08-26 04:59:01 +08:00
phy = devm_phy_get(dev, "pcie-phy");
if (!IS_ERR(phy)) {
rockchip->legacy_phy = true;
rockchip->phys[0] = phy;
dev_warn(dev, "legacy phy model is deprecated!\n");
return 0;
PCI: rockchip: Add Rockchip PCIe controller support Add support for the Rockchip PCIe controller found on RK3399 SoC platform. [bhelgaas: fold in Brian's rockchip_pcie_client_irq_handler() OR fix, other fixes and cleanups from Guenter Roeck <linux@roeck-us.net> and me, uninitialized variable fix from Arnd Bergmann <arnd@arndb.de>] Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org>
2016-09-04 00:41:09 +08:00
}
PCI: rockchip: Add per-lane PHY support We distinguish the legacy PHY from newer per-lane PHYs by adding legacy_phy flag. Note that the legacy PHY is still the first option to be searched in order not to break the backward compatibility of DTB. Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> [bhelgaas: tidy rockchip_pcie_get_phys()] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-08-26 04:59:01 +08:00
if (PTR_ERR(phy) == -EPROBE_DEFER)
return PTR_ERR(phy);
PCI: rockchip: Add Rockchip PCIe controller support Add support for the Rockchip PCIe controller found on RK3399 SoC platform. [bhelgaas: fold in Brian's rockchip_pcie_client_irq_handler() OR fix, other fixes and cleanups from Guenter Roeck <linux@roeck-us.net> and me, uninitialized variable fix from Arnd Bergmann <arnd@arndb.de>] Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org>
2016-09-04 00:41:09 +08:00
PCI: rockchip: Add per-lane PHY support We distinguish the legacy PHY from newer per-lane PHYs by adding legacy_phy flag. Note that the legacy PHY is still the first option to be searched in order not to break the backward compatibility of DTB. Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> [bhelgaas: tidy rockchip_pcie_get_phys()] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-08-26 04:59:01 +08:00
dev_dbg(dev, "missing legacy phy; search for per-lane PHY\n");
PCI: rockchip: Add Rockchip PCIe controller support Add support for the Rockchip PCIe controller found on RK3399 SoC platform. [bhelgaas: fold in Brian's rockchip_pcie_client_irq_handler() OR fix, other fixes and cleanups from Guenter Roeck <linux@roeck-us.net> and me, uninitialized variable fix from Arnd Bergmann <arnd@arndb.de>] Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org>
2016-09-04 00:41:09 +08:00
PCI: rockchip: Idle inactive PHY(s) Check the status of all lanes and idle the inactive one(s). Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> [bhelgaas: always set lanes_map, even for legacy_phy case] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-07-19 17:55:15 +08:00
for (i = 0; i < MAX_LANE_NUM; i++) {
PCI: rockchip: Add per-lane PHY support We distinguish the legacy PHY from newer per-lane PHYs by adding legacy_phy flag. Note that the legacy PHY is still the first option to be searched in order not to break the backward compatibility of DTB. Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> [bhelgaas: tidy rockchip_pcie_get_phys()] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-08-26 04:59:01 +08:00
name = kasprintf(GFP_KERNEL, "pcie-phy-%u", i);
if (!name)
return -ENOMEM;
PCI: rockchip: Factor out rockchip_pcie_get_phys() We plan to introduce per-lane PHYs, so factor out rockchip_pcie_get_phys() to make it easier in the future. No functional change intended. Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-07-19 17:55:12 +08:00
PCI: rockchip: Add per-lane PHY support We distinguish the legacy PHY from newer per-lane PHYs by adding legacy_phy flag. Note that the legacy PHY is still the first option to be searched in order not to break the backward compatibility of DTB. Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> [bhelgaas: tidy rockchip_pcie_get_phys()] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-08-26 04:59:01 +08:00
phy = devm_of_phy_get(dev, dev->of_node, name);
kfree(name);
if (IS_ERR(phy)) {
if (PTR_ERR(phy) != -EPROBE_DEFER)
dev_err(dev, "missing phy for lane %d: %ld\n",
i, PTR_ERR(phy));
return PTR_ERR(phy);
PCI: rockchip: Idle inactive PHY(s) Check the status of all lanes and idle the inactive one(s). Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> [bhelgaas: always set lanes_map, even for legacy_phy case] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-07-19 17:55:15 +08:00
}
PCI: rockchip: Add per-lane PHY support We distinguish the legacy PHY from newer per-lane PHYs by adding legacy_phy flag. Note that the legacy PHY is still the first option to be searched in order not to break the backward compatibility of DTB. Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> [bhelgaas: tidy rockchip_pcie_get_phys()] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-08-26 04:59:01 +08:00
rockchip->phys[i] = phy;
PCI: rockchip: Disable RC's ASPM L0s based on DT "aspm-no-l0s" Rockchip's RC produces a 100MHz reference clock but there are two methods for the PHY to generate it: (1) Use the system PLL to generate a 100MHz clock. The PHY will relock it, filter signal noise, and output the reference clock. ASPM L0s works correctly, but circuit noise issues make it difficult to pass the TX compatibility test. (2) Share the SoC's 24MHZ crystal oscillator with the PHY and force the PHY's PLL to generate 100MHz internally. In this case, exit from ASPM L0s sometimes fails due to a design error in the RC receiver circuit. Even if we use extended-synch, the PHY sometimes fails to relock the bits from FTS, which will hang the system. We want the flexibility to use both clocking methods, so add a DT property, "aspm-no-l0s". If that's present, disable L0s to avoid the issues with case (2). [bhelgaas: changelog] Reported-by: Jeffy Chen <jeffy.chen@rock-chips.com> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org> Acked-by: Rob Herring <robh@kernel.org>
2017-01-12 09:53:17 +08:00
}
PCI: rockchip: Add Rockchip PCIe controller support Add support for the Rockchip PCIe controller found on RK3399 SoC platform. [bhelgaas: fold in Brian's rockchip_pcie_client_irq_handler() OR fix, other fixes and cleanups from Guenter Roeck <linux@roeck-us.net> and me, uninitialized variable fix from Arnd Bergmann <arnd@arndb.de>] Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org>
2016-09-04 00:41:09 +08:00
return 0;
}
PCI: rockchip: Separate common code from RC driver In preparation for introducing EP driver for Rockchip PCIe controller, rename the RC driver from pcie-rockchip.c to pcie-rockchip-host.c, and only leave some common functions in pcie-rockchip.c in order to be reused for both of RC driver and EP driver. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com>
2018-05-09 09:11:49 +08:00
EXPORT_SYMBOL_GPL(rockchip_pcie_get_phys);
PCI: rockchip: Add Rockchip PCIe controller support Add support for the Rockchip PCIe controller found on RK3399 SoC platform. [bhelgaas: fold in Brian's rockchip_pcie_client_irq_handler() OR fix, other fixes and cleanups from Guenter Roeck <linux@roeck-us.net> and me, uninitialized variable fix from Arnd Bergmann <arnd@arndb.de>] Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org>
2016-09-04 00:41:09 +08:00
PCI: rockchip: Separate common code from RC driver In preparation for introducing EP driver for Rockchip PCIe controller, rename the RC driver from pcie-rockchip.c to pcie-rockchip-host.c, and only leave some common functions in pcie-rockchip.c in order to be reused for both of RC driver and EP driver. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com>
2018-05-09 09:11:49 +08:00
void rockchip_pcie_deinit_phys(struct rockchip_pcie *rockchip)
PCI: rockchip: Factor out rockchip_pcie_deinit_phys() Factor out rockchip_pcie_deinit_phys() so it can be reused by rockchip_pcie_suspend_noirq() and rockchip_pcie_remove(). No functional change intended. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-08-23 15:02:49 +08:00
{
int i;
for (i = 0; i < MAX_LANE_NUM; i++) {
/* inactive lanes are already powered off */
if (rockchip->lanes_map & BIT(i))
phy_power_off(rockchip->phys[i]);
phy_exit(rockchip->phys[i]);
}
}
PCI: rockchip: Separate common code from RC driver In preparation for introducing EP driver for Rockchip PCIe controller, rename the RC driver from pcie-rockchip.c to pcie-rockchip-host.c, and only leave some common functions in pcie-rockchip.c in order to be reused for both of RC driver and EP driver. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com>
2018-05-09 09:11:49 +08:00
EXPORT_SYMBOL_GPL(rockchip_pcie_deinit_phys);
PCI: rockchip: Factor out rockchip_pcie_deinit_phys() Factor out rockchip_pcie_deinit_phys() so it can be reused by rockchip_pcie_suspend_noirq() and rockchip_pcie_remove(). No functional change intended. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-08-23 15:02:49 +08:00
PCI: rockchip: Separate common code from RC driver In preparation for introducing EP driver for Rockchip PCIe controller, rename the RC driver from pcie-rockchip.c to pcie-rockchip-host.c, and only leave some common functions in pcie-rockchip.c in order to be reused for both of RC driver and EP driver. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com>
2018-05-09 09:11:49 +08:00
int rockchip_pcie_enable_clocks(struct rockchip_pcie *rockchip)
PCI: rockchip: Add Rockchip PCIe controller support Add support for the Rockchip PCIe controller found on RK3399 SoC platform. [bhelgaas: fold in Brian's rockchip_pcie_client_irq_handler() OR fix, other fixes and cleanups from Guenter Roeck <linux@roeck-us.net> and me, uninitialized variable fix from Arnd Bergmann <arnd@arndb.de>] Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org>
2016-09-04 00:41:09 +08:00
{
struct device *dev = rockchip->dev;
PCI: rockchip: Factor out rockchip_pcie_enable_clocks() Factor out rockchip_pcie_enable_clocks() so it can be reused by rockchip_pcie_resume_noirq() and rockchip_pcie_probe(). No functional change intended, but it does change the order of unpreparing clocks in the rockchip_pcie_resume_noirq() error path. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-08-23 15:02:19 +08:00
int err;
PCI: rockchip: Add Rockchip PCIe controller support Add support for the Rockchip PCIe controller found on RK3399 SoC platform. [bhelgaas: fold in Brian's rockchip_pcie_client_irq_handler() OR fix, other fixes and cleanups from Guenter Roeck <linux@roeck-us.net> and me, uninitialized variable fix from Arnd Bergmann <arnd@arndb.de>] Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org>
2016-09-04 00:41:09 +08:00
PCI: rockchip: Factor out rockchip_pcie_enable_clocks() Factor out rockchip_pcie_enable_clocks() so it can be reused by rockchip_pcie_resume_noirq() and rockchip_pcie_probe(). No functional change intended, but it does change the order of unpreparing clocks in the rockchip_pcie_resume_noirq() error path. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-08-23 15:02:19 +08:00
err = clk_prepare_enable(rockchip->aclk_pcie);
if (err) {
dev_err(dev, "unable to enable aclk_pcie clock\n");
return err;
}
PCI: rockchip: Add Rockchip PCIe controller support Add support for the Rockchip PCIe controller found on RK3399 SoC platform. [bhelgaas: fold in Brian's rockchip_pcie_client_irq_handler() OR fix, other fixes and cleanups from Guenter Roeck <linux@roeck-us.net> and me, uninitialized variable fix from Arnd Bergmann <arnd@arndb.de>] Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org>
2016-09-04 00:41:09 +08:00
PCI: rockchip: Factor out rockchip_pcie_enable_clocks() Factor out rockchip_pcie_enable_clocks() so it can be reused by rockchip_pcie_resume_noirq() and rockchip_pcie_probe(). No functional change intended, but it does change the order of unpreparing clocks in the rockchip_pcie_resume_noirq() error path. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-08-23 15:02:19 +08:00
err = clk_prepare_enable(rockchip->aclk_perf_pcie);
if (err) {
dev_err(dev, "unable to enable aclk_perf_pcie clock\n");
goto err_aclk_perf_pcie;
}
PCI: rockchip: Add Rockchip PCIe controller support Add support for the Rockchip PCIe controller found on RK3399 SoC platform. [bhelgaas: fold in Brian's rockchip_pcie_client_irq_handler() OR fix, other fixes and cleanups from Guenter Roeck <linux@roeck-us.net> and me, uninitialized variable fix from Arnd Bergmann <arnd@arndb.de>] Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org>
2016-09-04 00:41:09 +08:00
PCI: rockchip: Factor out rockchip_pcie_enable_clocks() Factor out rockchip_pcie_enable_clocks() so it can be reused by rockchip_pcie_resume_noirq() and rockchip_pcie_probe(). No functional change intended, but it does change the order of unpreparing clocks in the rockchip_pcie_resume_noirq() error path. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-08-23 15:02:19 +08:00
err = clk_prepare_enable(rockchip->hclk_pcie);
if (err) {
dev_err(dev, "unable to enable hclk_pcie clock\n");
goto err_hclk_pcie;
}
err = clk_prepare_enable(rockchip->clk_pcie_pm);
if (err) {
dev_err(dev, "unable to enable clk_pcie_pm clock\n");
goto err_clk_pcie_pm;
}
return 0;
err_clk_pcie_pm:
clk_disable_unprepare(rockchip->hclk_pcie);
err_hclk_pcie:
clk_disable_unprepare(rockchip->aclk_perf_pcie);
err_aclk_perf_pcie:
clk_disable_unprepare(rockchip->aclk_pcie);
return err;
}
PCI: rockchip: Separate common code from RC driver In preparation for introducing EP driver for Rockchip PCIe controller, rename the RC driver from pcie-rockchip.c to pcie-rockchip-host.c, and only leave some common functions in pcie-rockchip.c in order to be reused for both of RC driver and EP driver. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com>
2018-05-09 09:11:49 +08:00
EXPORT_SYMBOL_GPL(rockchip_pcie_enable_clocks);
PCI: rockchip: Factor out rockchip_pcie_enable_clocks() Factor out rockchip_pcie_enable_clocks() so it can be reused by rockchip_pcie_resume_noirq() and rockchip_pcie_probe(). No functional change intended, but it does change the order of unpreparing clocks in the rockchip_pcie_resume_noirq() error path. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-08-23 15:02:19 +08:00
PCI: rockchip: Separate common code from RC driver In preparation for introducing EP driver for Rockchip PCIe controller, rename the RC driver from pcie-rockchip.c to pcie-rockchip-host.c, and only leave some common functions in pcie-rockchip.c in order to be reused for both of RC driver and EP driver. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com>
2018-05-09 09:11:49 +08:00
void rockchip_pcie_disable_clocks(void *data)
PCI: rockchip: Factor out rockchip_pcie_disable_clocks() Factor out rockchip_pcie_disable_clocks() so it can be reused by other functions. No functional change intended, but it does change the order of unpreparing clocks in the rockchip_pcie_resume_noirq() error path so it matches the other paths. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-08-23 15:02:28 +08:00
{
struct rockchip_pcie *rockchip = data;
clk_disable_unprepare(rockchip->clk_pcie_pm);
clk_disable_unprepare(rockchip->hclk_pcie);
clk_disable_unprepare(rockchip->aclk_perf_pcie);
clk_disable_unprepare(rockchip->aclk_pcie);
}
PCI: rockchip: Separate common code from RC driver In preparation for introducing EP driver for Rockchip PCIe controller, rename the RC driver from pcie-rockchip.c to pcie-rockchip-host.c, and only leave some common functions in pcie-rockchip.c in order to be reused for both of RC driver and EP driver. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com>
2018-05-09 09:11:49 +08:00
EXPORT_SYMBOL_GPL(rockchip_pcie_disable_clocks);
PCI: rockchip: Factor out rockchip_pcie_disable_clocks() Factor out rockchip_pcie_disable_clocks() so it can be reused by other functions. No functional change intended, but it does change the order of unpreparing clocks in the rockchip_pcie_resume_noirq() error path so it matches the other paths. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-08-23 15:02:28 +08:00
PCI: rockchip: Separate common code from RC driver In preparation for introducing EP driver for Rockchip PCIe controller, rename the RC driver from pcie-rockchip.c to pcie-rockchip-host.c, and only leave some common functions in pcie-rockchip.c in order to be reused for both of RC driver and EP driver. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com>
2018-05-09 09:11:49 +08:00
void rockchip_pcie_cfg_configuration_accesses(
struct rockchip_pcie *rockchip, u32 type)
PCI: rockchip: Add remove() support Currently, if we try to unbind the platform device, the remove will succeed, but the removal won't undo most of the registration, leaving partially-configured PCI devices in the system. This allows, for example, a simple 'lspci' to crash the system, as it will try to touch the freed (via devm_*) driver structures, e.g., on RK3399: # echo f8000000.pcie > /sys/bus/platform/drivers/rockchip-pcie/unbind # lspci So let's implement device remove(). Signed-off-by: Brian Norris <briannorris@chromium.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Shawn Lin <shawn.lin@rock-chips.com>
2017-03-10 10:46:15 +08:00
{
PCI: rockchip: Separate common code from RC driver In preparation for introducing EP driver for Rockchip PCIe controller, rename the RC driver from pcie-rockchip.c to pcie-rockchip-host.c, and only leave some common functions in pcie-rockchip.c in order to be reused for both of RC driver and EP driver. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com>
2018-05-09 09:11:49 +08:00
u32 ob_desc_0;
PCI: rockchip: Add remove() support Currently, if we try to unbind the platform device, the remove will succeed, but the removal won't undo most of the registration, leaving partially-configured PCI devices in the system. This allows, for example, a simple 'lspci' to crash the system, as it will try to touch the freed (via devm_*) driver structures, e.g., on RK3399: # echo f8000000.pcie > /sys/bus/platform/drivers/rockchip-pcie/unbind # lspci So let's implement device remove(). Signed-off-by: Brian Norris <briannorris@chromium.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Shawn Lin <shawn.lin@rock-chips.com>
2017-03-10 10:46:15 +08:00
PCI: rockchip: Separate common code from RC driver In preparation for introducing EP driver for Rockchip PCIe controller, rename the RC driver from pcie-rockchip.c to pcie-rockchip-host.c, and only leave some common functions in pcie-rockchip.c in order to be reused for both of RC driver and EP driver. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com>
2018-05-09 09:11:49 +08:00
/* Configuration Accesses for region 0 */
rockchip_pcie_write(rockchip, 0x0, PCIE_RC_BAR_CONF);
PCI: rockchip: Add remove() support Currently, if we try to unbind the platform device, the remove will succeed, but the removal won't undo most of the registration, leaving partially-configured PCI devices in the system. This allows, for example, a simple 'lspci' to crash the system, as it will try to touch the freed (via devm_*) driver structures, e.g., on RK3399: # echo f8000000.pcie > /sys/bus/platform/drivers/rockchip-pcie/unbind # lspci So let's implement device remove(). Signed-off-by: Brian Norris <briannorris@chromium.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Shawn Lin <shawn.lin@rock-chips.com>
2017-03-10 10:46:15 +08:00
PCI: rockchip: Separate common code from RC driver In preparation for introducing EP driver for Rockchip PCIe controller, rename the RC driver from pcie-rockchip.c to pcie-rockchip-host.c, and only leave some common functions in pcie-rockchip.c in order to be reused for both of RC driver and EP driver. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com>
2018-05-09 09:11:49 +08:00
rockchip_pcie_write(rockchip,
(RC_REGION_0_ADDR_TRANS_L + RC_REGION_0_PASS_BITS),
PCIE_CORE_OB_REGION_ADDR0);
rockchip_pcie_write(rockchip, RC_REGION_0_ADDR_TRANS_H,
PCIE_CORE_OB_REGION_ADDR1);
ob_desc_0 = rockchip_pcie_read(rockchip, PCIE_CORE_OB_REGION_DESC0);
ob_desc_0 &= ~(RC_REGION_0_TYPE_MASK);
ob_desc_0 |= (type | (0x1 << 23));
rockchip_pcie_write(rockchip, ob_desc_0, PCIE_CORE_OB_REGION_DESC0);
rockchip_pcie_write(rockchip, 0x0, PCIE_CORE_OB_REGION_DESC1);
PCI: rockchip: Add remove() support Currently, if we try to unbind the platform device, the remove will succeed, but the removal won't undo most of the registration, leaving partially-configured PCI devices in the system. This allows, for example, a simple 'lspci' to crash the system, as it will try to touch the freed (via devm_*) driver structures, e.g., on RK3399: # echo f8000000.pcie > /sys/bus/platform/drivers/rockchip-pcie/unbind # lspci So let's implement device remove(). Signed-off-by: Brian Norris <briannorris@chromium.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Shawn Lin <shawn.lin@rock-chips.com>
2017-03-10 10:46:15 +08:00
}
PCI: rockchip: Separate common code from RC driver In preparation for introducing EP driver for Rockchip PCIe controller, rename the RC driver from pcie-rockchip.c to pcie-rockchip-host.c, and only leave some common functions in pcie-rockchip.c in order to be reused for both of RC driver and EP driver. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com>
2018-05-09 09:11:49 +08:00
EXPORT_SYMBOL_GPL(rockchip_pcie_cfg_configuration_accesses);