84 lines
1.7 KiB
Plaintext
84 lines
1.7 KiB
Plaintext
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Binding for a Clockgen hardware block found on
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certain STMicroelectronics consumer electronics SoC devices.
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A Clockgen node can contain pll, diviser or multiplexer nodes.
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We will find only the base address of the Clockgen, this base
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address is common of all subnode.
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clockgen_node {
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reg = <>;
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pll_node {
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...
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};
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prediv_node {
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...
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};
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divmux_node {
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...
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};
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quadfs_node {
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...
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};
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...
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};
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This binding uses the common clock binding[1].
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Each subnode should use the binding discribe in [2]..[4]
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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[2] Documentation/devicetree/bindings/clock/st,quadfs.txt
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[3] Documentation/devicetree/bindings/clock/st,quadfs.txt
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[4] Documentation/devicetree/bindings/clock/st,quadfs.txt
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Required properties:
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- reg : A Base address and length of the register set.
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Example:
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clockgenA@fee62000 {
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reg = <0xfee62000 0xb48>;
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CLK_S_A0_PLL: CLK_S_A0_PLL {
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#clock-cells = <1>;
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compatible = "st,clkgena-plls-c65";
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clocks = <&CLK_SYSIN>;
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clock-output-names = "CLK_S_A0_PLL0_HS",
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"CLK_S_A0_PLL0_LS",
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"CLK_S_A0_PLL1";
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};
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CLK_S_A0_OSC_PREDIV: CLK_S_A0_OSC_PREDIV {
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#clock-cells = <0>;
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compatible = "st,clkgena-prediv-c65",
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"st,clkgena-prediv";
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clocks = <&CLK_SYSIN>;
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clock-output-names = "CLK_S_A0_OSC_PREDIV";
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};
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CLK_S_A0_HS: CLK_S_A0_HS {
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#clock-cells = <1>;
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compatible = "st,clkgena-divmux-c65-hs",
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"st,clkgena-divmux";
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clocks = <&CLK_S_A0_OSC_PREDIV>,
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<&CLK_S_A0_PLL 0>, /* PLL0 HS */
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<&CLK_S_A0_PLL 2>; /* PLL1 */
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clock-output-names = "CLK_S_FDMA_0",
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"CLK_S_FDMA_1",
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""; /* CLK_S_JIT_SENSE */
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/* Fourth output unused */
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};
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};
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