26 lines
641 B
Plaintext
26 lines
641 B
Plaintext
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Devicetree bindings for Zynq Ultrascale MPSoC FPGA Manager.
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The ZynqMP SoC uses the PCAP (Processor configuration Port) to configure the
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Programmable Logic (PL). The configuration uses the firmware interface.
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Required properties:
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- compatible: should contain "xlnx,zynqmp-pcap-fpga"
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Example for full FPGA configuration:
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fpga-region0 {
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compatible = "fpga-region";
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fpga-mgr = <&zynqmp_pcap>;
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#address-cells = <0x1>;
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#size-cells = <0x1>;
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};
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firmware {
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zynqmp_firmware: zynqmp-firmware {
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compatible = "xlnx,zynqmp-firmware";
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method = "smc";
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zynqmp_pcap: pcap {
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compatible = "xlnx,zynqmp-pcap-fpga";
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};
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};
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};
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