2011-03-22 05:08:55 +08:00
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/*
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* OMAP Voltage Controller (VC) interface
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*
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* Copyright (C) 2011 Texas Instruments, Inc.
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <plat/cpu.h>
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#include "voltage.h"
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#include "vc.h"
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#include "prm-regbits-34xx.h"
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#include "prm-regbits-44xx.h"
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#include "prm44xx.h"
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/* Voltage scale and accessory APIs */
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int omap_vc_pre_scale(struct voltagedomain *voltdm,
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unsigned long target_volt,
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u8 *target_vsel, u8 *current_vsel)
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{
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2011-03-23 07:14:57 +08:00
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struct omap_vc_channel *vc = voltdm->vc;
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2011-03-22 05:08:55 +08:00
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struct omap_vdd_info *vdd = voltdm->vdd;
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struct omap_volt_data *volt_data;
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const struct omap_vp_common_data *vp_common;
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u32 vc_cmdval, vp_errgain_val;
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vp_common = vdd->vp_data->vp_common;
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/* Check if sufficient pmic info is available for this vdd */
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if (!vdd->pmic_info) {
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pr_err("%s: Insufficient pmic info to scale the vdd_%s\n",
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__func__, voltdm->name);
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return -EINVAL;
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}
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if (!vdd->pmic_info->uv_to_vsel) {
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pr_err("%s: PMIC function to convert voltage in uV to"
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"vsel not registered. Hence unable to scale voltage"
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"for vdd_%s\n", __func__, voltdm->name);
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return -ENODATA;
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}
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2011-03-29 01:40:15 +08:00
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if (!voltdm->read || !voltdm->write) {
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2011-03-22 05:08:55 +08:00
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pr_err("%s: No read/write API for accessing vdd_%s regs\n",
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__func__, voltdm->name);
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return -EINVAL;
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}
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/* Get volt_data corresponding to target_volt */
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volt_data = omap_voltage_get_voltdata(voltdm, target_volt);
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if (IS_ERR(volt_data))
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volt_data = NULL;
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*target_vsel = vdd->pmic_info->uv_to_vsel(target_volt);
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2011-03-29 01:40:15 +08:00
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*current_vsel = voltdm->read(vdd->vp_data->voltage);
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2011-03-22 05:08:55 +08:00
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/* Setting the ON voltage to the new target voltage */
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2011-03-29 01:40:15 +08:00
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vc_cmdval = voltdm->read(vc->cmdval_reg);
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2011-03-23 07:14:57 +08:00
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vc_cmdval &= ~vc->common->cmd_on_mask;
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vc_cmdval |= (*target_vsel << vc->common->cmd_on_shift);
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2011-03-29 01:40:15 +08:00
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voltdm->write(vc_cmdval, vc->cmdval_reg);
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2011-03-22 05:08:55 +08:00
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/* Setting vp errorgain based on the voltage */
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if (volt_data) {
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2011-03-29 01:40:15 +08:00
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vp_errgain_val = voltdm->read(vdd->vp_data->vpconfig);
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2011-03-22 05:08:55 +08:00
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vdd->vp_rt_data.vpconfig_errorgain = volt_data->vp_errgain;
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vp_errgain_val &= ~vp_common->vpconfig_errorgain_mask;
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vp_errgain_val |= vdd->vp_rt_data.vpconfig_errorgain <<
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vp_common->vpconfig_errorgain_shift;
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2011-03-29 01:40:15 +08:00
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voltdm->write(vp_errgain_val, vdd->vp_data->vpconfig);
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2011-03-22 05:08:55 +08:00
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}
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return 0;
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}
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void omap_vc_post_scale(struct voltagedomain *voltdm,
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unsigned long target_volt,
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u8 target_vsel, u8 current_vsel)
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{
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struct omap_vdd_info *vdd = voltdm->vdd;
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u32 smps_steps = 0, smps_delay = 0;
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smps_steps = abs(target_vsel - current_vsel);
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/* SMPS slew rate / step size. 2us added as buffer. */
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smps_delay = ((smps_steps * vdd->pmic_info->step_size) /
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vdd->pmic_info->slew_rate) + 2;
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udelay(smps_delay);
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vdd->curr_volt = target_volt;
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}
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2011-03-23 07:14:57 +08:00
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/* vc_bypass_scale - VC bypass method of voltage scaling */
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int omap_vc_bypass_scale(struct voltagedomain *voltdm,
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unsigned long target_volt)
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2011-03-22 05:08:55 +08:00
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{
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2011-03-23 07:14:57 +08:00
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struct omap_vc_channel *vc = voltdm->vc;
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2011-03-22 05:08:55 +08:00
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u32 loop_cnt = 0, retries_cnt = 0;
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u32 vc_valid, vc_bypass_val_reg, vc_bypass_value;
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u8 target_vsel, current_vsel;
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int ret;
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ret = omap_vc_pre_scale(voltdm, target_volt, &target_vsel, ¤t_vsel);
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if (ret)
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return ret;
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2011-03-23 07:14:57 +08:00
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vc_valid = vc->common->valid;
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vc_bypass_val_reg = vc->common->bypass_val_reg;
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vc_bypass_value = (target_vsel << vc->common->data_shift) |
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2011-03-30 05:24:47 +08:00
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(vc->volt_reg_addr << vc->common->regaddr_shift) |
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(vc->i2c_slave_addr << vc->common->slaveaddr_shift);
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2011-03-22 05:08:55 +08:00
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2011-03-29 01:40:15 +08:00
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voltdm->write(vc_bypass_value, vc_bypass_val_reg);
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voltdm->write(vc_bypass_value | vc_valid, vc_bypass_val_reg);
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2011-03-22 05:08:55 +08:00
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2011-03-29 01:40:15 +08:00
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vc_bypass_value = voltdm->read(vc_bypass_val_reg);
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2011-03-22 05:08:55 +08:00
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/*
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* Loop till the bypass command is acknowledged from the SMPS.
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* NOTE: This is legacy code. The loop count and retry count needs
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* to be revisited.
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*/
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while (!(vc_bypass_value & vc_valid)) {
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loop_cnt++;
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if (retries_cnt > 10) {
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pr_warning("%s: Retry count exceeded\n", __func__);
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return -ETIMEDOUT;
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}
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if (loop_cnt > 50) {
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retries_cnt++;
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loop_cnt = 0;
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udelay(10);
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}
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2011-03-29 01:40:15 +08:00
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vc_bypass_value = voltdm->read(vc_bypass_val_reg);
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2011-03-22 05:08:55 +08:00
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}
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omap_vc_post_scale(voltdm, target_volt, target_vsel, current_vsel);
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return 0;
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}
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static void __init omap3_vfsm_init(struct voltagedomain *voltdm)
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{
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/*
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* Voltage Manager FSM parameters init
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* XXX This data should be passed in from the board file
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*/
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2011-03-29 01:40:15 +08:00
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voltdm->write(OMAP3_CLKSETUP, OMAP3_PRM_CLKSETUP_OFFSET);
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voltdm->write(OMAP3_VOLTOFFSET, OMAP3_PRM_VOLTOFFSET_OFFSET);
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voltdm->write(OMAP3_VOLTSETUP2, OMAP3_PRM_VOLTSETUP2_OFFSET);
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2011-03-22 05:08:55 +08:00
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}
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static void __init omap3_vc_init_channel(struct voltagedomain *voltdm)
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{
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static bool is_initialized;
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if (is_initialized)
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return;
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/*
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* Generic VC parameters init
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* XXX This data should be abstracted out
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*/
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2011-03-29 01:40:15 +08:00
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voltdm->write(OMAP3430_CMD1_MASK | OMAP3430_RAV1_MASK,
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OMAP3_PRM_VC_CH_CONF_OFFSET);
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voltdm->write(OMAP3430_MCODE_SHIFT | OMAP3430_HSEN_MASK,
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OMAP3_PRM_VC_I2C_CFG_OFFSET);
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2011-03-22 05:08:55 +08:00
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omap3_vfsm_init(voltdm);
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is_initialized = true;
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}
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/* OMAP4 specific voltage init functions */
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static void __init omap4_vc_init_channel(struct voltagedomain *voltdm)
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{
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static bool is_initialized;
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u32 vc_val;
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if (is_initialized)
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return;
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/*
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* Generic VC parameters init
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* XXX This data should be abstracted out
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*/
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vc_val = (OMAP4430_RAV_VDD_MPU_L_MASK | OMAP4430_CMD_VDD_MPU_L_MASK |
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OMAP4430_RAV_VDD_IVA_L_MASK | OMAP4430_CMD_VDD_IVA_L_MASK |
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OMAP4430_RAV_VDD_CORE_L_MASK | OMAP4430_CMD_VDD_CORE_L_MASK);
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2011-03-29 01:40:15 +08:00
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voltdm->write(vc_val, OMAP4_PRM_VC_CFG_CHANNEL_OFFSET);
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2011-03-22 05:08:55 +08:00
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/* XXX These are magic numbers and do not belong! */
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vc_val = (0x60 << OMAP4430_SCLL_SHIFT | 0x26 << OMAP4430_SCLH_SHIFT);
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2011-03-29 01:40:15 +08:00
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voltdm->write(vc_val, OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET);
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2011-03-22 05:08:55 +08:00
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is_initialized = true;
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}
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void __init omap_vc_init_channel(struct voltagedomain *voltdm)
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{
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2011-03-23 07:14:57 +08:00
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struct omap_vc_channel *vc = voltdm->vc;
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2011-03-22 05:08:55 +08:00
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struct omap_vdd_info *vdd = voltdm->vdd;
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2011-03-30 06:14:38 +08:00
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u8 on_vsel, onlp_vsel, ret_vsel, off_vsel;
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u32 val;
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2011-03-22 05:08:55 +08:00
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if (!vdd->pmic_info || !vdd->pmic_info->uv_to_vsel) {
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pr_err("%s: PMIC info requried to configure vc for"
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"vdd_%s not populated.Hence cannot initialize vc\n",
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__func__, voltdm->name);
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return;
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}
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2011-03-29 01:40:15 +08:00
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if (!voltdm->read || !voltdm->write) {
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2011-03-22 05:08:55 +08:00
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pr_err("%s: No read/write API for accessing vdd_%s regs\n",
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__func__, voltdm->name);
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return;
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}
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2011-03-30 05:02:36 +08:00
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/* get PMIC/board specific settings */
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vc->i2c_slave_addr = vdd->pmic_info->i2c_slave_addr;
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2011-06-10 02:01:55 +08:00
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vc->volt_reg_addr = vdd->pmic_info->volt_reg_addr;
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vc->cmd_reg_addr = vdd->pmic_info->cmd_reg_addr;
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2011-03-30 05:36:04 +08:00
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vc->setup_time = vdd->pmic_info->volt_setup_time;
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2011-03-30 05:02:36 +08:00
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/* Configure the i2c slave address for this VC */
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voltdm->rmw(vc->smps_sa_mask,
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vc->i2c_slave_addr << __ffs(vc->smps_sa_mask),
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vc->common->smps_sa_reg);
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2011-03-22 05:08:55 +08:00
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2011-06-10 02:01:55 +08:00
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/*
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* Configure the PMIC register addresses.
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*/
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voltdm->rmw(vc->smps_volra_mask,
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vc->volt_reg_addr << __ffs(vc->smps_volra_mask),
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vc->common->smps_volra_reg);
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if (vc->cmd_reg_addr)
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voltdm->rmw(vc->smps_cmdra_mask,
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vc->cmd_reg_addr << __ffs(vc->smps_cmdra_mask),
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vc->common->smps_cmdra_reg);
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2011-03-22 05:08:55 +08:00
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2011-03-30 06:14:38 +08:00
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/* Set up the on, inactive, retention and off voltage */
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on_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->on_volt);
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onlp_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->onlp_volt);
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ret_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->ret_volt);
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off_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->off_volt);
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val = ((on_vsel << vc->common->cmd_on_shift) |
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(onlp_vsel << vc->common->cmd_onlp_shift) |
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(ret_vsel << vc->common->cmd_ret_shift) |
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(off_vsel << vc->common->cmd_off_shift));
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voltdm->write(val, vc->cmdval_reg);
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2011-03-22 05:08:55 +08:00
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/* Configure the setup times */
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2011-03-30 05:36:04 +08:00
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voltdm->rmw(voltdm->vfsm->voltsetup_mask,
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vc->setup_time << __ffs(voltdm->vfsm->voltsetup_mask),
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voltdm->vfsm->voltsetup_reg);
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2011-03-22 05:08:55 +08:00
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if (cpu_is_omap34xx())
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omap3_vc_init_channel(voltdm);
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else if (cpu_is_omap44xx())
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omap4_vc_init_channel(voltdm);
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}
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