linux_old1/arch/mips/mti-malta/malta-reset.c

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/*
* Carsten Langgaard, carstenl@mips.com
* Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
*
* ########################################################################
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
* ########################################################################
*
* Reset the MIPS boards.
*
*/
#include <linux/init.h>
#include <linux/pm.h>
#include <asm/io.h>
#include <asm/reboot.h>
#include <asm/mips-boards/generic.h>
static void mips_machine_restart(char *command)
{
[MIPS] Malta: Fix software reset on big endian I noticed that the commit f197465384bf7ef1af184c2ed1a4e268911a91e3 (MIPS Tech: Get rid of volatile in core code) broke the software reset functionality for MIPS Malta boards in big-endian mode. According to the MIPS Malta board user's manual, writing the magic 32-bit GORESET value into the SOFTRES register initiates board soft reset. My experimentation has shown that the endianness of the GORESET integer should thereby be the same as the endianness, which has been set for the CPU itself. The writew() function used to write the magic value in the code introduced by the commit mentioned above, however, swaps bytes for big-endian kernels and transfers 16 bits instead of 32. The patch below replaces the writew() function by the __raw_writel() routine, which leaves the byte order intact and transfers the whole MIPS machine word. Trivial code cleanup (replacing spaces by a tab and cutting oversized lines to make checkpatch.pl happy) is also included. The patch was tested using a Malta evaluation board running in both BE and LE modes. For both modes, software reset was fully functional after the change. P.S. I suspect that the same commit broke the "standby" functionality for MIPS Atlas boards. However, I did not touch the Atlas code as I don't have such board at my disposal and also because the linux-mips.org Web site claims that Atlas support is scheduled for removal. Signed-off-by: Dmitri Vorobiev <dmitri.vorobiev@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-01-08 11:44:00 +08:00
unsigned int __iomem *softres_reg =
ioremap(SOFTRES_REG, sizeof(unsigned int));
[MIPS] Malta: Fix software reset on big endian I noticed that the commit f197465384bf7ef1af184c2ed1a4e268911a91e3 (MIPS Tech: Get rid of volatile in core code) broke the software reset functionality for MIPS Malta boards in big-endian mode. According to the MIPS Malta board user's manual, writing the magic 32-bit GORESET value into the SOFTRES register initiates board soft reset. My experimentation has shown that the endianness of the GORESET integer should thereby be the same as the endianness, which has been set for the CPU itself. The writew() function used to write the magic value in the code introduced by the commit mentioned above, however, swaps bytes for big-endian kernels and transfers 16 bits instead of 32. The patch below replaces the writew() function by the __raw_writel() routine, which leaves the byte order intact and transfers the whole MIPS machine word. Trivial code cleanup (replacing spaces by a tab and cutting oversized lines to make checkpatch.pl happy) is also included. The patch was tested using a Malta evaluation board running in both BE and LE modes. For both modes, software reset was fully functional after the change. P.S. I suspect that the same commit broke the "standby" functionality for MIPS Atlas boards. However, I did not touch the Atlas code as I don't have such board at my disposal and also because the linux-mips.org Web site claims that Atlas support is scheduled for removal. Signed-off-by: Dmitri Vorobiev <dmitri.vorobiev@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-01-08 11:44:00 +08:00
__raw_writel(GORESET, softres_reg);
}
static void mips_machine_halt(void)
{
[MIPS] Malta: Fix software reset on big endian I noticed that the commit f197465384bf7ef1af184c2ed1a4e268911a91e3 (MIPS Tech: Get rid of volatile in core code) broke the software reset functionality for MIPS Malta boards in big-endian mode. According to the MIPS Malta board user's manual, writing the magic 32-bit GORESET value into the SOFTRES register initiates board soft reset. My experimentation has shown that the endianness of the GORESET integer should thereby be the same as the endianness, which has been set for the CPU itself. The writew() function used to write the magic value in the code introduced by the commit mentioned above, however, swaps bytes for big-endian kernels and transfers 16 bits instead of 32. The patch below replaces the writew() function by the __raw_writel() routine, which leaves the byte order intact and transfers the whole MIPS machine word. Trivial code cleanup (replacing spaces by a tab and cutting oversized lines to make checkpatch.pl happy) is also included. The patch was tested using a Malta evaluation board running in both BE and LE modes. For both modes, software reset was fully functional after the change. P.S. I suspect that the same commit broke the "standby" functionality for MIPS Atlas boards. However, I did not touch the Atlas code as I don't have such board at my disposal and also because the linux-mips.org Web site claims that Atlas support is scheduled for removal. Signed-off-by: Dmitri Vorobiev <dmitri.vorobiev@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-01-08 11:44:00 +08:00
unsigned int __iomem *softres_reg =
ioremap(SOFTRES_REG, sizeof(unsigned int));
[MIPS] Malta: Fix software reset on big endian I noticed that the commit f197465384bf7ef1af184c2ed1a4e268911a91e3 (MIPS Tech: Get rid of volatile in core code) broke the software reset functionality for MIPS Malta boards in big-endian mode. According to the MIPS Malta board user's manual, writing the magic 32-bit GORESET value into the SOFTRES register initiates board soft reset. My experimentation has shown that the endianness of the GORESET integer should thereby be the same as the endianness, which has been set for the CPU itself. The writew() function used to write the magic value in the code introduced by the commit mentioned above, however, swaps bytes for big-endian kernels and transfers 16 bits instead of 32. The patch below replaces the writew() function by the __raw_writel() routine, which leaves the byte order intact and transfers the whole MIPS machine word. Trivial code cleanup (replacing spaces by a tab and cutting oversized lines to make checkpatch.pl happy) is also included. The patch was tested using a Malta evaluation board running in both BE and LE modes. For both modes, software reset was fully functional after the change. P.S. I suspect that the same commit broke the "standby" functionality for MIPS Atlas boards. However, I did not touch the Atlas code as I don't have such board at my disposal and also because the linux-mips.org Web site claims that Atlas support is scheduled for removal. Signed-off-by: Dmitri Vorobiev <dmitri.vorobiev@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-01-08 11:44:00 +08:00
__raw_writel(GORESET, softres_reg);
}
static int __init mips_reboot_setup(void)
{
_machine_restart = mips_machine_restart;
_machine_halt = mips_machine_halt;
pm_power_off = mips_machine_halt;
return 0;
}
arch_initcall(mips_reboot_setup);