2012-12-29 08:29:10 +08:00
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/*
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2012-01-07 19:18:35 +08:00
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* Copyright (c) 2010 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* EXYNOS - CPUFreq support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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enum cpufreq_level_index {
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L0, L1, L2, L3, L4,
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L5, L6, L7, L8, L9,
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L10, L11, L12, L13, L14,
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L15, L16, L17, L18, L19,
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L20,
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};
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2014-05-17 07:19:30 +08:00
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enum exynos_soc_type {
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EXYNOS_SOC_4212,
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EXYNOS_SOC_4412,
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EXYNOS_SOC_5250,
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};
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2012-12-24 07:57:42 +08:00
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#define APLL_FREQ(f, a0, a1, a2, a3, a4, a5, a6, a7, b0, b1, b2, m, p, s) \
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{ \
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.freq = (f) * 1000, \
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.clk_div_cpu0 = ((a0) | (a1) << 4 | (a2) << 8 | (a3) << 12 | \
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(a4) << 16 | (a5) << 20 | (a6) << 24 | (a7) << 28), \
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.clk_div_cpu1 = (b0 << 0 | b1 << 4 | b2 << 8), \
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.mps = ((m) << 16 | (p) << 8 | (s)), \
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}
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struct apll_freq {
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unsigned int freq;
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u32 clk_div_cpu0;
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u32 clk_div_cpu1;
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u32 mps;
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};
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2012-01-07 19:18:35 +08:00
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struct exynos_dvfs_info {
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2014-05-17 07:19:30 +08:00
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enum exynos_soc_type type;
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2014-04-18 10:20:33 +08:00
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struct device *dev;
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2012-01-07 19:18:35 +08:00
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unsigned long mpll_freq_khz;
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unsigned int pll_safe_idx;
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struct clk *cpu_clk;
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unsigned int *volt_table;
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struct cpufreq_frequency_table *freq_table;
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void (*set_freq)(unsigned int, unsigned int);
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bool (*need_apll_change)(unsigned int, unsigned int);
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2014-05-26 05:26:03 +08:00
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void __iomem *cmu_regs;
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2012-01-07 19:18:35 +08:00
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};
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2013-08-09 20:04:55 +08:00
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#ifdef CONFIG_ARM_EXYNOS4X12_CPUFREQ
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2012-03-10 18:59:22 +08:00
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extern int exynos4x12_cpufreq_init(struct exynos_dvfs_info *);
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2013-08-09 20:04:55 +08:00
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#else
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static inline int exynos4x12_cpufreq_init(struct exynos_dvfs_info *info)
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{
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return -EOPNOTSUPP;
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}
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#endif
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#ifdef CONFIG_ARM_EXYNOS5250_CPUFREQ
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2012-03-10 19:00:02 +08:00
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extern int exynos5250_cpufreq_init(struct exynos_dvfs_info *);
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2013-08-09 20:04:55 +08:00
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#else
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static inline int exynos5250_cpufreq_init(struct exynos_dvfs_info *info)
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{
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return -EOPNOTSUPP;
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}
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#endif
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2013-12-19 03:21:34 +08:00
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2014-05-26 05:26:03 +08:00
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#define EXYNOS4_CLKSRC_CPU 0x14200
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#define EXYNOS4_CLKMUX_STATCPU 0x14400
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2013-12-19 03:21:34 +08:00
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2014-05-26 05:26:03 +08:00
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#define EXYNOS4_CLKDIV_CPU 0x14500
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#define EXYNOS4_CLKDIV_CPU1 0x14504
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#define EXYNOS4_CLKDIV_STATCPU 0x14600
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#define EXYNOS4_CLKDIV_STATCPU1 0x14604
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2013-12-19 03:21:34 +08:00
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#define EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT (16)
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#define EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT)
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2014-05-26 05:26:03 +08:00
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#define EXYNOS5_APLL_LOCK 0x00000
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#define EXYNOS5_APLL_CON0 0x00100
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#define EXYNOS5_CLKMUX_STATCPU 0x00400
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#define EXYNOS5_CLKDIV_CPU0 0x00500
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#define EXYNOS5_CLKDIV_CPU1 0x00504
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#define EXYNOS5_CLKDIV_STATCPU0 0x00600
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#define EXYNOS5_CLKDIV_STATCPU1 0x00604
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