License cleanup: add SPDX GPL-2.0 license identifier to files with no license
Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.
By default all files without license information are under the default
license of the kernel, which is GPL version 2.
Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier. The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.
This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.
How this work was done:
Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
- file had no licensing information it it.
- file was a */uapi/* one with no licensing information in it,
- file was a */uapi/* one with existing licensing information,
Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.
The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne. Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.
The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed. Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.
Criteria used to select files for SPDX license identifier tagging was:
- Files considered eligible had to be source code files.
- Make and config files were included as candidates if they contained >5
lines of source
- File already had some variant of a license header in it (even if <5
lines).
All documentation files were explicitly excluded.
The following heuristics were used to determine which SPDX license
identifiers to apply.
- when both scanners couldn't find any license traces, file was
considered to have no license information in it, and the top level
COPYING file license applied.
For non */uapi/* files that summary was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 11139
and resulted in the first patch in this series.
If that file was a */uapi/* path one, it was "GPL-2.0 WITH
Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 WITH Linux-syscall-note 930
and resulted in the second patch in this series.
- if a file had some form of licensing information in it, and was one
of the */uapi/* ones, it was denoted with the Linux-syscall-note if
any GPL family license was found in the file or had no licensing in
it (per prior point). Results summary:
SPDX license identifier # files
---------------------------------------------------|------
GPL-2.0 WITH Linux-syscall-note 270
GPL-2.0+ WITH Linux-syscall-note 169
((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21
((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17
LGPL-2.1+ WITH Linux-syscall-note 15
GPL-1.0+ WITH Linux-syscall-note 14
((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5
LGPL-2.0+ WITH Linux-syscall-note 4
LGPL-2.1 WITH Linux-syscall-note 3
((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3
((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1
and that resulted in the third patch in this series.
- when the two scanners agreed on the detected license(s), that became
the concluded license(s).
- when there was disagreement between the two scanners (one detected a
license but the other didn't, or they both detected different
licenses) a manual inspection of the file occurred.
- In most cases a manual inspection of the information in the file
resulted in a clear resolution of the license that should apply (and
which scanner probably needed to revisit its heuristics).
- When it was not immediately clear, the license identifier was
confirmed with lawyers working with the Linux Foundation.
- If there was any question as to the appropriate license identifier,
the file was flagged for further research and to be revisited later
in time.
In total, over 70 hours of logged manual review was done on the
spreadsheet to determine the SPDX license identifiers to apply to the
source files by Kate, Philippe, Thomas and, in some cases, confirmation
by lawyers working with the Linux Foundation.
Kate also obtained a third independent scan of the 4.13 code base from
FOSSology, and compared selected files where the other two scanners
disagreed against that SPDX file, to see if there was new insights. The
Windriver scanner is based on an older version of FOSSology in part, so
they are related.
Thomas did random spot checks in about 500 files from the spreadsheets
for the uapi headers and agreed with SPDX license identifier in the
files he inspected. For the non-uapi files Thomas did random spot checks
in about 15000 files.
In initial set of patches against 4.14-rc6, 3 files were found to have
copy/paste license identifier errors, and have been fixed to reflect the
correct identifier.
Additionally Philippe spent 10 hours this week doing a detailed manual
inspection and review of the 12,461 patched files from the initial patch
version early this week with:
- a full scancode scan run, collecting the matched texts, detected
license ids and scores
- reviewing anything where there was a license detected (about 500+
files) to ensure that the applied SPDX license was correct
- reviewing anything where there was no detection but the patch license
was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied
SPDX license was correct
This produced a worksheet with 20 files needing minor correction. This
worksheet was then exported into 3 different .csv files for the
different types of files to be modified.
These .csv files were then reviewed by Greg. Thomas wrote a script to
parse the csv files and add the proper SPDX tag to the file, in the
format that the file expected. This script was further refined by Greg
based on the output to detect more types of files automatically and to
distinguish between header and source .c files (which need different
comment types.) Finally Greg ran the script using the .csv files to
generate the patches.
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-01 22:07:57 +08:00
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// SPDX-License-Identifier: GPL-2.0
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2005-04-17 06:20:36 +08:00
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#include <linux/pci.h>
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#include <linux/acpi.h>
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#include <linux/init.h>
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2005-10-01 00:34:42 +08:00
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#include <linux/irq.h>
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2007-10-04 06:56:14 +08:00
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#include <linux/dmi.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 16:04:11 +08:00
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#include <linux/slab.h>
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2015-10-14 14:29:41 +08:00
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#include <linux/pci-acpi.h>
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2005-09-13 00:49:24 +08:00
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#include <asm/numa.h>
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2008-12-27 21:02:28 +08:00
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#include <asm/pci_x86.h>
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2005-04-17 06:20:36 +08:00
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2007-10-04 06:56:51 +08:00
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struct pci_root_info {
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2015-10-14 14:29:41 +08:00
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struct acpi_pci_root_info common;
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2012-04-03 09:31:53 +08:00
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struct pci_sysdata sd;
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2012-06-22 14:55:17 +08:00
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#ifdef CONFIG_PCI_MMCONFIG
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bool mcfg_added;
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u8 start_bus;
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u8 end_bus;
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#endif
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2007-10-04 06:56:51 +08:00
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};
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2010-02-24 01:24:41 +08:00
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static bool pci_use_crs = true;
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2012-10-30 07:26:54 +08:00
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static bool pci_ignore_seg = false;
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2010-02-24 01:24:41 +08:00
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static int __init set_use_crs(const struct dmi_system_id *id)
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{
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pci_use_crs = true;
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return 0;
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}
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2011-12-31 03:37:05 +08:00
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static int __init set_nouse_crs(const struct dmi_system_id *id)
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{
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pci_use_crs = false;
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return 0;
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}
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2012-10-30 07:26:54 +08:00
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static int __init set_ignore_seg(const struct dmi_system_id *id)
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{
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printk(KERN_INFO "PCI: %s detected: ignoring ACPI _SEG\n", id->ident);
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pci_ignore_seg = true;
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return 0;
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}
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static const struct dmi_system_id pci_crs_quirks[] __initconst = {
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2010-02-24 01:24:41 +08:00
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/* http://bugzilla.kernel.org/show_bug.cgi?id=14183 */
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{
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.callback = set_use_crs,
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.ident = "IBM System x3800",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
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DMI_MATCH(DMI_PRODUCT_NAME, "x3800"),
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},
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},
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x86/PCI: use host bridge _CRS info on ASRock ALiveSATA2-GLAN
This DMI quirk turns on "pci=use_crs" for the ALiveSATA2-GLAN because
amd_bus.c doesn't handle this system correctly.
The system has a single HyperTransport I/O chain, but has two PCI host
bridges to buses 00 and 80. amd_bus.c learns the MMIO range associated
with buses 00-ff and that this range is routed to the HT chain hosted at
node 0, link 0:
bus: [00, ff] on node 0 link 0
bus: 00 index 1 [mem 0x80000000-0xfcffffffff]
This includes the address space for both bus 00 and bus 80, and amd_bus.c
assumes it's all routed to bus 00.
We find device 80:01.0, which BIOS left in the middle of that space, but
we don't find a bridge from bus 00 to bus 80, so we conclude that 80:01.0
is unreachable from bus 00, and we move it from the original, working,
address to something outside the bus 00 aperture, which does not work:
pci 0000:80:01.0: reg 10: [mem 0xfebfc000-0xfebfffff 64bit]
pci 0000:80:01.0: BAR 0: assigned [mem 0xfd00000000-0xfd00003fff 64bit]
The BIOS told us everything we need to know to handle this correctly,
so we're better off if we just pay attention, which lets us leave the
80:01.0 device at the original, working, address:
ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-7f])
pci_root PNP0A03:00: host bridge window [mem 0x80000000-0xff37ffff]
ACPI: PCI Root Bridge [PCI1] (domain 0000 [bus 80-ff])
pci_root PNP0A08:00: host bridge window [mem 0xfebfc000-0xfebfffff]
This was a regression between 2.6.33 and 2.6.34. In 2.6.33, amd_bus.c
was used only when we found multiple HT chains. 3e3da00c01d050, which
enabled amd_bus.c even on systems with a single HT chain, caused this
failure.
This quirk was written by Graham. If we ever enable "pci=use_crs" for
machines from 2006 or earlir, this quirk should be removed.
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=16007
Cc: stable@kernel.org
Reported-by: Graham Ramsey <ramsey.graham@ntlworld.com>
Signed-off-by: Bjorn Helgaas <bjorn.helgaas@hp.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2010-07-24 02:53:27 +08:00
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/* https://bugzilla.kernel.org/show_bug.cgi?id=16007 */
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/* 2006 AMD HT/VIA system with two host bridges */
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{
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.callback = set_use_crs,
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.ident = "ASRock ALiveSATA2-GLAN",
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.matches = {
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DMI_MATCH(DMI_PRODUCT_NAME, "ALiveSATA2-GLAN"),
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},
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},
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2011-08-31 23:07:10 +08:00
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/* https://bugzilla.kernel.org/show_bug.cgi?id=30552 */
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/* 2006 AMD HT/VIA system with two host bridges */
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{
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.callback = set_use_crs,
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.ident = "ASUS M2V-MX SE",
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.matches = {
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DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
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DMI_MATCH(DMI_BOARD_NAME, "M2V-MX SE"),
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DMI_MATCH(DMI_BIOS_VENDOR, "American Megatrends Inc."),
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},
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},
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2012-02-29 02:51:10 +08:00
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/* https://bugzilla.kernel.org/show_bug.cgi?id=42619 */
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{
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.callback = set_use_crs,
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.ident = "MSI MS-7253",
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.matches = {
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DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"),
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DMI_MATCH(DMI_BOARD_NAME, "MS-7253"),
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DMI_MATCH(DMI_BIOS_VENDOR, "Phoenix Technologies, LTD"),
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},
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},
|
2015-06-10 07:54:07 +08:00
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/* https://bugs.launchpad.net/ubuntu/+source/alsa-driver/+bug/931368 */
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/* https://bugs.launchpad.net/ubuntu/+source/alsa-driver/+bug/1033299 */
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{
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.callback = set_use_crs,
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.ident = "Foxconn K8M890-8237A",
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.matches = {
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DMI_MATCH(DMI_BOARD_VENDOR, "Foxconn"),
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DMI_MATCH(DMI_BOARD_NAME, "K8M890-8237A"),
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DMI_MATCH(DMI_BIOS_VENDOR, "Phoenix Technologies, LTD"),
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},
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},
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2011-12-31 03:37:05 +08:00
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2012-01-05 00:33:12 +08:00
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/* Now for the blacklist.. */
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/* https://bugzilla.redhat.com/show_bug.cgi?id=769657 */
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{
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.callback = set_nouse_crs,
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.ident = "Dell Studio 1557",
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.matches = {
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DMI_MATCH(DMI_BOARD_VENDOR, "Dell Inc."),
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DMI_MATCH(DMI_PRODUCT_NAME, "Studio 1557"),
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DMI_MATCH(DMI_BIOS_VERSION, "A09"),
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},
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},
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2012-01-05 00:30:52 +08:00
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/* https://bugzilla.redhat.com/show_bug.cgi?id=769657 */
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{
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.callback = set_nouse_crs,
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.ident = "Thinkpad SL510",
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.matches = {
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DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
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DMI_MATCH(DMI_BOARD_NAME, "2847DFG"),
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DMI_MATCH(DMI_BIOS_VERSION, "6JET85WW (1.43 )"),
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},
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},
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2016-12-29 04:55:16 +08:00
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/* https://bugzilla.kernel.org/show_bug.cgi?id=42606 */
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{
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.callback = set_nouse_crs,
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.ident = "Supermicro X8DTH",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"),
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DMI_MATCH(DMI_PRODUCT_NAME, "X8DTH-i/6/iF/6F"),
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DMI_MATCH(DMI_BIOS_VERSION, "2.0a"),
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},
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},
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2012-10-30 07:26:54 +08:00
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/* https://bugzilla.kernel.org/show_bug.cgi?id=15362 */
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{
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.callback = set_ignore_seg,
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.ident = "HP xw9300",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
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DMI_MATCH(DMI_PRODUCT_NAME, "HP xw9300 Workstation"),
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},
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},
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2010-02-24 01:24:41 +08:00
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{}
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};
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void __init pci_acpi_crs_quirks(void)
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{
|
2018-03-21 02:08:00 +08:00
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int year = dmi_get_bios_year();
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if (year >= 0 && year < 2008 && iomem_resource.end <= 0xffffffff)
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2018-02-22 20:59:21 +08:00
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pci_use_crs = false;
|
2010-02-24 01:24:41 +08:00
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2012-10-30 07:26:54 +08:00
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dmi_check_system(pci_crs_quirks);
|
2010-02-24 01:24:41 +08:00
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/*
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* If the user specifies "pci=use_crs" or "pci=nocrs" explicitly, that
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* takes precedence over anything we figured out above.
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*/
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if (pci_probe & PCI_ROOT_NO_CRS)
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pci_use_crs = false;
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else if (pci_probe & PCI_USE__CRS)
|
|
|
|
|
pci_use_crs = true;
|
|
|
|
|
|
|
|
|
|
printk(KERN_INFO "PCI: %s host bridge windows from ACPI; "
|
|
|
|
|
"if necessary, use \"pci=%s\" and report a bug\n",
|
|
|
|
|
pci_use_crs ? "Using" : "Ignoring",
|
|
|
|
|
pci_use_crs ? "nocrs" : "use_crs");
|
|
|
|
|
}
|
|
|
|
|
|
2012-06-22 14:55:17 +08:00
|
|
|
#ifdef CONFIG_PCI_MMCONFIG
|
2012-12-22 06:02:53 +08:00
|
|
|
static int check_segment(u16 seg, struct device *dev, char *estr)
|
2012-06-22 14:55:17 +08:00
|
|
|
{
|
|
|
|
|
if (seg) {
|
|
|
|
|
dev_err(dev,
|
|
|
|
|
"%s can't access PCI configuration "
|
|
|
|
|
"space under this host bridge.\n",
|
|
|
|
|
estr);
|
|
|
|
|
return -EIO;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Failure in adding MMCFG information is not fatal,
|
|
|
|
|
* just can't access extended configuration space of
|
|
|
|
|
* devices under this host bridge.
|
|
|
|
|
*/
|
|
|
|
|
dev_warn(dev,
|
|
|
|
|
"%s can't access extended PCI configuration "
|
|
|
|
|
"space under this bridge.\n",
|
|
|
|
|
estr);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2015-10-14 14:29:41 +08:00
|
|
|
static int setup_mcfg_map(struct acpi_pci_root_info *ci)
|
2012-06-22 14:55:17 +08:00
|
|
|
{
|
2015-10-14 14:29:41 +08:00
|
|
|
int result, seg;
|
|
|
|
|
struct pci_root_info *info;
|
|
|
|
|
struct acpi_pci_root *root = ci->root;
|
|
|
|
|
struct device *dev = &ci->bridge->dev;
|
2012-06-22 14:55:17 +08:00
|
|
|
|
2015-10-14 14:29:41 +08:00
|
|
|
info = container_of(ci, struct pci_root_info, common);
|
|
|
|
|
info->start_bus = (u8)root->secondary.start;
|
|
|
|
|
info->end_bus = (u8)root->secondary.end;
|
2012-06-22 14:55:17 +08:00
|
|
|
info->mcfg_added = false;
|
2015-10-14 14:29:41 +08:00
|
|
|
seg = info->sd.domain;
|
2012-06-22 14:55:17 +08:00
|
|
|
|
|
|
|
|
/* return success if MMCFG is not in use */
|
|
|
|
|
if (raw_pci_ext_ops && raw_pci_ext_ops != &pci_mmcfg)
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
if (!(pci_probe & PCI_PROBE_MMCONF))
|
|
|
|
|
return check_segment(seg, dev, "MMCONFIG is disabled,");
|
|
|
|
|
|
2015-10-14 14:29:41 +08:00
|
|
|
result = pci_mmconfig_insert(dev, seg, info->start_bus, info->end_bus,
|
|
|
|
|
root->mcfg_addr);
|
2012-06-22 14:55:17 +08:00
|
|
|
if (result == 0) {
|
|
|
|
|
/* enable MMCFG if it hasn't been enabled yet */
|
|
|
|
|
if (raw_pci_ext_ops == NULL)
|
|
|
|
|
raw_pci_ext_ops = &pci_mmcfg;
|
|
|
|
|
info->mcfg_added = true;
|
|
|
|
|
} else if (result != -EEXIST)
|
|
|
|
|
return check_segment(seg, dev,
|
|
|
|
|
"fail to add MMCONFIG information,");
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2015-10-14 14:29:41 +08:00
|
|
|
static void teardown_mcfg_map(struct acpi_pci_root_info *ci)
|
2012-06-22 14:55:17 +08:00
|
|
|
{
|
2015-10-14 14:29:41 +08:00
|
|
|
struct pci_root_info *info;
|
|
|
|
|
|
|
|
|
|
info = container_of(ci, struct pci_root_info, common);
|
2012-06-22 14:55:17 +08:00
|
|
|
if (info->mcfg_added) {
|
2015-10-14 14:29:41 +08:00
|
|
|
pci_mmconfig_delete(info->sd.domain,
|
|
|
|
|
info->start_bus, info->end_bus);
|
2012-06-22 14:55:17 +08:00
|
|
|
info->mcfg_added = false;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
#else
|
2015-10-14 14:29:41 +08:00
|
|
|
static int setup_mcfg_map(struct acpi_pci_root_info *ci)
|
2012-06-22 14:55:17 +08:00
|
|
|
{
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
2015-10-14 14:29:41 +08:00
|
|
|
|
|
|
|
|
static void teardown_mcfg_map(struct acpi_pci_root_info *ci)
|
2012-06-22 14:55:17 +08:00
|
|
|
{
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
|
2015-10-14 14:29:41 +08:00
|
|
|
static int pci_acpi_root_get_node(struct acpi_pci_root *root)
|
2007-10-04 06:56:51 +08:00
|
|
|
{
|
2015-10-14 14:29:41 +08:00
|
|
|
int busnum = root->secondary.start;
|
|
|
|
|
struct acpi_device *device = root->device;
|
|
|
|
|
int node = acpi_get_node(device->handle);
|
2015-02-05 13:44:46 +08:00
|
|
|
|
2015-10-14 14:29:41 +08:00
|
|
|
if (node == NUMA_NO_NODE) {
|
|
|
|
|
node = x86_pci_root_bus_node(busnum);
|
|
|
|
|
if (node != 0 && node != NUMA_NO_NODE)
|
|
|
|
|
dev_info(&device->dev, FW_BUG "no _PXM; falling back to node %d from hardware (may be inconsistent with ACPI node numbers)\n",
|
|
|
|
|
node);
|
2010-09-23 01:09:19 +08:00
|
|
|
}
|
2015-10-14 14:29:41 +08:00
|
|
|
if (node != NUMA_NO_NODE && !node_online(node))
|
|
|
|
|
node = NUMA_NO_NODE;
|
|
|
|
|
|
|
|
|
|
return node;
|
2010-09-23 01:09:19 +08:00
|
|
|
}
|
|
|
|
|
|
2015-10-14 14:29:41 +08:00
|
|
|
static int pci_acpi_root_init_info(struct acpi_pci_root_info *ci)
|
2010-09-23 01:09:19 +08:00
|
|
|
{
|
2015-10-14 14:29:41 +08:00
|
|
|
return setup_mcfg_map(ci);
|
2012-04-03 09:31:53 +08:00
|
|
|
}
|
|
|
|
|
|
2015-10-14 14:29:41 +08:00
|
|
|
static void pci_acpi_root_release_info(struct acpi_pci_root_info *ci)
|
2012-04-03 09:31:53 +08:00
|
|
|
{
|
2015-10-14 14:29:41 +08:00
|
|
|
teardown_mcfg_map(ci);
|
|
|
|
|
kfree(container_of(ci, struct pci_root_info, common));
|
2012-04-03 09:31:53 +08:00
|
|
|
}
|
2012-06-22 14:55:17 +08:00
|
|
|
|
2015-04-30 12:41:28 +08:00
|
|
|
/*
|
|
|
|
|
* An IO port or MMIO resource assigned to a PCI host bridge may be
|
|
|
|
|
* consumed by the host bridge itself or available to its child
|
|
|
|
|
* bus/devices. The ACPI specification defines a bit (Producer/Consumer)
|
|
|
|
|
* to tell whether the resource is consumed by the host bridge itself,
|
|
|
|
|
* but firmware hasn't used that bit consistently, so we can't rely on it.
|
|
|
|
|
*
|
|
|
|
|
* On x86 and IA64 platforms, all IO port and MMIO resources are assumed
|
|
|
|
|
* to be available to child bus/devices except one special case:
|
|
|
|
|
* IO port [0xCF8-0xCFF] is consumed by the host bridge itself
|
|
|
|
|
* to access PCI configuration space.
|
|
|
|
|
*
|
|
|
|
|
* So explicitly filter out PCI CFG IO ports[0xCF8-0xCFF].
|
|
|
|
|
*/
|
|
|
|
|
static bool resource_is_pcicfg_ioport(struct resource *res)
|
|
|
|
|
{
|
|
|
|
|
return (res->flags & IORESOURCE_IO) &&
|
|
|
|
|
res->start == 0xCF8 && res->end == 0xCFF;
|
|
|
|
|
}
|
|
|
|
|
|
2015-10-14 14:29:41 +08:00
|
|
|
static int pci_acpi_root_prepare_resources(struct acpi_pci_root_info *ci)
|
2007-10-04 06:56:51 +08:00
|
|
|
{
|
2015-10-14 14:29:41 +08:00
|
|
|
struct acpi_device *device = ci->bridge;
|
|
|
|
|
int busnum = ci->root->secondary.start;
|
2015-03-04 16:47:11 +08:00
|
|
|
struct resource_entry *entry, *tmp;
|
2015-10-14 14:29:41 +08:00
|
|
|
int status;
|
2007-10-04 06:56:51 +08:00
|
|
|
|
2015-10-14 14:29:41 +08:00
|
|
|
status = acpi_pci_probe_root_resources(ci);
|
|
|
|
|
if (pci_use_crs) {
|
|
|
|
|
resource_list_for_each_entry_safe(entry, tmp, &ci->resources)
|
|
|
|
|
if (resource_is_pcicfg_ioport(entry->res))
|
2015-03-04 16:47:11 +08:00
|
|
|
resource_list_destroy_entry(entry);
|
2015-10-14 14:29:41 +08:00
|
|
|
return status;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
resource_list_for_each_entry_safe(entry, tmp, &ci->resources) {
|
|
|
|
|
dev_printk(KERN_DEBUG, &device->dev,
|
|
|
|
|
"host bridge window %pR (ignored)\n", entry->res);
|
|
|
|
|
resource_list_destroy_entry(entry);
|
|
|
|
|
}
|
|
|
|
|
x86_pci_root_bus_resources(busnum, &ci->resources);
|
|
|
|
|
|
|
|
|
|
return 0;
|
2007-10-04 06:56:51 +08:00
|
|
|
}
|
|
|
|
|
|
2015-10-14 14:29:41 +08:00
|
|
|
static struct acpi_pci_root_ops acpi_pci_root_ops = {
|
|
|
|
|
.pci_ops = &pci_root_ops,
|
|
|
|
|
.init_info = pci_acpi_root_init_info,
|
|
|
|
|
.release_info = pci_acpi_root_release_info,
|
|
|
|
|
.prepare_resources = pci_acpi_root_prepare_resources,
|
|
|
|
|
};
|
|
|
|
|
|
2012-12-22 06:02:53 +08:00
|
|
|
struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root)
|
2005-04-17 06:20:36 +08:00
|
|
|
{
|
2010-03-12 03:20:11 +08:00
|
|
|
int domain = root->segment;
|
|
|
|
|
int busnum = root->secondary.start;
|
2015-10-14 14:29:41 +08:00
|
|
|
int node = pci_acpi_root_get_node(root);
|
2014-01-25 01:41:11 +08:00
|
|
|
struct pci_bus *bus;
|
2007-07-22 05:23:39 +08:00
|
|
|
|
2012-10-30 07:26:54 +08:00
|
|
|
if (pci_ignore_seg)
|
2015-10-14 14:29:40 +08:00
|
|
|
root->segment = domain = 0;
|
2012-10-30 07:26:54 +08:00
|
|
|
|
2007-10-12 04:58:30 +08:00
|
|
|
if (domain && !pci_domains_supported) {
|
2009-11-05 01:32:47 +08:00
|
|
|
printk(KERN_WARNING "pci_bus %04x:%02x: "
|
|
|
|
|
"ignored (multiple domains not supported)\n",
|
|
|
|
|
domain, busnum);
|
2007-10-12 04:58:30 +08:00
|
|
|
return NULL;
|
|
|
|
|
}
|
|
|
|
|
|
2008-04-16 05:34:49 +08:00
|
|
|
bus = pci_find_bus(domain, busnum);
|
|
|
|
|
if (bus) {
|
|
|
|
|
/*
|
2014-01-25 01:38:40 +08:00
|
|
|
* If the desired bus has been scanned already, replace
|
|
|
|
|
* its bus->sysdata.
|
2008-04-16 05:34:49 +08:00
|
|
|
*/
|
2015-10-14 14:29:41 +08:00
|
|
|
struct pci_sysdata sd = {
|
|
|
|
|
.domain = domain,
|
|
|
|
|
.node = node,
|
|
|
|
|
.companion = root->device
|
|
|
|
|
};
|
2015-02-05 13:44:46 +08:00
|
|
|
|
2015-10-14 14:29:41 +08:00
|
|
|
memcpy(bus->sysdata, &sd, sizeof(sd));
|
|
|
|
|
} else {
|
|
|
|
|
struct pci_root_info *info;
|
|
|
|
|
|
|
|
|
|
info = kzalloc_node(sizeof(*info), GFP_KERNEL, node);
|
|
|
|
|
if (!info)
|
|
|
|
|
dev_err(&root->device->dev,
|
|
|
|
|
"pci_bus %04x:%02x: ignored (out of memory)\n",
|
|
|
|
|
domain, busnum);
|
|
|
|
|
else {
|
|
|
|
|
info->sd.domain = domain;
|
|
|
|
|
info->sd.node = node;
|
|
|
|
|
info->sd.companion = root->device;
|
|
|
|
|
bus = acpi_pci_root_create(root, &acpi_pci_root_ops,
|
|
|
|
|
&info->common, &info->sd);
|
2012-04-03 09:31:53 +08:00
|
|
|
}
|
2009-06-25 11:00:12 +08:00
|
|
|
}
|
2007-07-22 05:23:39 +08:00
|
|
|
|
PCI: Set PCI-E Max Payload Size on fabric
On a given PCI-E fabric, each device, bridge, and root port can have a
different PCI-E maximum payload size. There is a sizable performance
boost for having the largest possible maximum payload size on each PCI-E
device. However, if improperly configured, fatal bus errors can occur.
Thus, it is important to ensure that PCI-E payloads sends by a device
are never larger than the MPS setting of all devices on the way to the
destination.
This can be achieved two ways:
- A conservative approach is to use the smallest common denominator of
the entire tree below a root complex for every device on that fabric.
This means for example that having a 128 bytes MPS USB controller on one
leg of a switch will dramatically reduce performances of a video card or
10GE adapter on another leg of that same switch.
It also means that any hierarchy supporting hotplug slots (including
expresscard or thunderbolt I suppose, dbl check that) will have to be
entirely clamped to 128 bytes since we cannot predict what will be
plugged into those slots, and we cannot change the MPS on a "live"
system.
- A more optimal way is possible, if it falls within a couple of
constraints:
* The top-level host bridge will never generate packets larger than the
smallest TLP (or if it can be controlled independently from its MPS at
least)
* The device will never generate packets larger than MPS (which can be
configured via MRRS)
* No support of direct PCI-E <-> PCI-E transfers between devices without
some additional code to specifically deal with that case
Then we can use an approach that basically ignores downstream requests
and focuses exclusively on upstream requests. In that case, all we need
to care about is that a device MPS is no larger than its parent MPS,
which allows us to keep all switches/bridges to the max MPS supported by
their parent and eventually the PHB.
In this case, your USB controller would no longer "starve" your 10GE
Ethernet and your hotplug slots won't affect your global MPS.
Additionally, the hotplugged devices themselves can be configured to a
larger MPS up to the value configured in the hotplug bridge.
To choose between the two available options, two PCI kernel boot args
have been added to the PCI calls. "pcie_bus_safe" will provide the
former behavior, while "pcie_bus_perf" will perform the latter behavior.
By default, the latter behavior is used.
NOTE: due to the location of the enablement, each arch will need to add
calls to this function. This patch only enables x86.
This patch includes a number of changes recommended by Benjamin
Herrenschmidt.
Tested-by: Jordan_Hargrave@dell.com
Signed-off-by: Jon Mason <mason@myri.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2011-07-21 04:20:54 +08:00
|
|
|
/* After the PCI-E bus has been walked and all devices discovered,
|
|
|
|
|
* configure any settings of the fabric that might be necessary.
|
|
|
|
|
*/
|
|
|
|
|
if (bus) {
|
|
|
|
|
struct pci_bus *child;
|
2013-08-22 11:24:44 +08:00
|
|
|
list_for_each_entry(child, &bus->children, node)
|
|
|
|
|
pcie_bus_configure_settings(child);
|
PCI: Set PCI-E Max Payload Size on fabric
On a given PCI-E fabric, each device, bridge, and root port can have a
different PCI-E maximum payload size. There is a sizable performance
boost for having the largest possible maximum payload size on each PCI-E
device. However, if improperly configured, fatal bus errors can occur.
Thus, it is important to ensure that PCI-E payloads sends by a device
are never larger than the MPS setting of all devices on the way to the
destination.
This can be achieved two ways:
- A conservative approach is to use the smallest common denominator of
the entire tree below a root complex for every device on that fabric.
This means for example that having a 128 bytes MPS USB controller on one
leg of a switch will dramatically reduce performances of a video card or
10GE adapter on another leg of that same switch.
It also means that any hierarchy supporting hotplug slots (including
expresscard or thunderbolt I suppose, dbl check that) will have to be
entirely clamped to 128 bytes since we cannot predict what will be
plugged into those slots, and we cannot change the MPS on a "live"
system.
- A more optimal way is possible, if it falls within a couple of
constraints:
* The top-level host bridge will never generate packets larger than the
smallest TLP (or if it can be controlled independently from its MPS at
least)
* The device will never generate packets larger than MPS (which can be
configured via MRRS)
* No support of direct PCI-E <-> PCI-E transfers between devices without
some additional code to specifically deal with that case
Then we can use an approach that basically ignores downstream requests
and focuses exclusively on upstream requests. In that case, all we need
to care about is that a device MPS is no larger than its parent MPS,
which allows us to keep all switches/bridges to the max MPS supported by
their parent and eventually the PHB.
In this case, your USB controller would no longer "starve" your 10GE
Ethernet and your hotplug slots won't affect your global MPS.
Additionally, the hotplugged devices themselves can be configured to a
larger MPS up to the value configured in the hotplug bridge.
To choose between the two available options, two PCI kernel boot args
have been added to the PCI calls. "pcie_bus_safe" will provide the
former behavior, while "pcie_bus_perf" will perform the latter behavior.
By default, the latter behavior is used.
NOTE: due to the location of the enablement, each arch will need to add
calls to this function. This patch only enables x86.
This patch includes a number of changes recommended by Benjamin
Herrenschmidt.
Tested-by: Jordan_Hargrave@dell.com
Signed-off-by: Jon Mason <mason@myri.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2011-07-21 04:20:54 +08:00
|
|
|
}
|
|
|
|
|
|
2005-09-13 00:49:24 +08:00
|
|
|
return bus;
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
|
|
|
|
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ACPI / PCI: Set root bridge ACPI handle in advance
The ACPI handles of PCI root bridges need to be known to
acpi_bind_one(), so that it can create the appropriate
"firmware_node" and "physical_node" files for them, but currently
the way it gets to know those handles is not exactly straightforward
(to put it lightly).
This is how it works, roughly:
1. acpi_bus_scan() finds the handle of a PCI root bridge,
creates a struct acpi_device object for it and passes that
object to acpi_pci_root_add().
2. acpi_pci_root_add() creates a struct acpi_pci_root object,
populates its "device" field with its argument's address
(device->handle is the ACPI handle found in step 1).
3. The struct acpi_pci_root object created in step 2 is passed
to pci_acpi_scan_root() and used to get resources that are
passed to pci_create_root_bus().
4. pci_create_root_bus() creates a struct pci_host_bridge object
and passes its "dev" member to device_register().
5. platform_notify(), which for systems with ACPI is set to
acpi_platform_notify(), is called.
So far, so good. Now it starts to be "interesting".
6. acpi_find_bridge_device() is used to find the ACPI handle of
the given device (which is the PCI root bridge) and executes
acpi_pci_find_root_bridge(), among other things, for the
given device object.
7. acpi_pci_find_root_bridge() uses the name (sic!) of the given
device object to extract the segment and bus numbers of the PCI
root bridge and passes them to acpi_get_pci_rootbridge_handle().
8. acpi_get_pci_rootbridge_handle() browses the list of ACPI PCI
root bridges and finds the one that matches the given segment
and bus numbers. Its handle is then used to initialize the
ACPI handle of the PCI root bridge's device object by
acpi_bind_one(). However, this is *exactly* the ACPI handle we
started with in step 1.
Needless to say, this is quite embarassing, but it may be avoided
thanks to commit f3fd0c8 (ACPI: Allow ACPI handles of devices to be
initialized in advance), which makes it possible to initialize the
ACPI handle of a device before passing it to device_register().
Accordingly, add a new __weak routine, pcibios_root_bridge_prepare(),
defaulting to an empty implementation that can be replaced by the
interested architecutres (x86 and ia64 at the moment) with functions
that will set the root bridge's ACPI handle before its dev member is
passed to device_register(). Make both x86 and ia64 provide such
implementations of pcibios_root_bridge_prepare() and remove
acpi_pci_find_root_bridge() and acpi_get_pci_rootbridge_handle() that
aren't necessary any more.
Included is a fix for breakage on systems with non-ACPI PCI host
bridges from Bjorn Helgaas.
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2013-01-10 05:33:37 +08:00
|
|
|
int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
|
|
|
|
|
{
|
2015-05-28 07:39:53 +08:00
|
|
|
/*
|
|
|
|
|
* We pass NULL as parent to pci_create_root_bus(), so if it is not NULL
|
|
|
|
|
* here, pci_create_root_bus() has been called by someone else and
|
|
|
|
|
* sysdata is likely to be different from what we expect. Let it go in
|
|
|
|
|
* that case.
|
|
|
|
|
*/
|
|
|
|
|
if (!bridge->dev.parent) {
|
|
|
|
|
struct pci_sysdata *sd = bridge->bus->sysdata;
|
|
|
|
|
ACPI_COMPANION_SET(&bridge->dev, sd->companion);
|
|
|
|
|
}
|
ACPI / PCI: Set root bridge ACPI handle in advance
The ACPI handles of PCI root bridges need to be known to
acpi_bind_one(), so that it can create the appropriate
"firmware_node" and "physical_node" files for them, but currently
the way it gets to know those handles is not exactly straightforward
(to put it lightly).
This is how it works, roughly:
1. acpi_bus_scan() finds the handle of a PCI root bridge,
creates a struct acpi_device object for it and passes that
object to acpi_pci_root_add().
2. acpi_pci_root_add() creates a struct acpi_pci_root object,
populates its "device" field with its argument's address
(device->handle is the ACPI handle found in step 1).
3. The struct acpi_pci_root object created in step 2 is passed
to pci_acpi_scan_root() and used to get resources that are
passed to pci_create_root_bus().
4. pci_create_root_bus() creates a struct pci_host_bridge object
and passes its "dev" member to device_register().
5. platform_notify(), which for systems with ACPI is set to
acpi_platform_notify(), is called.
So far, so good. Now it starts to be "interesting".
6. acpi_find_bridge_device() is used to find the ACPI handle of
the given device (which is the PCI root bridge) and executes
acpi_pci_find_root_bridge(), among other things, for the
given device object.
7. acpi_pci_find_root_bridge() uses the name (sic!) of the given
device object to extract the segment and bus numbers of the PCI
root bridge and passes them to acpi_get_pci_rootbridge_handle().
8. acpi_get_pci_rootbridge_handle() browses the list of ACPI PCI
root bridges and finds the one that matches the given segment
and bus numbers. Its handle is then used to initialize the
ACPI handle of the PCI root bridge's device object by
acpi_bind_one(). However, this is *exactly* the ACPI handle we
started with in step 1.
Needless to say, this is quite embarassing, but it may be avoided
thanks to commit f3fd0c8 (ACPI: Allow ACPI handles of devices to be
initialized in advance), which makes it possible to initialize the
ACPI handle of a device before passing it to device_register().
Accordingly, add a new __weak routine, pcibios_root_bridge_prepare(),
defaulting to an empty implementation that can be replaced by the
interested architecutres (x86 and ia64 at the moment) with functions
that will set the root bridge's ACPI handle before its dev member is
passed to device_register(). Make both x86 and ia64 provide such
implementations of pcibios_root_bridge_prepare() and remove
acpi_pci_find_root_bridge() and acpi_get_pci_rootbridge_handle() that
aren't necessary any more.
Included is a fix for breakage on systems with non-ACPI PCI host
bridges from Bjorn Helgaas.
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2013-01-10 05:33:37 +08:00
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2008-07-03 04:50:29 +08:00
|
|
|
int __init pci_acpi_init(void)
|
2005-04-17 06:20:36 +08:00
|
|
|
{
|
|
|
|
|
struct pci_dev *dev = NULL;
|
|
|
|
|
|
|
|
|
|
if (acpi_noirq)
|
2009-08-29 22:24:51 +08:00
|
|
|
return -ENODEV;
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
|
printk(KERN_INFO "PCI: Using ACPI for IRQ routing\n");
|
|
|
|
|
acpi_irq_penalty_init();
|
|
|
|
|
pcibios_enable_irq = acpi_pci_irq_enable;
|
2005-07-28 11:02:00 +08:00
|
|
|
pcibios_disable_irq = acpi_pci_irq_disable;
|
2009-08-29 23:47:33 +08:00
|
|
|
x86_init.pci.init_irq = x86_init_noop;
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
|
if (pci_routeirq) {
|
|
|
|
|
/*
|
|
|
|
|
* PCI IRQ routing is set up by pci_enable_device(), but we
|
|
|
|
|
* also do it here in case there are still broken drivers that
|
|
|
|
|
* don't use pci_enable_device().
|
|
|
|
|
*/
|
|
|
|
|
printk(KERN_INFO "PCI: Routing PCI interrupts for all devices because \"pci=routeirq\" specified\n");
|
2005-11-07 15:39:36 +08:00
|
|
|
for_each_pci_dev(dev)
|
2005-04-17 06:20:36 +08:00
|
|
|
acpi_pci_irq_enable(dev);
|
2008-02-19 00:44:13 +08:00
|
|
|
}
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|