usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
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/**
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* core.c - DesignWare USB3 DRD Controller Core file
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*
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* Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
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*
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* Authors: Felipe Balbi <balbi@ti.com>,
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* Sebastian Andrzej Siewior <bigeasy@linutronix.de>
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*
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2013-06-30 19:15:11 +08:00
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 of
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* the License as published by the Free Software Foundation.
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usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
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*
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2013-06-30 19:15:11 +08:00
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
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*
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2013-06-30 19:15:11 +08:00
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
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*/
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2014-09-20 04:51:11 +08:00
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#include <linux/version.h>
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2011-09-05 18:37:28 +08:00
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#include <linux/module.h>
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usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/io.h>
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#include <linux/list.h>
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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2012-01-19 00:04:09 +08:00
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#include <linux/of.h>
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2014-09-25 15:57:02 +08:00
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#include <linux/acpi.h>
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2015-08-31 23:39:08 +08:00
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#include <linux/pinctrl/consumer.h>
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usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
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#include <linux/usb/ch9.h>
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#include <linux/usb/gadget.h>
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2013-06-30 19:29:51 +08:00
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#include <linux/usb/of.h>
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2013-07-06 20:52:49 +08:00
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#include <linux/usb/otg.h>
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usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
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#include "core.h"
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#include "gadget.h"
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#include "io.h"
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#include "debug.h"
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2016-05-16 18:14:48 +08:00
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#define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */
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2011-10-18 18:54:01 +08:00
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2011-11-01 05:25:40 +08:00
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void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
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{
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u32 reg;
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reg = dwc3_readl(dwc->regs, DWC3_GCTL);
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reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
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reg |= DWC3_GCTL_PRTCAPDIR(mode);
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dwc3_writel(dwc->regs, DWC3_GCTL, reg);
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}
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2011-10-18 18:54:01 +08:00
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2016-04-14 20:03:39 +08:00
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u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
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{
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struct dwc3 *dwc = dep->dwc;
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u32 reg;
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dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
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DWC3_GDBGFIFOSPACE_NUM(dep->number) |
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DWC3_GDBGFIFOSPACE_TYPE(type));
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reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
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return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
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}
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|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
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/**
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* dwc3_core_soft_reset - Issues core soft reset and PHY reset
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* @dwc: pointer to our context structure
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*/
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2014-03-03 19:38:11 +08:00
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static int dwc3_core_soft_reset(struct dwc3 *dwc)
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usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
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{
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u32 reg;
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2016-03-11 16:51:52 +08:00
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int retries = 1000;
|
2014-03-03 19:38:11 +08:00
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int ret;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
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2012-07-19 19:09:48 +08:00
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usb_phy_init(dwc->usb2_phy);
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usb_phy_init(dwc->usb3_phy);
|
2014-03-03 19:38:11 +08:00
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ret = phy_init(dwc->usb2_generic_phy);
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if (ret < 0)
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return ret;
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ret = phy_init(dwc->usb3_generic_phy);
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if (ret < 0) {
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phy_exit(dwc->usb2_generic_phy);
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return ret;
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}
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
2016-03-11 16:51:52 +08:00
|
|
|
/*
|
|
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* We're resetting only the device side because, if we're in host mode,
|
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* XHCI driver will reset the host block. If dwc3 was configured for
|
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|
* host-only mode, then we can return early.
|
|
|
|
*/
|
|
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|
if (dwc->dr_mode == USB_DR_MODE_HOST)
|
|
|
|
return 0;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
2016-03-11 16:51:52 +08:00
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_DCTL);
|
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|
|
reg |= DWC3_DCTL_CSFTRST;
|
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|
|
dwc3_writel(dwc->regs, DWC3_DCTL, reg);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
2016-03-11 16:51:52 +08:00
|
|
|
do {
|
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_DCTL);
|
|
|
|
if (!(reg & DWC3_DCTL_CSFTRST))
|
|
|
|
return 0;
|
2012-06-21 20:14:28 +08:00
|
|
|
|
2016-03-11 16:51:52 +08:00
|
|
|
udelay(1);
|
|
|
|
} while (--retries);
|
2014-03-03 19:38:11 +08:00
|
|
|
|
2016-03-11 16:51:52 +08:00
|
|
|
return -ETIMEDOUT;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
}
|
|
|
|
|
2015-05-13 20:26:47 +08:00
|
|
|
/**
|
|
|
|
* dwc3_soft_reset - Issue soft reset
|
|
|
|
* @dwc: Pointer to our controller context structure
|
|
|
|
*/
|
|
|
|
static int dwc3_soft_reset(struct dwc3 *dwc)
|
|
|
|
{
|
|
|
|
unsigned long timeout;
|
|
|
|
u32 reg;
|
|
|
|
|
|
|
|
timeout = jiffies + msecs_to_jiffies(500);
|
|
|
|
dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
|
|
|
|
do {
|
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_DCTL);
|
|
|
|
if (!(reg & DWC3_DCTL_CSFTRST))
|
|
|
|
break;
|
|
|
|
|
|
|
|
if (time_after(jiffies, timeout)) {
|
|
|
|
dev_err(dwc->dev, "Reset Timed Out\n");
|
|
|
|
return -ETIMEDOUT;
|
|
|
|
}
|
|
|
|
|
|
|
|
cpu_relax();
|
|
|
|
} while (true);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2015-09-04 12:45:58 +08:00
|
|
|
/*
|
|
|
|
* dwc3_frame_length_adjustment - Adjusts frame length if required
|
|
|
|
* @dwc3: Pointer to our controller context structure
|
|
|
|
*/
|
2016-05-16 15:42:23 +08:00
|
|
|
static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
|
2015-09-04 12:45:58 +08:00
|
|
|
{
|
|
|
|
u32 reg;
|
|
|
|
u32 dft;
|
|
|
|
|
|
|
|
if (dwc->revision < DWC3_REVISION_250A)
|
|
|
|
return;
|
|
|
|
|
2016-05-16 15:42:23 +08:00
|
|
|
if (dwc->fladj == 0)
|
2015-09-04 12:45:58 +08:00
|
|
|
return;
|
|
|
|
|
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
|
|
|
|
dft = reg & DWC3_GFLADJ_30MHZ_MASK;
|
2016-05-16 15:42:23 +08:00
|
|
|
if (!dev_WARN_ONCE(dwc->dev, dft == dwc->fladj,
|
2015-09-04 12:45:58 +08:00
|
|
|
"request value same as default, ignoring\n")) {
|
|
|
|
reg &= ~DWC3_GFLADJ_30MHZ_MASK;
|
2016-05-16 15:42:23 +08:00
|
|
|
reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
|
2015-09-04 12:45:58 +08:00
|
|
|
dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
/**
|
|
|
|
* dwc3_free_one_event_buffer - Frees one event buffer
|
|
|
|
* @dwc: Pointer to our controller context structure
|
|
|
|
* @evt: Pointer to event buffer to be freed
|
|
|
|
*/
|
|
|
|
static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
|
|
|
|
struct dwc3_event_buffer *evt)
|
|
|
|
{
|
|
|
|
dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma);
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
2012-02-16 10:56:56 +08:00
|
|
|
* dwc3_alloc_one_event_buffer - Allocates one event buffer structure
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
* @dwc: Pointer to our controller context structure
|
|
|
|
* @length: size of the event buffer
|
|
|
|
*
|
2012-02-16 10:56:56 +08:00
|
|
|
* Returns a pointer to the allocated event buffer structure on success
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
* otherwise ERR_PTR(errno).
|
|
|
|
*/
|
2013-02-22 22:31:07 +08:00
|
|
|
static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
|
|
|
|
unsigned length)
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
{
|
|
|
|
struct dwc3_event_buffer *evt;
|
|
|
|
|
2012-10-11 18:48:36 +08:00
|
|
|
evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
if (!evt)
|
|
|
|
return ERR_PTR(-ENOMEM);
|
|
|
|
|
|
|
|
evt->dwc = dwc;
|
|
|
|
evt->length = length;
|
|
|
|
evt->buf = dma_alloc_coherent(dwc->dev, length,
|
|
|
|
&evt->dma, GFP_KERNEL);
|
2012-11-08 21:26:41 +08:00
|
|
|
if (!evt->buf)
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
return ERR_PTR(-ENOMEM);
|
|
|
|
|
|
|
|
return evt;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* dwc3_free_event_buffers - frees all allocated event buffers
|
|
|
|
* @dwc: Pointer to our controller context structure
|
|
|
|
*/
|
|
|
|
static void dwc3_free_event_buffers(struct dwc3 *dwc)
|
|
|
|
{
|
|
|
|
struct dwc3_event_buffer *evt;
|
|
|
|
|
2016-03-30 14:37:03 +08:00
|
|
|
evt = dwc->ev_buf;
|
2016-03-30 14:26:24 +08:00
|
|
|
if (evt)
|
|
|
|
dwc3_free_one_event_buffer(dwc, evt);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
|
2012-02-16 10:56:56 +08:00
|
|
|
* @dwc: pointer to our controller context structure
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
* @length: size of event buffer
|
|
|
|
*
|
2012-02-16 10:56:56 +08:00
|
|
|
* Returns 0 on success otherwise negative errno. In the error case, dwc
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
* may contain some buffers allocated but not all which were requested.
|
|
|
|
*/
|
2012-11-20 02:21:48 +08:00
|
|
|
static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
{
|
2016-03-30 14:26:24 +08:00
|
|
|
struct dwc3_event_buffer *evt;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
2016-03-30 14:26:24 +08:00
|
|
|
evt = dwc3_alloc_one_event_buffer(dwc, length);
|
|
|
|
if (IS_ERR(evt)) {
|
|
|
|
dev_err(dwc->dev, "can't allocate event buffer\n");
|
|
|
|
return PTR_ERR(evt);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
}
|
2016-03-30 14:37:03 +08:00
|
|
|
dwc->ev_buf = evt;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* dwc3_event_buffers_setup - setup our allocated event buffers
|
2012-02-16 10:56:56 +08:00
|
|
|
* @dwc: pointer to our controller context structure
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
*
|
|
|
|
* Returns 0 on success otherwise negative errno.
|
|
|
|
*/
|
2012-04-27 19:28:02 +08:00
|
|
|
static int dwc3_event_buffers_setup(struct dwc3 *dwc)
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
{
|
|
|
|
struct dwc3_event_buffer *evt;
|
|
|
|
|
2016-03-30 14:37:03 +08:00
|
|
|
evt = dwc->ev_buf;
|
2016-03-30 14:26:24 +08:00
|
|
|
dwc3_trace(trace_dwc3_core,
|
|
|
|
"Event buf %p dma %08llx length %d\n",
|
|
|
|
evt->buf, (unsigned long long) evt->dma,
|
|
|
|
evt->length);
|
|
|
|
|
|
|
|
evt->lpos = 0;
|
|
|
|
|
|
|
|
dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
|
|
|
|
lower_32_bits(evt->dma));
|
|
|
|
dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
|
|
|
|
upper_32_bits(evt->dma));
|
|
|
|
dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
|
|
|
|
DWC3_GEVNTSIZ_SIZE(evt->length));
|
|
|
|
dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
|
|
|
|
{
|
|
|
|
struct dwc3_event_buffer *evt;
|
|
|
|
|
2016-03-30 14:37:03 +08:00
|
|
|
evt = dwc->ev_buf;
|
2012-04-27 19:28:02 +08:00
|
|
|
|
2016-03-30 14:26:24 +08:00
|
|
|
evt->lpos = 0;
|
2012-04-27 19:28:02 +08:00
|
|
|
|
2016-03-30 14:26:24 +08:00
|
|
|
dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
|
|
|
|
dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
|
|
|
|
dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
|
|
|
|
| DWC3_GEVNTSIZ_SIZE(0));
|
|
|
|
dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
}
|
|
|
|
|
2013-12-20 03:04:28 +08:00
|
|
|
static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
|
|
|
|
{
|
|
|
|
if (!dwc->has_hibernation)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
if (!dwc->nr_scratch)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
|
|
|
|
DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
|
|
|
|
if (!dwc->scratchbuf)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
|
|
|
|
{
|
|
|
|
dma_addr_t scratch_addr;
|
|
|
|
u32 param;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
if (!dwc->has_hibernation)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
if (!dwc->nr_scratch)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
/* should never fall here */
|
|
|
|
if (!WARN_ON(dwc->scratchbuf))
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
scratch_addr = dma_map_single(dwc->dev, dwc->scratchbuf,
|
|
|
|
dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
|
|
|
|
DMA_BIDIRECTIONAL);
|
|
|
|
if (dma_mapping_error(dwc->dev, scratch_addr)) {
|
|
|
|
dev_err(dwc->dev, "failed to map scratch buffer\n");
|
|
|
|
ret = -EFAULT;
|
|
|
|
goto err0;
|
|
|
|
}
|
|
|
|
|
|
|
|
dwc->scratch_addr = scratch_addr;
|
|
|
|
|
|
|
|
param = lower_32_bits(scratch_addr);
|
|
|
|
|
|
|
|
ret = dwc3_send_gadget_generic_command(dwc,
|
|
|
|
DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
|
|
|
|
if (ret < 0)
|
|
|
|
goto err1;
|
|
|
|
|
|
|
|
param = upper_32_bits(scratch_addr);
|
|
|
|
|
|
|
|
ret = dwc3_send_gadget_generic_command(dwc,
|
|
|
|
DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
|
|
|
|
if (ret < 0)
|
|
|
|
goto err1;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
err1:
|
|
|
|
dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch *
|
|
|
|
DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
|
|
|
|
|
|
|
|
err0:
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
|
|
|
|
{
|
|
|
|
if (!dwc->has_hibernation)
|
|
|
|
return;
|
|
|
|
|
|
|
|
if (!dwc->nr_scratch)
|
|
|
|
return;
|
|
|
|
|
|
|
|
/* should never fall here */
|
|
|
|
if (!WARN_ON(dwc->scratchbuf))
|
|
|
|
return;
|
|
|
|
|
|
|
|
dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch *
|
|
|
|
DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
|
|
|
|
kfree(dwc->scratchbuf);
|
|
|
|
}
|
|
|
|
|
2011-05-05 20:53:10 +08:00
|
|
|
static void dwc3_core_num_eps(struct dwc3 *dwc)
|
|
|
|
{
|
|
|
|
struct dwc3_hwparams *parms = &dwc->hwparams;
|
|
|
|
|
|
|
|
dwc->num_in_eps = DWC3_NUM_IN_EPS(parms);
|
|
|
|
dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps;
|
|
|
|
|
2015-01-28 03:48:14 +08:00
|
|
|
dwc3_trace(trace_dwc3_core, "found %d IN and %d OUT endpoints",
|
2011-05-05 20:53:10 +08:00
|
|
|
dwc->num_in_eps, dwc->num_out_eps);
|
|
|
|
}
|
|
|
|
|
2012-11-20 02:21:48 +08:00
|
|
|
static void dwc3_cache_hwparams(struct dwc3 *dwc)
|
2011-09-30 15:58:49 +08:00
|
|
|
{
|
|
|
|
struct dwc3_hwparams *parms = &dwc->hwparams;
|
|
|
|
|
|
|
|
parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
|
|
|
|
parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
|
|
|
|
parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
|
|
|
|
parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
|
|
|
|
parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
|
|
|
|
parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
|
|
|
|
parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
|
|
|
|
parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
|
|
|
|
parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
|
|
|
|
}
|
|
|
|
|
2014-10-28 19:54:28 +08:00
|
|
|
/**
|
|
|
|
* dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
|
|
|
|
* @dwc: Pointer to our controller context structure
|
2015-05-13 20:26:51 +08:00
|
|
|
*
|
|
|
|
* Returns 0 on success. The USB PHY interfaces are configured but not
|
|
|
|
* initialized. The PHY interfaces and the PHYs get initialized together with
|
|
|
|
* the core in dwc3_core_init.
|
2014-10-28 19:54:28 +08:00
|
|
|
*/
|
2015-05-13 20:26:51 +08:00
|
|
|
static int dwc3_phy_setup(struct dwc3 *dwc)
|
2014-10-28 19:54:28 +08:00
|
|
|
{
|
|
|
|
u32 reg;
|
2015-05-13 20:26:51 +08:00
|
|
|
int ret;
|
2014-10-28 19:54:28 +08:00
|
|
|
|
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
|
|
|
|
|
2014-10-28 19:54:35 +08:00
|
|
|
/*
|
|
|
|
* Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
|
|
|
|
* to '0' during coreConsultant configuration. So default value
|
|
|
|
* will be '0' when the core is reset. Application needs to set it
|
|
|
|
* to '1' after the core initialization is completed.
|
|
|
|
*/
|
|
|
|
if (dwc->revision > DWC3_REVISION_194A)
|
|
|
|
reg |= DWC3_GUSB3PIPECTL_SUSPHY;
|
|
|
|
|
2014-10-28 19:54:28 +08:00
|
|
|
if (dwc->u2ss_inp3_quirk)
|
|
|
|
reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
|
|
|
|
|
2016-03-14 17:10:50 +08:00
|
|
|
if (dwc->dis_rxdet_inp3_quirk)
|
|
|
|
reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
|
|
|
|
|
2014-10-28 19:54:29 +08:00
|
|
|
if (dwc->req_p1p2p3_quirk)
|
|
|
|
reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
|
|
|
|
|
2014-10-28 19:54:30 +08:00
|
|
|
if (dwc->del_p1p2p3_quirk)
|
|
|
|
reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
|
|
|
|
|
2014-10-28 19:54:31 +08:00
|
|
|
if (dwc->del_phy_power_chg_quirk)
|
|
|
|
reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
|
|
|
|
|
2014-10-28 19:54:32 +08:00
|
|
|
if (dwc->lfps_filter_quirk)
|
|
|
|
reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
|
|
|
|
|
2014-10-28 19:54:33 +08:00
|
|
|
if (dwc->rx_detect_poll_quirk)
|
|
|
|
reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
|
|
|
|
|
2014-10-31 11:11:12 +08:00
|
|
|
if (dwc->tx_de_emphasis_quirk)
|
|
|
|
reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
|
|
|
|
|
2014-11-07 01:31:00 +08:00
|
|
|
if (dwc->dis_u3_susphy_quirk)
|
2014-10-31 11:11:13 +08:00
|
|
|
reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
|
|
|
|
|
2014-10-28 19:54:28 +08:00
|
|
|
dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
|
|
|
|
|
2014-10-28 19:54:35 +08:00
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
|
|
|
|
|
2015-05-13 20:26:49 +08:00
|
|
|
/* Select the HS PHY interface */
|
|
|
|
switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
|
|
|
|
case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
|
2015-07-02 11:03:09 +08:00
|
|
|
if (dwc->hsphy_interface &&
|
|
|
|
!strncmp(dwc->hsphy_interface, "utmi", 4)) {
|
2015-05-13 20:26:49 +08:00
|
|
|
reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
|
2015-05-13 20:26:51 +08:00
|
|
|
break;
|
2015-07-02 11:03:09 +08:00
|
|
|
} else if (dwc->hsphy_interface &&
|
|
|
|
!strncmp(dwc->hsphy_interface, "ulpi", 4)) {
|
2015-05-13 20:26:49 +08:00
|
|
|
reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
|
2015-05-13 20:26:51 +08:00
|
|
|
dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
|
2015-05-13 20:26:49 +08:00
|
|
|
} else {
|
2015-05-13 20:26:51 +08:00
|
|
|
/* Relying on default value. */
|
|
|
|
if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
|
|
|
|
break;
|
2015-05-13 20:26:49 +08:00
|
|
|
}
|
|
|
|
/* FALLTHROUGH */
|
2015-05-13 20:26:51 +08:00
|
|
|
case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
|
|
|
|
/* Making sure the interface and PHY are operational */
|
|
|
|
ret = dwc3_soft_reset(dwc);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
udelay(1);
|
|
|
|
|
|
|
|
ret = dwc3_ulpi_init(dwc);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
/* FALLTHROUGH */
|
2015-05-13 20:26:49 +08:00
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2016-08-16 22:44:38 +08:00
|
|
|
switch (dwc->hsphy_mode) {
|
|
|
|
case USBPHY_INTERFACE_MODE_UTMI:
|
|
|
|
reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
|
|
|
|
DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
|
|
|
|
reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
|
|
|
|
DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
|
|
|
|
break;
|
|
|
|
case USBPHY_INTERFACE_MODE_UTMIW:
|
|
|
|
reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
|
|
|
|
DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
|
|
|
|
reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
|
|
|
|
DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2014-10-28 19:54:35 +08:00
|
|
|
/*
|
|
|
|
* Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
|
|
|
|
* '0' during coreConsultant configuration. So default value will
|
|
|
|
* be '0' when the core is reset. Application needs to set it to
|
|
|
|
* '1' after the core initialization is completed.
|
|
|
|
*/
|
|
|
|
if (dwc->revision > DWC3_REVISION_194A)
|
|
|
|
reg |= DWC3_GUSB2PHYCFG_SUSPHY;
|
|
|
|
|
2014-11-07 01:31:00 +08:00
|
|
|
if (dwc->dis_u2_susphy_quirk)
|
2014-10-31 11:11:14 +08:00
|
|
|
reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
|
|
|
|
|
2015-10-03 11:30:57 +08:00
|
|
|
if (dwc->dis_enblslpm_quirk)
|
|
|
|
reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
|
|
|
|
|
2016-08-16 22:44:37 +08:00
|
|
|
if (dwc->dis_u2_freeclk_exists_quirk)
|
|
|
|
reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
|
|
|
|
|
2014-10-28 19:54:35 +08:00
|
|
|
dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
|
2015-05-13 20:26:51 +08:00
|
|
|
|
|
|
|
return 0;
|
2014-10-28 19:54:28 +08:00
|
|
|
}
|
|
|
|
|
2016-05-16 15:49:01 +08:00
|
|
|
static void dwc3_core_exit(struct dwc3 *dwc)
|
|
|
|
{
|
|
|
|
dwc3_event_buffers_cleanup(dwc);
|
|
|
|
|
|
|
|
usb_phy_shutdown(dwc->usb2_phy);
|
|
|
|
usb_phy_shutdown(dwc->usb3_phy);
|
|
|
|
phy_exit(dwc->usb2_generic_phy);
|
|
|
|
phy_exit(dwc->usb3_generic_phy);
|
|
|
|
|
|
|
|
usb_phy_set_suspend(dwc->usb2_phy, 1);
|
|
|
|
usb_phy_set_suspend(dwc->usb3_phy, 1);
|
|
|
|
phy_power_off(dwc->usb2_generic_phy);
|
|
|
|
phy_power_off(dwc->usb3_generic_phy);
|
|
|
|
}
|
|
|
|
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
/**
|
|
|
|
* dwc3_core_init - Low-level initialization of DWC3 Core
|
|
|
|
* @dwc: Pointer to our controller context structure
|
|
|
|
*
|
|
|
|
* Returns 0 on success otherwise negative errno.
|
|
|
|
*/
|
2012-11-20 02:21:48 +08:00
|
|
|
static int dwc3_core_init(struct dwc3 *dwc)
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
{
|
2013-12-20 03:04:28 +08:00
|
|
|
u32 hwparams4 = dwc->hwparams.hwparams4;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
u32 reg;
|
|
|
|
int ret;
|
|
|
|
|
2011-08-29 19:56:36 +08:00
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
|
|
|
|
/* This should read as U3 followed by revision number */
|
2015-09-05 10:15:10 +08:00
|
|
|
if ((reg & DWC3_GSNPSID_MASK) == 0x55330000) {
|
|
|
|
/* Detected DWC_usb3 IP */
|
|
|
|
dwc->revision = reg;
|
|
|
|
} else if ((reg & DWC3_GSNPSID_MASK) == 0x33310000) {
|
|
|
|
/* Detected DWC_usb31 IP */
|
|
|
|
dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
|
|
|
|
dwc->revision |= DWC3_REVISION_IS_DWC31;
|
|
|
|
} else {
|
2011-08-29 19:56:36 +08:00
|
|
|
dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
|
|
|
|
ret = -ENODEV;
|
|
|
|
goto err0;
|
|
|
|
}
|
|
|
|
|
2014-09-20 04:51:11 +08:00
|
|
|
/*
|
|
|
|
* Write Linux Version Code to our GUID register so it's easy to figure
|
|
|
|
* out which kernel version a bug was found.
|
|
|
|
*/
|
|
|
|
dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
|
|
|
|
|
2014-05-24 02:39:24 +08:00
|
|
|
/* Handle USB2.0-only core configuration */
|
|
|
|
if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
|
|
|
|
DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
|
|
|
|
if (dwc->maximum_speed == USB_SPEED_SUPER)
|
|
|
|
dwc->maximum_speed = USB_SPEED_HIGH;
|
|
|
|
}
|
|
|
|
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
/* issue device SoftReset too */
|
2015-05-13 20:26:47 +08:00
|
|
|
ret = dwc3_soft_reset(dwc);
|
|
|
|
if (ret)
|
|
|
|
goto err0;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
2014-03-03 19:38:11 +08:00
|
|
|
ret = dwc3_core_soft_reset(dwc);
|
|
|
|
if (ret)
|
|
|
|
goto err0;
|
2012-06-21 20:14:29 +08:00
|
|
|
|
2016-05-16 15:49:01 +08:00
|
|
|
ret = dwc3_phy_setup(dwc);
|
|
|
|
if (ret)
|
|
|
|
goto err0;
|
|
|
|
|
2011-11-01 05:25:41 +08:00
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_GCTL);
|
2012-02-25 09:32:13 +08:00
|
|
|
reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
|
2011-11-01 05:25:41 +08:00
|
|
|
|
2011-11-24 18:22:05 +08:00
|
|
|
switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
|
2011-11-01 05:25:41 +08:00
|
|
|
case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
|
2014-02-26 04:00:13 +08:00
|
|
|
/**
|
|
|
|
* WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
|
|
|
|
* issue which would cause xHCI compliance tests to fail.
|
|
|
|
*
|
|
|
|
* Because of that we cannot enable clock gating on such
|
|
|
|
* configurations.
|
|
|
|
*
|
|
|
|
* Refers to:
|
|
|
|
*
|
|
|
|
* STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
|
|
|
|
* SOF/ITP Mode Used
|
|
|
|
*/
|
|
|
|
if ((dwc->dr_mode == USB_DR_MODE_HOST ||
|
|
|
|
dwc->dr_mode == USB_DR_MODE_OTG) &&
|
|
|
|
(dwc->revision >= DWC3_REVISION_210A &&
|
|
|
|
dwc->revision <= DWC3_REVISION_250A))
|
|
|
|
reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
|
|
|
|
else
|
|
|
|
reg &= ~DWC3_GCTL_DSBLCLKGTNG;
|
2011-11-01 05:25:41 +08:00
|
|
|
break;
|
2013-12-20 03:04:28 +08:00
|
|
|
case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
|
|
|
|
/* enable hibernation here */
|
|
|
|
dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
|
2014-10-28 19:54:22 +08:00
|
|
|
|
|
|
|
/*
|
|
|
|
* REVISIT Enabling this bit so that host-mode hibernation
|
|
|
|
* will work. Device-mode hibernation is not yet implemented.
|
|
|
|
*/
|
|
|
|
reg |= DWC3_GCTL_GBLHIBERNATIONEN;
|
2013-12-20 03:04:28 +08:00
|
|
|
break;
|
2011-11-01 05:25:41 +08:00
|
|
|
default:
|
2015-11-17 06:06:37 +08:00
|
|
|
dwc3_trace(trace_dwc3_core, "No power optimization available\n");
|
2011-11-01 05:25:41 +08:00
|
|
|
}
|
|
|
|
|
2014-10-28 19:54:23 +08:00
|
|
|
/* check if current dwc3 is on simulation board */
|
|
|
|
if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
|
2015-11-17 06:06:37 +08:00
|
|
|
dwc3_trace(trace_dwc3_core,
|
|
|
|
"running on FPGA platform\n");
|
2014-10-28 19:54:23 +08:00
|
|
|
dwc->is_fpga = true;
|
|
|
|
}
|
|
|
|
|
2014-10-28 19:54:25 +08:00
|
|
|
WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
|
|
|
|
"disable_scramble cannot be used on non-FPGA builds\n");
|
|
|
|
|
|
|
|
if (dwc->disable_scramble_quirk && dwc->is_fpga)
|
|
|
|
reg |= DWC3_GCTL_DISSCRAMBLE;
|
|
|
|
else
|
|
|
|
reg &= ~DWC3_GCTL_DISSCRAMBLE;
|
|
|
|
|
2014-10-28 19:54:27 +08:00
|
|
|
if (dwc->u2exit_lfps_quirk)
|
|
|
|
reg |= DWC3_GCTL_U2EXIT_LFPS;
|
|
|
|
|
2011-11-01 05:25:41 +08:00
|
|
|
/*
|
|
|
|
* WORKAROUND: DWC3 revisions <1.90a have a bug
|
2012-02-16 10:56:56 +08:00
|
|
|
* where the device can fail to connect at SuperSpeed
|
2011-11-01 05:25:41 +08:00
|
|
|
* and falls back to high-speed mode which causes
|
2012-02-16 10:56:56 +08:00
|
|
|
* the device to enter a Connect/Disconnect loop
|
2011-11-01 05:25:41 +08:00
|
|
|
*/
|
|
|
|
if (dwc->revision < DWC3_REVISION_190A)
|
|
|
|
reg |= DWC3_GCTL_U2RSTECN;
|
|
|
|
|
|
|
|
dwc3_writel(dwc->regs, DWC3_GCTL, reg);
|
|
|
|
|
2016-05-16 15:49:01 +08:00
|
|
|
dwc3_core_num_eps(dwc);
|
2013-12-20 03:04:28 +08:00
|
|
|
|
|
|
|
ret = dwc3_setup_scratch_buffers(dwc);
|
|
|
|
if (ret)
|
2016-05-16 15:49:01 +08:00
|
|
|
goto err1;
|
|
|
|
|
|
|
|
/* Adjust Frame Length */
|
|
|
|
dwc3_frame_length_adjustment(dwc);
|
|
|
|
|
|
|
|
usb_phy_set_suspend(dwc->usb2_phy, 0);
|
|
|
|
usb_phy_set_suspend(dwc->usb3_phy, 0);
|
|
|
|
ret = phy_power_on(dwc->usb2_generic_phy);
|
|
|
|
if (ret < 0)
|
2013-12-20 03:04:28 +08:00
|
|
|
goto err2;
|
|
|
|
|
2016-05-16 15:49:01 +08:00
|
|
|
ret = phy_power_on(dwc->usb3_generic_phy);
|
|
|
|
if (ret < 0)
|
|
|
|
goto err3;
|
|
|
|
|
|
|
|
ret = dwc3_event_buffers_setup(dwc);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(dwc->dev, "failed to setup event buffers\n");
|
|
|
|
goto err4;
|
|
|
|
}
|
|
|
|
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
return 0;
|
|
|
|
|
2016-05-16 15:49:01 +08:00
|
|
|
err4:
|
|
|
|
phy_power_off(dwc->usb2_generic_phy);
|
|
|
|
|
|
|
|
err3:
|
|
|
|
phy_power_off(dwc->usb3_generic_phy);
|
|
|
|
|
2013-12-20 03:04:28 +08:00
|
|
|
err2:
|
2016-05-16 15:49:01 +08:00
|
|
|
usb_phy_set_suspend(dwc->usb2_phy, 1);
|
|
|
|
usb_phy_set_suspend(dwc->usb3_phy, 1);
|
|
|
|
dwc3_core_exit(dwc);
|
2013-12-20 03:04:28 +08:00
|
|
|
|
|
|
|
err1:
|
|
|
|
usb_phy_shutdown(dwc->usb2_phy);
|
|
|
|
usb_phy_shutdown(dwc->usb3_phy);
|
2014-03-03 19:38:11 +08:00
|
|
|
phy_exit(dwc->usb2_generic_phy);
|
|
|
|
phy_exit(dwc->usb3_generic_phy);
|
2013-12-20 03:04:28 +08:00
|
|
|
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
err0:
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2014-04-17 04:08:29 +08:00
|
|
|
static int dwc3_core_get_phy(struct dwc3 *dwc)
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
{
|
2014-04-17 04:08:29 +08:00
|
|
|
struct device *dev = dwc->dev;
|
2013-07-31 14:21:25 +08:00
|
|
|
struct device_node *node = dev->of_node;
|
2014-04-17 04:08:29 +08:00
|
|
|
int ret;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
2013-01-25 19:06:53 +08:00
|
|
|
if (node) {
|
|
|
|
dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
|
|
|
|
dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
|
2013-08-15 02:21:23 +08:00
|
|
|
} else {
|
|
|
|
dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
|
|
|
|
dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
|
2013-01-25 19:06:53 +08:00
|
|
|
}
|
|
|
|
|
2013-03-15 16:52:08 +08:00
|
|
|
if (IS_ERR(dwc->usb2_phy)) {
|
|
|
|
ret = PTR_ERR(dwc->usb2_phy);
|
2014-03-03 19:38:10 +08:00
|
|
|
if (ret == -ENXIO || ret == -ENODEV) {
|
|
|
|
dwc->usb2_phy = NULL;
|
|
|
|
} else if (ret == -EPROBE_DEFER) {
|
2013-03-15 16:52:08 +08:00
|
|
|
return ret;
|
2014-03-03 19:38:10 +08:00
|
|
|
} else {
|
|
|
|
dev_err(dev, "no usb2 phy configured\n");
|
|
|
|
return ret;
|
|
|
|
}
|
2012-07-19 19:09:48 +08:00
|
|
|
}
|
|
|
|
|
2013-03-15 16:52:08 +08:00
|
|
|
if (IS_ERR(dwc->usb3_phy)) {
|
2013-07-04 13:59:34 +08:00
|
|
|
ret = PTR_ERR(dwc->usb3_phy);
|
2014-03-03 19:38:10 +08:00
|
|
|
if (ret == -ENXIO || ret == -ENODEV) {
|
|
|
|
dwc->usb3_phy = NULL;
|
|
|
|
} else if (ret == -EPROBE_DEFER) {
|
2013-03-15 16:52:08 +08:00
|
|
|
return ret;
|
2014-03-03 19:38:10 +08:00
|
|
|
} else {
|
|
|
|
dev_err(dev, "no usb3 phy configured\n");
|
|
|
|
return ret;
|
|
|
|
}
|
2012-07-19 19:09:48 +08:00
|
|
|
}
|
|
|
|
|
2014-03-03 19:38:11 +08:00
|
|
|
dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
|
|
|
|
if (IS_ERR(dwc->usb2_generic_phy)) {
|
|
|
|
ret = PTR_ERR(dwc->usb2_generic_phy);
|
|
|
|
if (ret == -ENOSYS || ret == -ENODEV) {
|
|
|
|
dwc->usb2_generic_phy = NULL;
|
|
|
|
} else if (ret == -EPROBE_DEFER) {
|
|
|
|
return ret;
|
|
|
|
} else {
|
|
|
|
dev_err(dev, "no usb2 phy configured\n");
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
|
|
|
|
if (IS_ERR(dwc->usb3_generic_phy)) {
|
|
|
|
ret = PTR_ERR(dwc->usb3_generic_phy);
|
|
|
|
if (ret == -ENOSYS || ret == -ENODEV) {
|
|
|
|
dwc->usb3_generic_phy = NULL;
|
|
|
|
} else if (ret == -EPROBE_DEFER) {
|
|
|
|
return ret;
|
|
|
|
} else {
|
|
|
|
dev_err(dev, "no usb3 phy configured\n");
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-04-17 04:08:29 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-04-17 04:13:45 +08:00
|
|
|
static int dwc3_core_init_mode(struct dwc3 *dwc)
|
|
|
|
{
|
|
|
|
struct device *dev = dwc->dev;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
switch (dwc->dr_mode) {
|
|
|
|
case USB_DR_MODE_PERIPHERAL:
|
|
|
|
dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
|
|
|
|
ret = dwc3_gadget_init(dwc);
|
|
|
|
if (ret) {
|
2016-06-10 19:48:38 +08:00
|
|
|
if (ret != -EPROBE_DEFER)
|
|
|
|
dev_err(dev, "failed to initialize gadget\n");
|
2014-04-17 04:13:45 +08:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case USB_DR_MODE_HOST:
|
|
|
|
dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
|
|
|
|
ret = dwc3_host_init(dwc);
|
|
|
|
if (ret) {
|
2016-06-10 19:48:38 +08:00
|
|
|
if (ret != -EPROBE_DEFER)
|
|
|
|
dev_err(dev, "failed to initialize host\n");
|
2014-04-17 04:13:45 +08:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case USB_DR_MODE_OTG:
|
|
|
|
dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
|
|
|
|
ret = dwc3_host_init(dwc);
|
|
|
|
if (ret) {
|
2016-06-10 19:48:38 +08:00
|
|
|
if (ret != -EPROBE_DEFER)
|
|
|
|
dev_err(dev, "failed to initialize host\n");
|
2014-04-17 04:13:45 +08:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = dwc3_gadget_init(dwc);
|
|
|
|
if (ret) {
|
2016-06-10 19:48:38 +08:00
|
|
|
if (ret != -EPROBE_DEFER)
|
|
|
|
dev_err(dev, "failed to initialize gadget\n");
|
2014-04-17 04:13:45 +08:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void dwc3_core_exit_mode(struct dwc3 *dwc)
|
|
|
|
{
|
|
|
|
switch (dwc->dr_mode) {
|
|
|
|
case USB_DR_MODE_PERIPHERAL:
|
|
|
|
dwc3_gadget_exit(dwc);
|
|
|
|
break;
|
|
|
|
case USB_DR_MODE_HOST:
|
|
|
|
dwc3_host_exit(dwc);
|
|
|
|
break;
|
|
|
|
case USB_DR_MODE_OTG:
|
|
|
|
dwc3_host_exit(dwc);
|
|
|
|
dwc3_gadget_exit(dwc);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
/* do nothing */
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-04-17 04:08:29 +08:00
|
|
|
#define DWC3_ALIGN_MASK (16 - 1)
|
|
|
|
|
|
|
|
static int dwc3_probe(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct device *dev = &pdev->dev;
|
|
|
|
struct resource *res;
|
|
|
|
struct dwc3 *dwc;
|
2014-10-28 19:54:26 +08:00
|
|
|
u8 lpm_nyet_threshold;
|
2014-10-31 11:11:12 +08:00
|
|
|
u8 tx_de_emphasis;
|
2014-10-31 11:11:18 +08:00
|
|
|
u8 hird_threshold;
|
2014-04-17 04:08:29 +08:00
|
|
|
|
2014-05-15 20:53:32 +08:00
|
|
|
int ret;
|
2014-04-17 04:08:29 +08:00
|
|
|
|
|
|
|
void __iomem *regs;
|
|
|
|
void *mem;
|
|
|
|
|
|
|
|
mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
|
2014-07-17 11:45:11 +08:00
|
|
|
if (!mem)
|
2014-04-17 04:08:29 +08:00
|
|
|
return -ENOMEM;
|
2014-07-17 11:45:11 +08:00
|
|
|
|
2014-04-17 04:08:29 +08:00
|
|
|
dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
|
|
|
|
dwc->mem = mem;
|
|
|
|
dwc->dev = dev;
|
|
|
|
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
|
|
if (!res) {
|
|
|
|
dev_err(dev, "missing memory resource\n");
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
|
2014-06-04 17:04:52 +08:00
|
|
|
dwc->xhci_resources[0].start = res->start;
|
|
|
|
dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
|
|
|
|
DWC3_XHCI_REGS_END;
|
|
|
|
dwc->xhci_resources[0].flags = res->flags;
|
|
|
|
dwc->xhci_resources[0].name = res->name;
|
|
|
|
|
|
|
|
res->start += DWC3_GLOBALS_REGS_START;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Request memory region but exclude xHCI regs,
|
|
|
|
* since it will be requested by the xhci-plat driver.
|
|
|
|
*/
|
|
|
|
regs = devm_ioremap_resource(dev, res);
|
2014-09-03 04:19:43 +08:00
|
|
|
if (IS_ERR(regs)) {
|
|
|
|
ret = PTR_ERR(regs);
|
|
|
|
goto err0;
|
|
|
|
}
|
2014-06-04 17:04:52 +08:00
|
|
|
|
|
|
|
dwc->regs = regs;
|
|
|
|
dwc->regs_size = resource_size(res);
|
|
|
|
|
2014-10-28 19:54:26 +08:00
|
|
|
/* default to highest possible threshold */
|
|
|
|
lpm_nyet_threshold = 0xff;
|
|
|
|
|
2014-10-31 11:11:12 +08:00
|
|
|
/* default to -3.5dB de-emphasis */
|
|
|
|
tx_de_emphasis = 1;
|
|
|
|
|
2014-10-31 11:11:18 +08:00
|
|
|
/*
|
|
|
|
* default to assert utmi_sleep_n and use maximum allowed HIRD
|
|
|
|
* threshold value of 0b1100
|
|
|
|
*/
|
|
|
|
hird_threshold = 12;
|
|
|
|
|
2015-09-21 16:14:32 +08:00
|
|
|
dwc->maximum_speed = usb_get_maximum_speed(dev);
|
2015-09-21 16:14:34 +08:00
|
|
|
dwc->dr_mode = usb_get_dr_mode(dev);
|
2016-08-16 22:44:38 +08:00
|
|
|
dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
|
2015-09-21 16:14:32 +08:00
|
|
|
|
2015-09-21 16:14:35 +08:00
|
|
|
dwc->has_lpm_erratum = device_property_read_bool(dev,
|
2014-10-28 19:54:26 +08:00
|
|
|
"snps,has-lpm-erratum");
|
2015-09-21 16:14:35 +08:00
|
|
|
device_property_read_u8(dev, "snps,lpm-nyet-threshold",
|
2014-10-28 19:54:26 +08:00
|
|
|
&lpm_nyet_threshold);
|
2015-09-21 16:14:35 +08:00
|
|
|
dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
|
2014-10-31 11:11:18 +08:00
|
|
|
"snps,is-utmi-l1-suspend");
|
2015-09-21 16:14:35 +08:00
|
|
|
device_property_read_u8(dev, "snps,hird-threshold",
|
2014-10-31 11:11:18 +08:00
|
|
|
&hird_threshold);
|
2015-09-21 16:14:35 +08:00
|
|
|
dwc->usb3_lpm_capable = device_property_read_bool(dev,
|
2015-03-09 22:06:12 +08:00
|
|
|
"snps,usb3_lpm_capable");
|
2014-04-17 04:08:29 +08:00
|
|
|
|
2015-09-21 16:14:35 +08:00
|
|
|
dwc->disable_scramble_quirk = device_property_read_bool(dev,
|
2014-10-28 19:54:25 +08:00
|
|
|
"snps,disable_scramble_quirk");
|
2015-09-21 16:14:35 +08:00
|
|
|
dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
|
2014-10-28 19:54:27 +08:00
|
|
|
"snps,u2exit_lfps_quirk");
|
2015-09-21 16:14:35 +08:00
|
|
|
dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
|
2014-10-28 19:54:28 +08:00
|
|
|
"snps,u2ss_inp3_quirk");
|
2015-09-21 16:14:35 +08:00
|
|
|
dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
|
2014-10-28 19:54:29 +08:00
|
|
|
"snps,req_p1p2p3_quirk");
|
2015-09-21 16:14:35 +08:00
|
|
|
dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
|
2014-10-28 19:54:30 +08:00
|
|
|
"snps,del_p1p2p3_quirk");
|
2015-09-21 16:14:35 +08:00
|
|
|
dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
|
2014-10-28 19:54:31 +08:00
|
|
|
"snps,del_phy_power_chg_quirk");
|
2015-09-21 16:14:35 +08:00
|
|
|
dwc->lfps_filter_quirk = device_property_read_bool(dev,
|
2014-10-28 19:54:32 +08:00
|
|
|
"snps,lfps_filter_quirk");
|
2015-09-21 16:14:35 +08:00
|
|
|
dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
|
2014-10-28 19:54:33 +08:00
|
|
|
"snps,rx_detect_poll_quirk");
|
2015-09-21 16:14:35 +08:00
|
|
|
dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
|
2014-10-31 11:11:13 +08:00
|
|
|
"snps,dis_u3_susphy_quirk");
|
2015-09-21 16:14:35 +08:00
|
|
|
dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
|
2014-10-31 11:11:14 +08:00
|
|
|
"snps,dis_u2_susphy_quirk");
|
2015-10-03 11:30:57 +08:00
|
|
|
dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
|
|
|
|
"snps,dis_enblslpm_quirk");
|
2016-03-14 17:10:50 +08:00
|
|
|
dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
|
|
|
|
"snps,dis_rxdet_inp3_quirk");
|
2016-08-16 22:44:37 +08:00
|
|
|
dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
|
|
|
|
"snps,dis-u2-freeclk-exists-quirk");
|
2014-10-31 11:11:12 +08:00
|
|
|
|
2015-09-21 16:14:35 +08:00
|
|
|
dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
|
2014-10-31 11:11:12 +08:00
|
|
|
"snps,tx_de_emphasis_quirk");
|
2015-09-21 16:14:35 +08:00
|
|
|
device_property_read_u8(dev, "snps,tx_de_emphasis",
|
2014-10-31 11:11:12 +08:00
|
|
|
&tx_de_emphasis);
|
2015-09-21 16:14:35 +08:00
|
|
|
device_property_read_string(dev, "snps,hsphy_interface",
|
|
|
|
&dwc->hsphy_interface);
|
|
|
|
device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
|
2016-05-16 15:42:23 +08:00
|
|
|
&dwc->fladj);
|
2015-09-21 16:14:35 +08:00
|
|
|
|
2014-10-28 19:54:26 +08:00
|
|
|
dwc->lpm_nyet_threshold = lpm_nyet_threshold;
|
2014-10-31 11:11:12 +08:00
|
|
|
dwc->tx_de_emphasis = tx_de_emphasis;
|
2014-10-28 19:54:26 +08:00
|
|
|
|
2014-10-31 11:11:18 +08:00
|
|
|
dwc->hird_threshold = hird_threshold
|
|
|
|
| (dwc->is_utmi_l1_suspend << 4);
|
|
|
|
|
2015-05-13 20:26:45 +08:00
|
|
|
platform_set_drvdata(pdev, dwc);
|
2015-05-13 20:26:46 +08:00
|
|
|
dwc3_cache_hwparams(dwc);
|
2015-05-13 20:26:45 +08:00
|
|
|
|
2014-04-17 04:08:29 +08:00
|
|
|
ret = dwc3_core_get_phy(dwc);
|
|
|
|
if (ret)
|
2014-09-03 04:19:43 +08:00
|
|
|
goto err0;
|
2014-04-17 04:08:29 +08:00
|
|
|
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
spin_lock_init(&dwc->lock);
|
|
|
|
|
2014-09-24 16:00:38 +08:00
|
|
|
if (!dev->dma_mask) {
|
|
|
|
dev->dma_mask = dev->parent->dma_mask;
|
|
|
|
dev->dma_parms = dev->parent->dma_parms;
|
|
|
|
dma_set_coherent_mask(dev, dev->parent->coherent_dma_mask);
|
|
|
|
}
|
2013-03-07 21:21:43 +08:00
|
|
|
|
2016-05-16 18:14:48 +08:00
|
|
|
pm_runtime_set_active(dev);
|
|
|
|
pm_runtime_use_autosuspend(dev);
|
|
|
|
pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY);
|
2012-02-15 17:27:55 +08:00
|
|
|
pm_runtime_enable(dev);
|
2016-06-10 19:38:02 +08:00
|
|
|
ret = pm_runtime_get_sync(dev);
|
|
|
|
if (ret < 0)
|
|
|
|
goto err1;
|
|
|
|
|
2012-02-15 17:27:55 +08:00
|
|
|
pm_runtime_forbid(dev);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
2012-10-11 18:54:36 +08:00
|
|
|
ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(dwc->dev, "failed to allocate event buffers\n");
|
|
|
|
ret = -ENOMEM;
|
2016-06-10 19:38:02 +08:00
|
|
|
goto err2;
|
2012-10-11 18:54:36 +08:00
|
|
|
}
|
|
|
|
|
2016-06-07 17:55:19 +08:00
|
|
|
if (IS_ENABLED(CONFIG_USB_DWC3_HOST) &&
|
|
|
|
(dwc->dr_mode == USB_DR_MODE_OTG ||
|
|
|
|
dwc->dr_mode == USB_DR_MODE_UNKNOWN))
|
2014-02-26 04:00:13 +08:00
|
|
|
dwc->dr_mode = USB_DR_MODE_HOST;
|
2016-06-07 17:55:19 +08:00
|
|
|
else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET) &&
|
|
|
|
(dwc->dr_mode == USB_DR_MODE_OTG ||
|
|
|
|
dwc->dr_mode == USB_DR_MODE_UNKNOWN))
|
2014-02-26 04:00:13 +08:00
|
|
|
dwc->dr_mode = USB_DR_MODE_PERIPHERAL;
|
|
|
|
|
|
|
|
if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
|
|
|
|
dwc->dr_mode = USB_DR_MODE_OTG;
|
|
|
|
|
2016-05-16 15:49:01 +08:00
|
|
|
ret = dwc3_alloc_scratch_buffers(dwc);
|
|
|
|
if (ret)
|
2016-06-10 19:38:02 +08:00
|
|
|
goto err3;
|
2016-05-16 15:49:01 +08:00
|
|
|
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
ret = dwc3_core_init(dwc);
|
|
|
|
if (ret) {
|
2012-02-15 17:27:55 +08:00
|
|
|
dev_err(dev, "failed to initialize core\n");
|
2016-06-10 19:38:02 +08:00
|
|
|
goto err4;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
}
|
|
|
|
|
2016-02-20 09:31:01 +08:00
|
|
|
/* Check the maximum_speed parameter */
|
|
|
|
switch (dwc->maximum_speed) {
|
|
|
|
case USB_SPEED_LOW:
|
|
|
|
case USB_SPEED_FULL:
|
|
|
|
case USB_SPEED_HIGH:
|
|
|
|
case USB_SPEED_SUPER:
|
|
|
|
case USB_SPEED_SUPER_PLUS:
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
dev_err(dev, "invalid maximum_speed parameter %d\n",
|
|
|
|
dwc->maximum_speed);
|
|
|
|
/* fall through */
|
|
|
|
case USB_SPEED_UNKNOWN:
|
|
|
|
/* default to superspeed */
|
2016-02-06 09:08:59 +08:00
|
|
|
dwc->maximum_speed = USB_SPEED_SUPER;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* default to superspeed plus if we are capable.
|
|
|
|
*/
|
|
|
|
if (dwc3_is_usb31(dwc) &&
|
|
|
|
(DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
|
|
|
|
DWC3_GHWPARAMS3_SSPHY_IFC_GEN2))
|
|
|
|
dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
|
2016-02-20 09:31:01 +08:00
|
|
|
|
|
|
|
break;
|
2016-02-06 09:08:59 +08:00
|
|
|
}
|
|
|
|
|
2014-04-17 04:13:45 +08:00
|
|
|
ret = dwc3_core_init_mode(dwc);
|
|
|
|
if (ret)
|
2016-06-10 19:38:02 +08:00
|
|
|
goto err5;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
2016-04-12 19:10:18 +08:00
|
|
|
dwc3_debugfs_init(dwc);
|
2016-05-16 18:14:48 +08:00
|
|
|
pm_runtime_put(dev);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
2016-06-10 19:38:02 +08:00
|
|
|
err5:
|
2016-05-16 15:49:01 +08:00
|
|
|
dwc3_event_buffers_cleanup(dwc);
|
2014-03-03 19:38:11 +08:00
|
|
|
|
2016-06-10 19:38:02 +08:00
|
|
|
err4:
|
2016-05-16 15:49:01 +08:00
|
|
|
dwc3_free_scratch_buffers(dwc);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
2016-06-10 19:38:02 +08:00
|
|
|
err3:
|
2012-10-11 18:54:36 +08:00
|
|
|
dwc3_free_event_buffers(dwc);
|
2015-05-13 20:26:51 +08:00
|
|
|
dwc3_ulpi_exit(dwc);
|
2012-10-11 18:54:36 +08:00
|
|
|
|
2016-06-10 19:38:02 +08:00
|
|
|
err2:
|
|
|
|
pm_runtime_allow(&pdev->dev);
|
|
|
|
|
|
|
|
err1:
|
|
|
|
pm_runtime_put_sync(&pdev->dev);
|
|
|
|
pm_runtime_disable(&pdev->dev);
|
|
|
|
|
2014-09-03 04:19:43 +08:00
|
|
|
err0:
|
|
|
|
/*
|
|
|
|
* restore res->start back to its original value so that, in case the
|
|
|
|
* probe is deferred, we don't end up getting error in request the
|
|
|
|
* memory region the next time probe is called.
|
|
|
|
*/
|
|
|
|
res->start -= DWC3_GLOBALS_REGS_START;
|
|
|
|
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2012-11-20 02:26:20 +08:00
|
|
|
static int dwc3_remove(struct platform_device *pdev)
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
{
|
|
|
|
struct dwc3 *dwc = platform_get_drvdata(pdev);
|
2014-09-03 04:19:43 +08:00
|
|
|
struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
|
|
|
2016-05-16 18:14:48 +08:00
|
|
|
pm_runtime_get_sync(&pdev->dev);
|
2014-09-03 04:19:43 +08:00
|
|
|
/*
|
|
|
|
* restore res->start back to its original value so that, in case the
|
|
|
|
* probe is deferred, we don't end up getting error in request the
|
|
|
|
* memory region the next time probe is called.
|
|
|
|
*/
|
|
|
|
res->start -= DWC3_GLOBALS_REGS_START;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
2014-09-04 05:13:37 +08:00
|
|
|
dwc3_debugfs_exit(dwc);
|
|
|
|
dwc3_core_exit_mode(dwc);
|
2013-01-25 11:00:54 +08:00
|
|
|
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
dwc3_core_exit(dwc);
|
2015-05-13 20:26:51 +08:00
|
|
|
dwc3_ulpi_exit(dwc);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
2013-10-11 21:34:28 +08:00
|
|
|
pm_runtime_put_sync(&pdev->dev);
|
2016-05-16 18:14:48 +08:00
|
|
|
pm_runtime_allow(&pdev->dev);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
pm_runtime_disable(&pdev->dev);
|
|
|
|
|
2016-05-16 18:14:48 +08:00
|
|
|
dwc3_free_event_buffers(dwc);
|
|
|
|
dwc3_free_scratch_buffers(dwc);
|
|
|
|
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-05-16 18:14:48 +08:00
|
|
|
#ifdef CONFIG_PM
|
|
|
|
static int dwc3_suspend_common(struct dwc3 *dwc)
|
2012-04-30 19:56:33 +08:00
|
|
|
{
|
2016-05-16 18:14:48 +08:00
|
|
|
unsigned long flags;
|
2012-04-30 19:56:33 +08:00
|
|
|
|
2013-07-06 20:52:49 +08:00
|
|
|
switch (dwc->dr_mode) {
|
|
|
|
case USB_DR_MODE_PERIPHERAL:
|
|
|
|
case USB_DR_MODE_OTG:
|
2016-05-16 18:14:48 +08:00
|
|
|
spin_lock_irqsave(&dwc->lock, flags);
|
2012-04-30 19:56:33 +08:00
|
|
|
dwc3_gadget_suspend(dwc);
|
2016-05-16 18:14:48 +08:00
|
|
|
spin_unlock_irqrestore(&dwc->lock, flags);
|
2016-05-16 15:52:58 +08:00
|
|
|
break;
|
2013-07-06 20:52:49 +08:00
|
|
|
case USB_DR_MODE_HOST:
|
2012-04-30 19:56:33 +08:00
|
|
|
default:
|
2016-05-16 15:52:58 +08:00
|
|
|
/* do nothing */
|
2012-04-30 19:56:33 +08:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2016-05-16 15:52:58 +08:00
|
|
|
dwc3_core_exit(dwc);
|
2016-04-11 22:12:34 +08:00
|
|
|
|
2012-04-30 19:56:33 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-05-16 18:14:48 +08:00
|
|
|
static int dwc3_resume_common(struct dwc3 *dwc)
|
2012-04-30 19:56:33 +08:00
|
|
|
{
|
2016-05-16 18:14:48 +08:00
|
|
|
unsigned long flags;
|
2014-03-03 19:38:11 +08:00
|
|
|
int ret;
|
2012-04-30 19:56:33 +08:00
|
|
|
|
2016-05-16 15:52:58 +08:00
|
|
|
ret = dwc3_core_init(dwc);
|
|
|
|
if (ret)
|
2016-04-11 22:12:34 +08:00
|
|
|
return ret;
|
|
|
|
|
2013-07-06 20:52:49 +08:00
|
|
|
switch (dwc->dr_mode) {
|
|
|
|
case USB_DR_MODE_PERIPHERAL:
|
|
|
|
case USB_DR_MODE_OTG:
|
2016-05-16 18:14:48 +08:00
|
|
|
spin_lock_irqsave(&dwc->lock, flags);
|
2012-04-30 19:56:33 +08:00
|
|
|
dwc3_gadget_resume(dwc);
|
2016-05-16 18:14:48 +08:00
|
|
|
spin_unlock_irqrestore(&dwc->lock, flags);
|
2012-04-30 19:56:33 +08:00
|
|
|
/* FALLTHROUGH */
|
2013-07-06 20:52:49 +08:00
|
|
|
case USB_DR_MODE_HOST:
|
2012-04-30 19:56:33 +08:00
|
|
|
default:
|
|
|
|
/* do nothing */
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2016-05-16 18:14:48 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int dwc3_runtime_checks(struct dwc3 *dwc)
|
|
|
|
{
|
|
|
|
switch (dwc->dr_mode) {
|
|
|
|
case USB_DR_MODE_PERIPHERAL:
|
|
|
|
case USB_DR_MODE_OTG:
|
|
|
|
if (dwc->connected)
|
|
|
|
return -EBUSY;
|
|
|
|
break;
|
|
|
|
case USB_DR_MODE_HOST:
|
|
|
|
default:
|
|
|
|
/* do nothing */
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int dwc3_runtime_suspend(struct device *dev)
|
|
|
|
{
|
|
|
|
struct dwc3 *dwc = dev_get_drvdata(dev);
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
if (dwc3_runtime_checks(dwc))
|
|
|
|
return -EBUSY;
|
|
|
|
|
|
|
|
ret = dwc3_suspend_common(dwc);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
device_init_wakeup(dev, true);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int dwc3_runtime_resume(struct device *dev)
|
|
|
|
{
|
|
|
|
struct dwc3 *dwc = dev_get_drvdata(dev);
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
device_init_wakeup(dev, false);
|
|
|
|
|
|
|
|
ret = dwc3_resume_common(dwc);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
switch (dwc->dr_mode) {
|
|
|
|
case USB_DR_MODE_PERIPHERAL:
|
|
|
|
case USB_DR_MODE_OTG:
|
|
|
|
dwc3_gadget_process_pending_events(dwc);
|
|
|
|
break;
|
|
|
|
case USB_DR_MODE_HOST:
|
|
|
|
default:
|
|
|
|
/* do nothing */
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
pm_runtime_mark_last_busy(dev);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int dwc3_runtime_idle(struct device *dev)
|
|
|
|
{
|
|
|
|
struct dwc3 *dwc = dev_get_drvdata(dev);
|
|
|
|
|
|
|
|
switch (dwc->dr_mode) {
|
|
|
|
case USB_DR_MODE_PERIPHERAL:
|
|
|
|
case USB_DR_MODE_OTG:
|
|
|
|
if (dwc3_runtime_checks(dwc))
|
|
|
|
return -EBUSY;
|
|
|
|
break;
|
|
|
|
case USB_DR_MODE_HOST:
|
|
|
|
default:
|
|
|
|
/* do nothing */
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
pm_runtime_mark_last_busy(dev);
|
|
|
|
pm_runtime_autosuspend(dev);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
#endif /* CONFIG_PM */
|
|
|
|
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
|
|
static int dwc3_suspend(struct device *dev)
|
|
|
|
{
|
|
|
|
struct dwc3 *dwc = dev_get_drvdata(dev);
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = dwc3_suspend_common(dwc);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
pinctrl_pm_select_sleep_state(dev);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int dwc3_resume(struct device *dev)
|
|
|
|
{
|
|
|
|
struct dwc3 *dwc = dev_get_drvdata(dev);
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
pinctrl_pm_select_default_state(dev);
|
|
|
|
|
|
|
|
ret = dwc3_resume_common(dwc);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2012-04-30 19:56:33 +08:00
|
|
|
pm_runtime_disable(dev);
|
|
|
|
pm_runtime_set_active(dev);
|
|
|
|
pm_runtime_enable(dev);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
2016-05-09 20:27:01 +08:00
|
|
|
#endif /* CONFIG_PM_SLEEP */
|
2012-04-30 19:56:33 +08:00
|
|
|
|
|
|
|
static const struct dev_pm_ops dwc3_dev_pm_ops = {
|
|
|
|
SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
|
2016-05-16 18:14:48 +08:00
|
|
|
SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume,
|
|
|
|
dwc3_runtime_idle)
|
2012-04-30 19:56:33 +08:00
|
|
|
};
|
|
|
|
|
2013-01-25 19:06:53 +08:00
|
|
|
#ifdef CONFIG_OF
|
|
|
|
static const struct of_device_id of_dwc3_match[] = {
|
2013-07-03 02:20:24 +08:00
|
|
|
{
|
|
|
|
.compatible = "snps,dwc3"
|
|
|
|
},
|
2013-01-25 19:06:53 +08:00
|
|
|
{
|
|
|
|
.compatible = "synopsys,dwc3"
|
|
|
|
},
|
|
|
|
{ },
|
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, of_dwc3_match);
|
|
|
|
#endif
|
|
|
|
|
2014-09-25 15:57:02 +08:00
|
|
|
#ifdef CONFIG_ACPI
|
|
|
|
|
|
|
|
#define ACPI_ID_INTEL_BSW "808622B7"
|
|
|
|
|
|
|
|
static const struct acpi_device_id dwc3_acpi_match[] = {
|
|
|
|
{ ACPI_ID_INTEL_BSW, 0 },
|
|
|
|
{ },
|
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
|
|
|
|
#endif
|
|
|
|
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
static struct platform_driver dwc3_driver = {
|
|
|
|
.probe = dwc3_probe,
|
2012-11-20 02:21:08 +08:00
|
|
|
.remove = dwc3_remove,
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
.driver = {
|
|
|
|
.name = "dwc3",
|
2013-01-25 19:06:53 +08:00
|
|
|
.of_match_table = of_match_ptr(of_dwc3_match),
|
2014-09-25 15:57:02 +08:00
|
|
|
.acpi_match_table = ACPI_PTR(dwc3_acpi_match),
|
2016-05-09 20:27:01 +08:00
|
|
|
.pm = &dwc3_dev_pm_ops,
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2012-02-28 19:57:20 +08:00
|
|
|
module_platform_driver(dwc3_driver);
|
|
|
|
|
2011-10-20 01:39:50 +08:00
|
|
|
MODULE_ALIAS("platform:dwc3");
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
|
2013-06-30 19:15:11 +08:00
|
|
|
MODULE_LICENSE("GPL v2");
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
|