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linux_old1/drivers/reset/Kconfig

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reset: Add reset controller API This adds a simple API for devices to request being reset by separate reset controller hardware and implements the reset signal device tree binding. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Shawn Guo <shawn.guo@linaro.org> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Pavel Machek <pavel@ucw.cz>
2012-11-20 00:23:13 +08:00
config ARCH_HAS_RESET_CONTROLLER
bool
menuconfig RESET_CONTROLLER
bool "Reset Controller Support"
default y if ARCH_HAS_RESET_CONTROLLER
help
Generic Reset Controller support.
This framework is designed to abstract reset handling of devices
via GPIOs or SoC-internal reset controller modules.
If unsure, say no.
drivers: reset: STi SoC system configuration reset controller support This patch adds a reset controller implementation for STMicroelectronics STi family SoCs; it allows a group of related reset like controls found in multiple system configuration registers to be represented by a single controller device. System configuration registers are accessed through the regmap framework and the mfd/syscon driver. The implementation optionally supports waiting for the reset action to be acknowledged in a separate status register and supports both active high and active low reset lines. These properties are common across all the reset channels in a specific reset controller instance, hence all channels in a paritcular controller are expected to behave in the same way. Signed-off-by: Stephen Gallimore <stephen.gallimore@st.com> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com> Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
2013-08-07 22:53:12 +08:00
reset: fix Kconfig menu to include reset drivers in sub-menu In "make menuconfig", reset drivers are currently lined up together with the reset sub-system menu, like this: -*- Reset Controller Support ---- < > Hi6220 Reset Driver (It also means, the menu "Reset Controller Support" is always empty.) "Hi6220 Reset Driver" should go into the sub-menu of the "Reset Controller Support". Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-05-03 14:29:52 +08:00
if RESET_CONTROLLER
reset: Add Altera Arria10 SR Reset Controller This patch adds the reset controller functionality for Peripheral PHYs to the Arria10 System Resource Chip. Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2017-02-23 01:10:17 +08:00
config RESET_A10SR
tristate "Altera Arria10 System Resource Reset"
depends on MFD_ALTERA_A10SR
help
This option enables support for the external reset functions for
peripheral PHYs on the Altera Arria10 System Resource Chip.
reset: ath79: add driver Kconfig option Visible only if COMPILE_TEST is enabled, this allows to include the driver in build tests. Acked-by: Aban Bedel <albeu@free.fr> Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-07-28 21:30:08 +08:00
config RESET_ATH79
bool "AR71xx Reset Driver" if COMPILE_TEST
default ATH79
help
This enables the ATH79 reset controller driver that supports the
AR71xx SoC reset controller.
ARC: reset: introduce AXS10x reset driver ARC AXS10x boards support custom IP-block which allows to control reset signals of selected peripherals. For example DW GMAC, etc... This block is controlled via memory-mapped register (AKA CREG) which represents up-to 32 reset lines. This regiter is self-clearing so we don't need to deassert line after reset. As of today only the following lines are used: - DW GMAC - line 5 Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2017-09-14 22:28:42 +08:00
config RESET_AXS10X
bool "AXS10x Reset Driver" if COMPILE_TEST
default ARC_PLAT_AXS10X
help
This enables the reset controller driver for AXS10x.
reset: berlin: add driver Kconfig option Visible only if COMPILE_TEST is enabled, this allows to include the driver in build tests. Cc: Antoine Tenart <antoine.tenart@free-electrons.com> Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-07-28 21:31:12 +08:00
config RESET_BERLIN
bool "Berlin Reset Driver" if COMPILE_TEST
default ARCH_BERLIN
help
This enables the reset controller driver for Marvell Berlin SoCs.
reset: Add Broadcom STB SW_INIT reset controller driver Add support for resetting blocks through the Linux reset controller subsystem when reset lines are provided through a SW_INIT-style reset controller on Broadcom STB SoCs. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2019-01-24 06:54:36 +08:00
config RESET_BRCMSTB
tristate "Broadcom STB reset controller"
depends on ARCH_BRCMSTB || COMPILE_TEST
default ARCH_BRCMSTB
help
This enables the reset controller driver for Broadcom STB SoCs using
a SUN_TOP_CTRL_SW_INIT style controller.
ARC: reset: remove the misleading v1 suffix all over There is no plan yet to do a v2 board. And even if we were to do it only some IPs would actually change, so it be best to add suffixes at that point, not now ! Signed-off-by: Vineet Gupta <vgupta@synopsys.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2017-09-01 02:06:07 +08:00
config RESET_HSDK
bool "Synopsys HSDK Reset Driver"
ARC: reset: Only build on archs that have IOMEM This avoids the error: drivers/reset/reset-hsdk-v1.o: In function `hsdkv1_reset_probe': /home/thomas/git/linux/drivers/reset/reset-hsdk-v1.c:101: undefined reference to `devm_ioremap_resource' collect2: error: ld returned 1 exit status Signed-off-by: Thomas Meyer <thomas@m3y3r.de> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2017-09-09 12:02:46 +08:00
depends on HAS_IOMEM
reset: Restrict RESET_HSDK to ARC_SOC_HSDK or COMPILE_TEST The HSDK reset driver is only useful when building for an ARC HSDK platform. While at it, drop the "default n", as that is the default. Fixes: e0be864f14240cb1 ("ARC: reset: introduce HSDKv1 reset driver") Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> [p.zabel@pengutronix.de: rebased, renamed RESET_HSDK_V1 to RESET_HSDK] Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2017-09-11 20:22:08 +08:00
depends on ARC_SOC_HSDK || COMPILE_TEST
ARC: reset: introduce HSDKv1 reset driver The HSDK v1 periphery IPs can be reset by accessing some registers from the CGU block. The list of available reset lines is documented in the DT bindings. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2017-07-20 02:45:11 +08:00
help
ARC: reset: remove the misleading v1 suffix all over There is no plan yet to do a v2 board. And even if we were to do it only some IPs would actually change, so it be best to add suffixes at that point, not now ! Signed-off-by: Vineet Gupta <vgupta@synopsys.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2017-09-01 02:06:07 +08:00
This enables the reset controller driver for HSDK board.
ARC: reset: introduce HSDKv1 reset driver The HSDK v1 periphery IPs can be reset by accessing some registers from the CGU block. The list of available reset lines is documented in the DT bindings. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2017-07-20 02:45:11 +08:00
reset: Add i.MX7 SRC reset driver Add reset controller driver exposing various reset faculties, implemented by System Reset Controller IP block. Cc: Lucas Stach <l.stach@pengutronix.de> Cc: Mark Rutland <mark.rutland@arm.com> Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2017-02-22 00:13:31 +08:00
config RESET_IMX7
reset: imx7: Add support for i.MX8MQ IP block variant Add bits and pieces needed to support IP block variant found on i.MX8MQ SoCs. Cc: p.zabel@pengutronix.de Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: cphealy@gmail.com Cc: l.stach@pengutronix.de Cc: Leonard Crestez <leonard.crestez@nxp.com> Cc: "A.s. Dong" <aisheng.dong@nxp.com> Cc: Richard Zhu <hongxing.zhu@nxp.com> Cc: Rob Herring <robh@kernel.org> Cc: devicetree@vger.kernel.org Cc: linux-imx@nxp.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> [p.zabel@pengutronix.de: fixed whitespace alignment] Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2019-01-22 10:10:43 +08:00
bool "i.MX7/8 Reset Driver" if COMPILE_TEST
reset: imx7: add 'depends on HAS_IOMEM' to fix unmet dependency This config select's MFD_SYSCON, but does not depend on HAS_IOMEM. Compile testing on architecture without HAS_IOMEM causes "unmet direct dependencies" in Kconfig phase. Detected by "make ARCH=score allyesconfig". Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2018-03-06 19:15:11 +08:00
depends on HAS_IOMEM
reset: imx7: Add support for i.MX8MQ IP block variant Add bits and pieces needed to support IP block variant found on i.MX8MQ SoCs. Cc: p.zabel@pengutronix.de Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: cphealy@gmail.com Cc: l.stach@pengutronix.de Cc: Leonard Crestez <leonard.crestez@nxp.com> Cc: "A.s. Dong" <aisheng.dong@nxp.com> Cc: Richard Zhu <hongxing.zhu@nxp.com> Cc: Rob Herring <robh@kernel.org> Cc: devicetree@vger.kernel.org Cc: linux-imx@nxp.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> [p.zabel@pengutronix.de: fixed whitespace alignment] Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2019-01-22 10:10:43 +08:00
default SOC_IMX7D || (ARM64 && ARCH_MXC)
reset: Add i.MX7 SRC reset driver Add reset controller driver exposing various reset faculties, implemented by System Reset Controller IP block. Cc: Lucas Stach <l.stach@pengutronix.de> Cc: Mark Rutland <mark.rutland@arm.com> Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2017-02-22 00:13:31 +08:00
select MFD_SYSCON
help
This enables the reset controller driver for i.MX7 SoCs.
reset: Add a reset controller driver for the Lantiq XWAY based SoCs The reset controllers (on xRX200 and newer SoCs have two of them) are provided by the RCU module. This was initially implemented as a simple reset controller. However, the RCU module provides more functionality (ethernet GPHYs, USB PHY, etc.), which makes it a MFD device. The old reset controller driver implementation from arch/mips/lantiq/xway/reset.c did not honor this fact. For some devices the request and the status bits are different. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Rob Herring <robh@kernel.org> Cc: john@phrozen.org Cc: kishon@ti.com Cc: mark.rutland@arm.com Cc: linux-mips@linux-mips.org Cc: linux-mtd@lists.infradead.org Cc: linux-watchdog@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-spi@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/17125/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-08-20 06:18:17 +08:00
config RESET_LANTIQ
bool "Lantiq XWAY Reset Driver" if COMPILE_TEST
default SOC_TYPE_XWAY
help
This enables the reset controller driver for Lantiq / Intel XWAY SoCs.
reset: lpc18xx: add driver Kconfig option Visible only if COMPILE_TEST is enabled, this allows to include the driver in build tests. Acked-by: Joachim Eastwood <manabian@gmail.com> Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-07-28 21:32:01 +08:00
config RESET_LPC18XX
bool "LPC18xx/43xx Reset Driver" if COMPILE_TEST
default ARCH_LPC18XX
help
This enables the reset controller driver for NXP LPC18xx/43xx SoCs.
reset: meson: add driver Kconfig option Visible only if COMPILE_TEST is enabled, this allows to include the driver in build tests. Acked-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-07-28 21:32:36 +08:00
config RESET_MESON
bool "Meson Reset Driver" if COMPILE_TEST
default ARCH_MESON
help
This enables the reset driver for Amlogic Meson SoCs.
reset: meson: add meson audio arb driver The Amlogic Audio ARB is a simple device which enables or disables the access of Audio FIFOs to DDR on AXG based SoC. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2018-07-20 23:26:33 +08:00
config RESET_MESON_AUDIO_ARB
tristate "Meson Audio Memory Arbiter Reset Driver"
depends on ARCH_MESON || COMPILE_TEST
help
This enables the reset driver for Audio Memory Arbiter of
Amlogic's A113 based SoCs
reset: Add Oxford Semiconductor Reset Controller driver Add System reset controller driver for Oxford Semiconductor OXNAS SoC Family. CC: Ma Haijun <mahaijuns@gmail.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-04-01 22:16:13 +08:00
config RESET_OXNAS
bool
reset: pistachio: add driver Kconfig option Visible only if COMPILE_TEST is enabled, this allows to include the driver in build tests. Cc: Damien Horsley <Damien.Horsley@imgtec.com> Acked-by: James Hartley <james.hartley@imgtec.com> Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-07-28 21:33:07 +08:00
config RESET_PISTACHIO
bool "Pistachio Reset Driver" if COMPILE_TEST
default MACH_PISTACHIO
help
This enables the reset driver for ImgTec Pistachio SoCs.
reset: qcom: AOSS (always on subsystem) reset controller Add reset controller driver for Qualcomm SDM845 SoC to control reset signals provided by AOSS for Modem, Venus ADSP, GPU, Camera, Wireless, Display subsystem Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2018-06-27 22:24:43 +08:00
config RESET_QCOM_AOSS
bool "Qcom AOSS Reset Driver"
depends on ARCH_QCOM || COMPILE_TEST
help
This enables the AOSS (always on subsystem) reset driver
for Qualcomm SDM845 SoCs. Say Y if you want to control
reset signals provided by AOSS for Modem, Venus, ADSP,
GPU, Camera, Wireless, Display subsystem. Otherwise, say N.
reset: qcom: PDC Global (Power Domain Controller) reset controller Add reset controller for SDM845 SoCs to control reset signals provided by PDC Global for Modem, Compute, Display, GPU, Debug, AOP, Sensors, Audio, SP and APPS Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2018-08-30 03:12:11 +08:00
config RESET_QCOM_PDC
tristate "Qualcomm PDC Reset Driver"
depends on ARCH_QCOM || COMPILE_TEST
help
This enables the PDC (Power Domain Controller) reset driver
for Qualcomm Technologies Inc SDM845 SoCs. Say Y if you want
to control reset signals provided by PDC for Modem, Compute,
Display, GPU, Debug, AOP, Sensors, Audio, SP and APPS.
reset: add reset-simple to unify socfpga, stm32, sunxi, and zx2967 Copy reusable parts from the sunxi driver, to add a driver for simple reset controllers with reset lines that can be controlled by toggling bits in exclusive, contiguous register ranges using read-modify-write cycles under a spinlock. The following patches will replace compatible reset drivers with reset-simple, extending it where necessary. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Alexandru Gagniuc <alex.g@adaptrum.com> Reviewed-by: Chen-Yu Tsai <wens@csie.org>
2017-08-11 18:58:43 +08:00
config RESET_SIMPLE
bool "Simple Reset Controller Driver" if COMPILE_TEST
reset: socfpga: add an early reset driver for SoCFPGA Create a separate reset driver that uses the reset operations in reset-simple. The reset driver for the SoCFPGA platform needs to register early in order to be able bring online timers that needed early in the kernel bootup. We do not need this early reset driver for Stratix10, because on arm64, Linux does not need the timers are that in reset. Linux is able to run just fine with the internal armv8 timer. Thus, we use a new binding "altr,stratix10-rst-mgr" for the Stratix10 platform. The Stratix10 platform will continue to use the reset-simple platform driver, while the 32-bit platforms(Cyclone5/Arria5/Arria10) will use the early reset driver. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> [p.zabel@pengutronix.de: fixed socfpga of_device_id in reset-simple] Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2018-11-14 02:50:48 +08:00
default ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARCH_ASPEED
reset: add reset-simple to unify socfpga, stm32, sunxi, and zx2967 Copy reusable parts from the sunxi driver, to add a driver for simple reset controllers with reset lines that can be controlled by toggling bits in exclusive, contiguous register ranges using read-modify-write cycles under a spinlock. The following patches will replace compatible reset drivers with reset-simple, extending it where necessary. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Alexandru Gagniuc <alex.g@adaptrum.com> Reviewed-by: Chen-Yu Tsai <wens@csie.org>
2017-08-11 18:58:43 +08:00
help
This enables a simple reset controller driver for reset lines that
that can be asserted and deasserted by toggling bits in a contiguous,
exclusive register space.
reset: simple: Enable for ASPEED systems ASPEED BMC SoCs have a reset controller in the LPC IP that can be controlled using this driver to release the UARTs from reset. No special configuration is required, so only the compatible string is added. Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2018-02-20 09:43:29 +08:00
Currently this driver supports:
- Altera SoCFPGAs
- ASPEED BMC SoCs
- RCC reset controller in STM32 MCUs
- Allwinner SoCs
- ZTE's zx2967 family
reset: stm32: add driver Kconfig option Visible only if COMPILE_TEST is enabled, this allows to include the driver in build tests. Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Gabriel Fernandez <gabriel.fernandez@st.com> Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-07-28 21:34:15 +08:00
reset: stm32mp1: Enable stm32mp1 reset driver stm32mp1 RCC IP 1 has a reset SET register and a reset CLEAR register. Writing '0' on reset SET register has no effect Writing '1' on reset SET register activates the reset of the corresponding peripheral Writing '0' on reset CLEAR register has no effect Writing '1' on reset CLEAR register releases the reset of the corresponding peripheral See Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.txt Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2018-03-19 15:25:51 +08:00
config RESET_STM32MP157
bool "STM32MP157 Reset Driver" if COMPILE_TEST
default MACH_STM32MP157
help
This enables the RCC reset controller driver for STM32 MPUs.
reset: socfpga: add an early reset driver for SoCFPGA Create a separate reset driver that uses the reset operations in reset-simple. The reset driver for the SoCFPGA platform needs to register early in order to be able bring online timers that needed early in the kernel bootup. We do not need this early reset driver for Stratix10, because on arm64, Linux does not need the timers are that in reset. Linux is able to run just fine with the internal armv8 timer. Thus, we use a new binding "altr,stratix10-rst-mgr" for the Stratix10 platform. The Stratix10 platform will continue to use the reset-simple platform driver, while the 32-bit platforms(Cyclone5/Arria5/Arria10) will use the early reset driver. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> [p.zabel@pengutronix.de: fixed socfpga of_device_id in reset-simple] Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2018-11-14 02:50:48 +08:00
config RESET_SOCFPGA
bool "SoCFPGA Reset Driver" if COMPILE_TEST && !ARCH_SOCFPGA
default ARCH_SOCFPGA
select RESET_SIMPLE
help
This enables the reset driver for the SoCFPGA ARMv7 platforms. This
driver gets initialized early during platform init calls.
reset: sunxi: add driver Kconfig option Visible only if COMPILE_TEST is enabled, this allows to include the driver in build tests. Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-08-09 15:28:44 +08:00
config RESET_SUNXI
bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI
default ARCH_SUNXI
reset: sunxi: use reset-simple driver Use the newly created copies in the reset-simple driver to replace the sunxi platform driver code and reset operations. The separate sunxi driver still remains to register the early reset controllers, but it reuses the reset operations in reset-simple. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Alexandru Gagniuc <alex.g@adaptrum.com> Reviewed-by: Chen-Yu Tsai <wens@csie.org>
2017-08-11 18:58:43 +08:00
select RESET_SIMPLE
reset: sunxi: add driver Kconfig option Visible only if COMPILE_TEST is enabled, this allows to include the driver in build tests. Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-08-09 15:28:44 +08:00
help
This enables the reset driver for Allwinner SoCs.
reset: Add the TI SCI reset driver Some TI Keystone family of SoCs contain a system controller (like the Power Management Micro Controller (PMMC) on 66AK2G SoCs) that manage the low-level device control (like clocks, resets etc) for the various hardware modules present on the SoC. These device control operations are provided to the host processor OS through a communication protocol called the TI System Control Interface (TI SCI) protocol. This patch adds a reset driver that communicates to the system controller over the TI SCI protocol for performing reset management of various devices present on the SoC. Various reset functionalities are achieved by the means of different TI SCI device operations provided by the TI SCI framework. Signed-off-by: Andrew F. Davis <afd@ti.com> [s-anna@ti.com: documentation changes, revised commit message] Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Santosh Shilimkar <ssantosh@kernel.org> [p.zabel@pengutronix.de: const struct reset_control_ops] Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2017-05-25 02:09:30 +08:00
config RESET_TI_SCI
tristate "TI System Control Interface (TI-SCI) reset driver"
depends on TI_SCI_PROTOCOL
help
This enables the reset driver support over TI System Control Interface
available on some new TI's SoCs. If you wish to use reset resources
managed by the TI System Controller, say Y here. Otherwise, say N.
reset: ti_syscon: Rename TI_SYSCON_RESET to RESET_TI_SYSCON Rename the current Kconfig name used for the TI SYSCON Reset driver from TI_SYSCON_RESET to RESET_TI_SYSCON to match the convention used for all the reset drivers present at the base reset folder. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2017-05-24 11:00:12 +08:00
config RESET_TI_SYSCON
reset: add TI SYSCON based reset driver Add a reset-controller driver for performing reset management of various devices present on the SoC, with the reset registers shared between devices in a common register memory space. This driver uses the syscon/regmap frameworks to actually implement the various reset functionalities needed by the reset consumer devices. Signed-off-by: Andrew F. Davis <afd@ti.com> [s-anna@ti.com: add documentation, syscon name change] Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-06-28 01:12:17 +08:00
tristate "TI SYSCON Reset Driver"
depends on HAS_IOMEM
select MFD_SYSCON
help
This enables the reset driver support for TI devices with
memory-mapped reset registers as part of a syscon device node. If
you wish to use the reset framework for such memory-mapped devices,
say Y here. Otherwise, say N.
reset: uniphier: add reset controller driver for UniPhier SoCs This is the initial commit for UniPhier reset controller driver. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-08-02 12:18:29 +08:00
config RESET_UNIPHIER
tristate "Reset controller driver for UniPhier SoCs"
depends on ARCH_UNIPHIER || COMPILE_TEST
depends on OF && MFD_SYSCON
default ARCH_UNIPHIER
help
Support for reset controllers on UniPhier SoCs.
Say Y if you want to control reset signals provided by System Control
block, Media I/O block, Peripheral Block.
reset: uniphier-usb3: Rename to reset-uniphier-glue This driver works for controlling the reset lines including USB3 glue layer, however, this can be applied to other glue layers. Now this patch renames the driver from "reset-uniphier-usb3" to "reset-uniphier-glue". At the same time, this changes CONFIG_RESET_UNIPHIER_USB3 to CONFIG_RESET_UNIPHIER_GLUE. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2018-11-09 09:42:05 +08:00
config RESET_UNIPHIER_GLUE
tristate "Reset driver in glue layer for UniPhier SoCs"
reset: uniphier: add USB3 core reset control Add a reset line to enable USB3 core implemented in UniPhier SoCs. This reuses only the reset operations in reset-simple, because the reset-simple doesn't handle any SoC-dependent clocks and resets. This reset line is included in the USB3 glue layer, and it's necessary to enable clocks and deassert resets of the layer before using this reset line. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2018-07-10 09:14:17 +08:00
depends on (ARCH_UNIPHIER || COMPILE_TEST) && OF
default ARCH_UNIPHIER
select RESET_SIMPLE
help
reset: uniphier-usb3: Rename to reset-uniphier-glue This driver works for controlling the reset lines including USB3 glue layer, however, this can be applied to other glue layers. Now this patch renames the driver from "reset-uniphier-usb3" to "reset-uniphier-glue". At the same time, this changes CONFIG_RESET_UNIPHIER_USB3 to CONFIG_RESET_UNIPHIER_GLUE. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2018-11-09 09:42:05 +08:00
Support for peripheral core reset included in its own glue layer
on UniPhier SoCs. Say Y if you want to control reset signals
provided by the glue layer.
reset: uniphier: add USB3 core reset control Add a reset line to enable USB3 core implemented in UniPhier SoCs. This reuses only the reset operations in reset-simple, because the reset-simple doesn't handle any SoC-dependent clocks and resets. This reset line is included in the USB3 glue layer, and it's necessary to enable clocks and deassert resets of the layer before using this reset line. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2018-07-10 09:14:17 +08:00
reset: zynq: add driver Kconfig option Visible only if COMPILE_TEST is enabled, this allows to include the driver in build tests. Cc: Moritz Fischer <moritz.fischer@ettus.com> Cc: Sören Brinkmann <soren.brinkmann@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-08-09 15:28:54 +08:00
config RESET_ZYNQ
bool "ZYNQ Reset Driver" if COMPILE_TEST
default ARCH_ZYNQ
help
This enables the reset controller driver for Xilinx Zynq SoCs.
drivers: reset: STi SoC system configuration reset controller support This patch adds a reset controller implementation for STMicroelectronics STi family SoCs; it allows a group of related reset like controls found in multiple system configuration registers to be represented by a single controller device. System configuration registers are accessed through the regmap framework and the mfd/syscon driver. The implementation optionally supports waiting for the reset action to be acknowledged in a separate status register and supports both active high and active low reset lines. These properties are common across all the reset channels in a specific reset controller instance, hence all channels in a paritcular controller are expected to behave in the same way. Signed-off-by: Stephen Gallimore <stephen.gallimore@st.com> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com> Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
2013-08-07 22:53:12 +08:00
source "drivers/reset/sti/Kconfig"
reset: hi6220: Reset driver for hisilicon hi6220 SoC Add reset driver for hi6220-hikey board,this driver supply deassert of IP on hi6220 SoC. Signed-off-by: Chen Feng <puck.chen@hisilicon.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2015-11-20 10:10:05 +08:00
source "drivers/reset/hisilicon/Kconfig"
reset: Add Tegra BPMP reset driver This driver uses the services provided by the BPMP firmware driver to implement a reset driver based on the MRQ_RESET request. Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-08-18 21:50:09 +08:00
source "drivers/reset/tegra/Kconfig"
reset: fix Kconfig menu to include reset drivers in sub-menu In "make menuconfig", reset drivers are currently lined up together with the reset sub-system menu, like this: -*- Reset Controller Support ---- < > Hi6220 Reset Driver (It also means, the menu "Reset Controller Support" is always empty.) "Hi6220 Reset Driver" should go into the sub-menu of the "Reset Controller Support". Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-05-03 14:29:52 +08:00
endif