658 lines
18 KiB
C
658 lines
18 KiB
C
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/*
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* Copyright 2008 Advanced Micro Devices, Inc.
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* Copyright 2008 Red Hat Inc.
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* Copyright 2009 Jerome Glisse.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Dave Airlie
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* Alex Deucher
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* Jerome Glisse
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*/
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#include "drmP.h"
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#include "radeon.h"
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#include "r600d.h"
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#include "avivod.h"
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static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p,
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struct radeon_cs_reloc **cs_reloc);
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static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p,
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struct radeon_cs_reloc **cs_reloc);
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typedef int (*next_reloc_t)(struct radeon_cs_parser*, struct radeon_cs_reloc**);
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static next_reloc_t r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_mm;
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/**
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* r600_cs_packet_parse() - parse cp packet and point ib index to next packet
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* @parser: parser structure holding parsing context.
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* @pkt: where to store packet informations
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*
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* Assume that chunk_ib_index is properly set. Will return -EINVAL
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* if packet is bigger than remaining ib size. or if packets is unknown.
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**/
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int r600_cs_packet_parse(struct radeon_cs_parser *p,
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struct radeon_cs_packet *pkt,
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unsigned idx)
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{
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struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
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uint32_t header;
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if (idx >= ib_chunk->length_dw) {
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DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
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idx, ib_chunk->length_dw);
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return -EINVAL;
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}
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header = ib_chunk->kdata[idx];
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pkt->idx = idx;
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pkt->type = CP_PACKET_GET_TYPE(header);
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pkt->count = CP_PACKET_GET_COUNT(header);
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pkt->one_reg_wr = 0;
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switch (pkt->type) {
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case PACKET_TYPE0:
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pkt->reg = CP_PACKET0_GET_REG(header);
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break;
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case PACKET_TYPE3:
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pkt->opcode = CP_PACKET3_GET_OPCODE(header);
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break;
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case PACKET_TYPE2:
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pkt->count = -1;
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break;
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default:
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DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
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return -EINVAL;
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}
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if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
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DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
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pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
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return -EINVAL;
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}
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return 0;
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}
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/**
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* r600_cs_packet_next_reloc_mm() - parse next packet which should be reloc packet3
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* @parser: parser structure holding parsing context.
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* @data: pointer to relocation data
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* @offset_start: starting offset
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* @offset_mask: offset mask (to align start offset on)
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* @reloc: reloc informations
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*
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* Check next packet is relocation packet3, do bo validation and compute
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* GPU offset using the provided start.
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**/
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static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p,
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struct radeon_cs_reloc **cs_reloc)
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{
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struct radeon_cs_chunk *ib_chunk;
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struct radeon_cs_chunk *relocs_chunk;
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struct radeon_cs_packet p3reloc;
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unsigned idx;
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int r;
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if (p->chunk_relocs_idx == -1) {
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DRM_ERROR("No relocation chunk !\n");
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return -EINVAL;
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}
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*cs_reloc = NULL;
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ib_chunk = &p->chunks[p->chunk_ib_idx];
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relocs_chunk = &p->chunks[p->chunk_relocs_idx];
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r = r600_cs_packet_parse(p, &p3reloc, p->idx);
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if (r) {
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return r;
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}
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p->idx += p3reloc.count + 2;
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if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
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DRM_ERROR("No packet3 for relocation for packet at %d.\n",
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p3reloc.idx);
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return -EINVAL;
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}
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idx = ib_chunk->kdata[p3reloc.idx + 1];
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if (idx >= relocs_chunk->length_dw) {
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DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
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idx, relocs_chunk->length_dw);
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return -EINVAL;
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}
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/* FIXME: we assume reloc size is 4 dwords */
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*cs_reloc = p->relocs_ptr[(idx / 4)];
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return 0;
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}
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/**
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* r600_cs_packet_next_reloc_nomm() - parse next packet which should be reloc packet3
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* @parser: parser structure holding parsing context.
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* @data: pointer to relocation data
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* @offset_start: starting offset
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* @offset_mask: offset mask (to align start offset on)
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* @reloc: reloc informations
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*
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* Check next packet is relocation packet3, do bo validation and compute
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* GPU offset using the provided start.
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**/
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static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p,
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struct radeon_cs_reloc **cs_reloc)
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{
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struct radeon_cs_chunk *ib_chunk;
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struct radeon_cs_chunk *relocs_chunk;
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struct radeon_cs_packet p3reloc;
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unsigned idx;
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int r;
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if (p->chunk_relocs_idx == -1) {
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DRM_ERROR("No relocation chunk !\n");
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return -EINVAL;
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}
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*cs_reloc = NULL;
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ib_chunk = &p->chunks[p->chunk_ib_idx];
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relocs_chunk = &p->chunks[p->chunk_relocs_idx];
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r = r600_cs_packet_parse(p, &p3reloc, p->idx);
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if (r) {
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return r;
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}
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p->idx += p3reloc.count + 2;
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if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
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DRM_ERROR("No packet3 for relocation for packet at %d.\n",
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p3reloc.idx);
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return -EINVAL;
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}
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idx = ib_chunk->kdata[p3reloc.idx + 1];
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if (idx >= relocs_chunk->length_dw) {
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DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
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idx, relocs_chunk->length_dw);
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return -EINVAL;
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}
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*cs_reloc = &p->relocs[0];
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(*cs_reloc)->lobj.gpu_offset = (u64)relocs_chunk->kdata[idx + 3] << 32;
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(*cs_reloc)->lobj.gpu_offset |= relocs_chunk->kdata[idx + 0];
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return 0;
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}
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static int r600_packet0_check(struct radeon_cs_parser *p,
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struct radeon_cs_packet *pkt,
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unsigned idx, unsigned reg)
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{
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switch (reg) {
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case AVIVO_D1MODE_VLINE_START_END:
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case AVIVO_D2MODE_VLINE_START_END:
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break;
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default:
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printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
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reg, idx);
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return -EINVAL;
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}
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return 0;
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}
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static int r600_cs_parse_packet0(struct radeon_cs_parser *p,
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struct radeon_cs_packet *pkt)
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{
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unsigned reg, i;
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unsigned idx;
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int r;
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idx = pkt->idx + 1;
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reg = pkt->reg;
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for (i = 0; i <= pkt->count; i++, idx++, reg += 4) {
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r = r600_packet0_check(p, pkt, idx, reg);
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if (r) {
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return r;
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}
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}
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return 0;
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}
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static int r600_packet3_check(struct radeon_cs_parser *p,
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struct radeon_cs_packet *pkt)
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{
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struct radeon_cs_chunk *ib_chunk;
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struct radeon_cs_reloc *reloc;
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volatile u32 *ib;
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unsigned idx;
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unsigned i;
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unsigned start_reg, end_reg, reg;
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int r;
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ib = p->ib->ptr;
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ib_chunk = &p->chunks[p->chunk_ib_idx];
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idx = pkt->idx + 1;
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switch (pkt->opcode) {
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case PACKET3_START_3D_CMDBUF:
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if (p->family >= CHIP_RV770 || pkt->count) {
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DRM_ERROR("bad START_3D\n");
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return -EINVAL;
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}
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break;
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case PACKET3_CONTEXT_CONTROL:
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if (pkt->count != 1) {
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DRM_ERROR("bad CONTEXT_CONTROL\n");
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return -EINVAL;
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}
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break;
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case PACKET3_INDEX_TYPE:
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case PACKET3_NUM_INSTANCES:
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if (pkt->count) {
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DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES\n");
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return -EINVAL;
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}
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break;
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case PACKET3_DRAW_INDEX:
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if (pkt->count != 3) {
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DRM_ERROR("bad DRAW_INDEX\n");
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return -EINVAL;
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}
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r = r600_cs_packet_next_reloc(p, &reloc);
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if (r) {
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DRM_ERROR("bad DRAW_INDEX\n");
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return -EINVAL;
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}
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ib[idx+0] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
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ib[idx+1] = upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
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break;
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case PACKET3_DRAW_INDEX_AUTO:
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if (pkt->count != 1) {
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DRM_ERROR("bad DRAW_INDEX_AUTO\n");
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return -EINVAL;
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}
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break;
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case PACKET3_DRAW_INDEX_IMMD_BE:
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case PACKET3_DRAW_INDEX_IMMD:
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if (pkt->count < 2) {
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DRM_ERROR("bad DRAW_INDEX_IMMD\n");
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return -EINVAL;
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}
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break;
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case PACKET3_WAIT_REG_MEM:
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if (pkt->count != 5) {
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DRM_ERROR("bad WAIT_REG_MEM\n");
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return -EINVAL;
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}
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/* bit 4 is reg (0) or mem (1) */
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if (ib_chunk->kdata[idx+0] & 0x10) {
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r = r600_cs_packet_next_reloc(p, &reloc);
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if (r) {
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DRM_ERROR("bad WAIT_REG_MEM\n");
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return -EINVAL;
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}
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ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
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ib[idx+2] = upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
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}
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break;
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case PACKET3_SURFACE_SYNC:
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if (pkt->count != 3) {
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DRM_ERROR("bad SURFACE_SYNC\n");
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return -EINVAL;
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}
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/* 0xffffffff/0x0 is flush all cache flag */
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if (ib_chunk->kdata[idx+1] != 0xffffffff ||
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ib_chunk->kdata[idx+2] != 0) {
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r = r600_cs_packet_next_reloc(p, &reloc);
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if (r) {
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DRM_ERROR("bad SURFACE_SYNC\n");
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return -EINVAL;
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}
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ib[idx+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
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}
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break;
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case PACKET3_EVENT_WRITE:
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if (pkt->count != 2 && pkt->count != 0) {
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DRM_ERROR("bad EVENT_WRITE\n");
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return -EINVAL;
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}
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if (pkt->count) {
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r = r600_cs_packet_next_reloc(p, &reloc);
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if (r) {
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DRM_ERROR("bad EVENT_WRITE\n");
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return -EINVAL;
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}
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ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
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ib[idx+2] |= upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
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}
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break;
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case PACKET3_EVENT_WRITE_EOP:
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if (pkt->count != 4) {
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DRM_ERROR("bad EVENT_WRITE_EOP\n");
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return -EINVAL;
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}
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r = r600_cs_packet_next_reloc(p, &reloc);
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if (r) {
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DRM_ERROR("bad EVENT_WRITE\n");
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return -EINVAL;
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}
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ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
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ib[idx+2] |= upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
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break;
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case PACKET3_SET_CONFIG_REG:
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start_reg = (ib[idx+0] << 2) + PACKET3_SET_CONFIG_REG_OFFSET;
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end_reg = 4 * pkt->count + start_reg - 4;
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if ((start_reg < PACKET3_SET_CONFIG_REG_OFFSET) ||
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(start_reg >= PACKET3_SET_CONFIG_REG_END) ||
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(end_reg >= PACKET3_SET_CONFIG_REG_END)) {
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|
|
DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n");
|
||
|
|
return -EINVAL;
|
||
|
|
}
|
||
|
|
for (i = 0; i < pkt->count; i++) {
|
||
|
|
reg = start_reg + (4 * i);
|
||
|
|
switch (reg) {
|
||
|
|
case CP_COHER_BASE:
|
||
|
|
/* use PACKET3_SURFACE_SYNC */
|
||
|
|
return -EINVAL;
|
||
|
|
default:
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
case PACKET3_SET_CONTEXT_REG:
|
||
|
|
start_reg = (ib[idx+0] << 2) + PACKET3_SET_CONTEXT_REG_OFFSET;
|
||
|
|
end_reg = 4 * pkt->count + start_reg - 4;
|
||
|
|
if ((start_reg < PACKET3_SET_CONTEXT_REG_OFFSET) ||
|
||
|
|
(start_reg >= PACKET3_SET_CONTEXT_REG_END) ||
|
||
|
|
(end_reg >= PACKET3_SET_CONTEXT_REG_END)) {
|
||
|
|
DRM_ERROR("bad PACKET3_SET_CONTEXT_REG\n");
|
||
|
|
return -EINVAL;
|
||
|
|
}
|
||
|
|
for (i = 0; i < pkt->count; i++) {
|
||
|
|
reg = start_reg + (4 * i);
|
||
|
|
switch (reg) {
|
||
|
|
case DB_DEPTH_BASE:
|
||
|
|
case CB_COLOR0_BASE:
|
||
|
|
case CB_COLOR1_BASE:
|
||
|
|
case CB_COLOR2_BASE:
|
||
|
|
case CB_COLOR3_BASE:
|
||
|
|
case CB_COLOR4_BASE:
|
||
|
|
case CB_COLOR5_BASE:
|
||
|
|
case CB_COLOR6_BASE:
|
||
|
|
case CB_COLOR7_BASE:
|
||
|
|
case SQ_PGM_START_FS:
|
||
|
|
case SQ_PGM_START_ES:
|
||
|
|
case SQ_PGM_START_VS:
|
||
|
|
case SQ_PGM_START_GS:
|
||
|
|
case SQ_PGM_START_PS:
|
||
|
|
r = r600_cs_packet_next_reloc(p, &reloc);
|
||
|
|
if (r) {
|
||
|
|
DRM_ERROR("bad SET_CONTEXT_REG "
|
||
|
|
"0x%04X\n", reg);
|
||
|
|
return -EINVAL;
|
||
|
|
}
|
||
|
|
ib[idx+1+i] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
|
||
|
|
break;
|
||
|
|
case VGT_DMA_BASE:
|
||
|
|
case VGT_DMA_BASE_HI:
|
||
|
|
/* These should be handled by DRAW_INDEX packet 3 */
|
||
|
|
case VGT_STRMOUT_BASE_OFFSET_0:
|
||
|
|
case VGT_STRMOUT_BASE_OFFSET_1:
|
||
|
|
case VGT_STRMOUT_BASE_OFFSET_2:
|
||
|
|
case VGT_STRMOUT_BASE_OFFSET_3:
|
||
|
|
case VGT_STRMOUT_BASE_OFFSET_HI_0:
|
||
|
|
case VGT_STRMOUT_BASE_OFFSET_HI_1:
|
||
|
|
case VGT_STRMOUT_BASE_OFFSET_HI_2:
|
||
|
|
case VGT_STRMOUT_BASE_OFFSET_HI_3:
|
||
|
|
case VGT_STRMOUT_BUFFER_BASE_0:
|
||
|
|
case VGT_STRMOUT_BUFFER_BASE_1:
|
||
|
|
case VGT_STRMOUT_BUFFER_BASE_2:
|
||
|
|
case VGT_STRMOUT_BUFFER_BASE_3:
|
||
|
|
case VGT_STRMOUT_BUFFER_OFFSET_0:
|
||
|
|
case VGT_STRMOUT_BUFFER_OFFSET_1:
|
||
|
|
case VGT_STRMOUT_BUFFER_OFFSET_2:
|
||
|
|
case VGT_STRMOUT_BUFFER_OFFSET_3:
|
||
|
|
/* These should be handled by STRMOUT_BUFFER packet 3 */
|
||
|
|
DRM_ERROR("bad context reg: 0x%08x\n", reg);
|
||
|
|
return -EINVAL;
|
||
|
|
default:
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
case PACKET3_SET_RESOURCE:
|
||
|
|
if (pkt->count % 7) {
|
||
|
|
DRM_ERROR("bad SET_RESOURCE\n");
|
||
|
|
return -EINVAL;
|
||
|
|
}
|
||
|
|
start_reg = (ib[idx+0] << 2) + PACKET3_SET_RESOURCE_OFFSET;
|
||
|
|
end_reg = 4 * pkt->count + start_reg - 4;
|
||
|
|
if ((start_reg < PACKET3_SET_RESOURCE_OFFSET) ||
|
||
|
|
(start_reg >= PACKET3_SET_RESOURCE_END) ||
|
||
|
|
(end_reg >= PACKET3_SET_RESOURCE_END)) {
|
||
|
|
DRM_ERROR("bad SET_RESOURCE\n");
|
||
|
|
return -EINVAL;
|
||
|
|
}
|
||
|
|
for (i = 0; i < (pkt->count / 7); i++) {
|
||
|
|
switch (G__SQ_VTX_CONSTANT_TYPE(ib[idx+(i*7)+6+1])) {
|
||
|
|
case SQ_TEX_VTX_VALID_TEXTURE:
|
||
|
|
/* tex base */
|
||
|
|
r = r600_cs_packet_next_reloc(p, &reloc);
|
||
|
|
if (r) {
|
||
|
|
DRM_ERROR("bad SET_RESOURCE\n");
|
||
|
|
return -EINVAL;
|
||
|
|
}
|
||
|
|
ib[idx+1+(i*7)+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
|
||
|
|
/* tex mip base */
|
||
|
|
r = r600_cs_packet_next_reloc(p, &reloc);
|
||
|
|
if (r) {
|
||
|
|
DRM_ERROR("bad SET_RESOURCE\n");
|
||
|
|
return -EINVAL;
|
||
|
|
}
|
||
|
|
ib[idx+1+(i*7)+3] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
|
||
|
|
break;
|
||
|
|
case SQ_TEX_VTX_VALID_BUFFER:
|
||
|
|
/* vtx base */
|
||
|
|
r = r600_cs_packet_next_reloc(p, &reloc);
|
||
|
|
if (r) {
|
||
|
|
DRM_ERROR("bad SET_RESOURCE\n");
|
||
|
|
return -EINVAL;
|
||
|
|
}
|
||
|
|
ib[idx+1+(i*7)+0] += (u32)((reloc->lobj.gpu_offset) & 0xffffffff);
|
||
|
|
ib[idx+1+(i*7)+2] |= upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
|
||
|
|
break;
|
||
|
|
case SQ_TEX_VTX_INVALID_TEXTURE:
|
||
|
|
case SQ_TEX_VTX_INVALID_BUFFER:
|
||
|
|
default:
|
||
|
|
DRM_ERROR("bad SET_RESOURCE\n");
|
||
|
|
return -EINVAL;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
case PACKET3_SET_ALU_CONST:
|
||
|
|
start_reg = (ib[idx+0] << 2) + PACKET3_SET_ALU_CONST_OFFSET;
|
||
|
|
end_reg = 4 * pkt->count + start_reg - 4;
|
||
|
|
if ((start_reg < PACKET3_SET_ALU_CONST_OFFSET) ||
|
||
|
|
(start_reg >= PACKET3_SET_ALU_CONST_END) ||
|
||
|
|
(end_reg >= PACKET3_SET_ALU_CONST_END)) {
|
||
|
|
DRM_ERROR("bad SET_ALU_CONST\n");
|
||
|
|
return -EINVAL;
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
case PACKET3_SET_BOOL_CONST:
|
||
|
|
start_reg = (ib[idx+0] << 2) + PACKET3_SET_BOOL_CONST_OFFSET;
|
||
|
|
end_reg = 4 * pkt->count + start_reg - 4;
|
||
|
|
if ((start_reg < PACKET3_SET_BOOL_CONST_OFFSET) ||
|
||
|
|
(start_reg >= PACKET3_SET_BOOL_CONST_END) ||
|
||
|
|
(end_reg >= PACKET3_SET_BOOL_CONST_END)) {
|
||
|
|
DRM_ERROR("bad SET_BOOL_CONST\n");
|
||
|
|
return -EINVAL;
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
case PACKET3_SET_LOOP_CONST:
|
||
|
|
start_reg = (ib[idx+0] << 2) + PACKET3_SET_LOOP_CONST_OFFSET;
|
||
|
|
end_reg = 4 * pkt->count + start_reg - 4;
|
||
|
|
if ((start_reg < PACKET3_SET_LOOP_CONST_OFFSET) ||
|
||
|
|
(start_reg >= PACKET3_SET_LOOP_CONST_END) ||
|
||
|
|
(end_reg >= PACKET3_SET_LOOP_CONST_END)) {
|
||
|
|
DRM_ERROR("bad SET_LOOP_CONST\n");
|
||
|
|
return -EINVAL;
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
case PACKET3_SET_CTL_CONST:
|
||
|
|
start_reg = (ib[idx+0] << 2) + PACKET3_SET_CTL_CONST_OFFSET;
|
||
|
|
end_reg = 4 * pkt->count + start_reg - 4;
|
||
|
|
if ((start_reg < PACKET3_SET_CTL_CONST_OFFSET) ||
|
||
|
|
(start_reg >= PACKET3_SET_CTL_CONST_END) ||
|
||
|
|
(end_reg >= PACKET3_SET_CTL_CONST_END)) {
|
||
|
|
DRM_ERROR("bad SET_CTL_CONST\n");
|
||
|
|
return -EINVAL;
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
case PACKET3_SET_SAMPLER:
|
||
|
|
if (pkt->count % 3) {
|
||
|
|
DRM_ERROR("bad SET_SAMPLER\n");
|
||
|
|
return -EINVAL;
|
||
|
|
}
|
||
|
|
start_reg = (ib[idx+0] << 2) + PACKET3_SET_SAMPLER_OFFSET;
|
||
|
|
end_reg = 4 * pkt->count + start_reg - 4;
|
||
|
|
if ((start_reg < PACKET3_SET_SAMPLER_OFFSET) ||
|
||
|
|
(start_reg >= PACKET3_SET_SAMPLER_END) ||
|
||
|
|
(end_reg >= PACKET3_SET_SAMPLER_END)) {
|
||
|
|
DRM_ERROR("bad SET_SAMPLER\n");
|
||
|
|
return -EINVAL;
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
case PACKET3_SURFACE_BASE_UPDATE:
|
||
|
|
if (p->family >= CHIP_RV770 || p->family == CHIP_R600) {
|
||
|
|
DRM_ERROR("bad SURFACE_BASE_UPDATE\n");
|
||
|
|
return -EINVAL;
|
||
|
|
}
|
||
|
|
if (pkt->count) {
|
||
|
|
DRM_ERROR("bad SURFACE_BASE_UPDATE\n");
|
||
|
|
return -EINVAL;
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
case PACKET3_NOP:
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
|
||
|
|
return -EINVAL;
|
||
|
|
}
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
int r600_cs_parse(struct radeon_cs_parser *p)
|
||
|
|
{
|
||
|
|
struct radeon_cs_packet pkt;
|
||
|
|
int r;
|
||
|
|
|
||
|
|
do {
|
||
|
|
r = r600_cs_packet_parse(p, &pkt, p->idx);
|
||
|
|
if (r) {
|
||
|
|
return r;
|
||
|
|
}
|
||
|
|
p->idx += pkt.count + 2;
|
||
|
|
switch (pkt.type) {
|
||
|
|
case PACKET_TYPE0:
|
||
|
|
r = r600_cs_parse_packet0(p, &pkt);
|
||
|
|
break;
|
||
|
|
case PACKET_TYPE2:
|
||
|
|
break;
|
||
|
|
case PACKET_TYPE3:
|
||
|
|
r = r600_packet3_check(p, &pkt);
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
DRM_ERROR("Unknown packet type %d !\n", pkt.type);
|
||
|
|
return -EINVAL;
|
||
|
|
}
|
||
|
|
if (r) {
|
||
|
|
return r;
|
||
|
|
}
|
||
|
|
} while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
|
||
|
|
#if 0
|
||
|
|
for (r = 0; r < p->ib->length_dw; r++) {
|
||
|
|
printk(KERN_INFO "%05d 0x%08X\n", r, p->ib->ptr[r]);
|
||
|
|
mdelay(1);
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int r600_cs_parser_relocs_legacy(struct radeon_cs_parser *p)
|
||
|
|
{
|
||
|
|
if (p->chunk_relocs_idx == -1) {
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
p->relocs = kcalloc(1, sizeof(struct radeon_cs_reloc), GFP_KERNEL);
|
||
|
|
if (p->relocs == NULL) {
|
||
|
|
return -ENOMEM;
|
||
|
|
}
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* cs_parser_fini() - clean parser states
|
||
|
|
* @parser: parser structure holding parsing context.
|
||
|
|
* @error: error number
|
||
|
|
*
|
||
|
|
* If error is set than unvalidate buffer, otherwise just free memory
|
||
|
|
* used by parsing context.
|
||
|
|
**/
|
||
|
|
static void r600_cs_parser_fini(struct radeon_cs_parser *parser, int error)
|
||
|
|
{
|
||
|
|
unsigned i;
|
||
|
|
|
||
|
|
kfree(parser->relocs);
|
||
|
|
for (i = 0; i < parser->nchunks; i++) {
|
||
|
|
kfree(parser->chunks[i].kdata);
|
||
|
|
}
|
||
|
|
kfree(parser->chunks);
|
||
|
|
kfree(parser->chunks_array);
|
||
|
|
}
|
||
|
|
|
||
|
|
int r600_cs_legacy(struct drm_device *dev, void *data, struct drm_file *filp,
|
||
|
|
unsigned family, u32 *ib, int *l)
|
||
|
|
{
|
||
|
|
struct radeon_cs_parser parser;
|
||
|
|
struct radeon_cs_chunk *ib_chunk;
|
||
|
|
struct radeon_ib fake_ib;
|
||
|
|
int r;
|
||
|
|
|
||
|
|
/* initialize parser */
|
||
|
|
memset(&parser, 0, sizeof(struct radeon_cs_parser));
|
||
|
|
parser.filp = filp;
|
||
|
|
parser.rdev = NULL;
|
||
|
|
parser.family = family;
|
||
|
|
parser.ib = &fake_ib;
|
||
|
|
fake_ib.ptr = ib;
|
||
|
|
r = radeon_cs_parser_init(&parser, data);
|
||
|
|
if (r) {
|
||
|
|
DRM_ERROR("Failed to initialize parser !\n");
|
||
|
|
r600_cs_parser_fini(&parser, r);
|
||
|
|
return r;
|
||
|
|
}
|
||
|
|
r = r600_cs_parser_relocs_legacy(&parser);
|
||
|
|
if (r) {
|
||
|
|
DRM_ERROR("Failed to parse relocation !\n");
|
||
|
|
r600_cs_parser_fini(&parser, r);
|
||
|
|
return r;
|
||
|
|
}
|
||
|
|
/* Copy the packet into the IB, the parser will read from the
|
||
|
|
* input memory (cached) and write to the IB (which can be
|
||
|
|
* uncached). */
|
||
|
|
ib_chunk = &parser.chunks[parser.chunk_ib_idx];
|
||
|
|
parser.ib->length_dw = ib_chunk->length_dw;
|
||
|
|
memcpy((void *)parser.ib->ptr, ib_chunk->kdata, ib_chunk->length_dw*4);
|
||
|
|
*l = parser.ib->length_dw;
|
||
|
|
r = r600_cs_parse(&parser);
|
||
|
|
if (r) {
|
||
|
|
DRM_ERROR("Invalid command stream !\n");
|
||
|
|
r600_cs_parser_fini(&parser, r);
|
||
|
|
return r;
|
||
|
|
}
|
||
|
|
r600_cs_parser_fini(&parser, r);
|
||
|
|
return r;
|
||
|
|
}
|
||
|
|
|
||
|
|
void r600_cs_legacy_init(void)
|
||
|
|
{
|
||
|
|
r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_nomm;
|
||
|
|
}
|