2019-08-16 02:37:33 +08:00
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// SPDX-License-Identifier: GPL-2.0-only
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// Miscellaneous Arm SMMU implementation and integration quirks
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// Copyright (C) 2019 Arm Limited
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#define pr_fmt(fmt) "arm-smmu: " fmt
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2019-08-16 02:37:34 +08:00
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#include <linux/of.h>
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2019-08-16 02:37:33 +08:00
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#include "arm-smmu.h"
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2019-08-16 02:37:34 +08:00
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static int arm_smmu_gr0_ns(int offset)
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{
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switch(offset) {
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case ARM_SMMU_GR0_sCR0:
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case ARM_SMMU_GR0_sACR:
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case ARM_SMMU_GR0_sGFSR:
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case ARM_SMMU_GR0_sGFSYNR0:
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case ARM_SMMU_GR0_sGFSYNR1:
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case ARM_SMMU_GR0_sGFSYNR2:
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return offset + 0x400;
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default:
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return offset;
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}
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}
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static u32 arm_smmu_read_ns(struct arm_smmu_device *smmu, int page,
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int offset)
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{
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if (page == ARM_SMMU_GR0)
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offset = arm_smmu_gr0_ns(offset);
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return readl_relaxed(arm_smmu_page(smmu, page) + offset);
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}
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static void arm_smmu_write_ns(struct arm_smmu_device *smmu, int page,
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int offset, u32 val)
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{
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if (page == ARM_SMMU_GR0)
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offset = arm_smmu_gr0_ns(offset);
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writel_relaxed(val, arm_smmu_page(smmu, page) + offset);
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}
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/* Since we don't care for sGFAR, we can do without 64-bit accessors */
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const struct arm_smmu_impl calxeda_impl = {
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.read_reg = arm_smmu_read_ns,
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.write_reg = arm_smmu_write_ns,
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};
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2019-08-16 02:37:35 +08:00
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static int cavium_cfg_probe(struct arm_smmu_device *smmu)
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{
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static atomic_t context_count = ATOMIC_INIT(0);
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/*
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* Cavium CN88xx erratum #27704.
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* Ensure ASID and VMID allocation is unique across all SMMUs in
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* the system.
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*/
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smmu->cavium_id_base = atomic_fetch_add(smmu->num_context_banks,
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&context_count);
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dev_notice(smmu->dev, "\tenabling workaround for Cavium erratum 27704\n");
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return 0;
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}
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const struct arm_smmu_impl cavium_impl = {
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.cfg_probe = cavium_cfg_probe,
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};
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2019-08-16 02:37:33 +08:00
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struct arm_smmu_device *arm_smmu_impl_init(struct arm_smmu_device *smmu)
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{
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2019-08-16 02:37:35 +08:00
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/*
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* We will inevitably have to combine model-specific implementation
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* quirks with platform-specific integration quirks, but everything
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* we currently support happens to work out as straightforward
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* mutually-exclusive assignments.
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*/
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switch (smmu->model) {
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case CAVIUM_SMMUV2:
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smmu->impl = &cavium_impl;
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break;
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default:
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break;
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}
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2019-08-16 02:37:34 +08:00
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if (of_property_read_bool(smmu->dev->of_node,
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"calxeda,smmu-secure-config-access"))
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smmu->impl = &calxeda_impl;
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2019-08-16 02:37:33 +08:00
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return smmu;
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}
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