98 lines
2.5 KiB
C
98 lines
2.5 KiB
C
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
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*
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* This doesn't really fly - but I don't have a GT64240 system for testing.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <asm/gt64240.h>
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/*
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* We assume these address ranges have been programmed into the GT-64240 by
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* the firmware. PMON in case of the Ocelot G does that. Note the size of
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* the I/O range is completly stupid; I/O mappings are limited to at most
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* 256 bytes by the PCI spec and deprecated; and just to make things worse
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* apparently many devices don't decode more than 64k of I/O space.
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*/
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#define gt_io_size 0x20000000UL
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#define gt_io_base 0xe0000000UL
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static struct resource gt_pci_mem0_resource = {
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.name = "MV64240 PCI0 MEM",
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.start = 0xc0000000UL,
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.end = 0xcfffffffUL,
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.flags = IORESOURCE_MEM
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};
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static struct resource gt_pci_io_mem0_resource = {
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.name = "MV64240 PCI0 IO MEM",
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.start = 0xe0000000UL,
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.end = 0xefffffffUL,
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.flags = IORESOURCE_IO
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};
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static struct mv_pci_controller gt_bus0_controller = {
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.pcic = {
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.pci_ops = &mv_pci_ops,
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.mem_resource = >_pci_mem0_resource,
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.mem_offset = 0xc0000000UL,
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.io_resource = >_pci_io_mem0_resource,
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.io_offset = 0x00000000UL
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},
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.config_addr = PCI_0CONFIGURATION_ADDRESS,
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.config_vreg = PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER,
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};
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static struct resource gt_pci_mem1_resource = {
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.name = "MV64240 PCI1 MEM",
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.start = 0xd0000000UL,
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.end = 0xdfffffffUL,
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.flags = IORESOURCE_MEM
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};
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static struct resource gt_pci_io_mem1_resource = {
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.name = "MV64240 PCI1 IO MEM",
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.start = 0xf0000000UL,
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.end = 0xffffffffUL,
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.flags = IORESOURCE_IO
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};
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static struct mv_pci_controller gt_bus1_controller = {
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.pcic = {
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.pci_ops = &mv_pci_ops,
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.mem_resource = >_pci_mem1_resource,
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.mem_offset = 0xd0000000UL,
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.io_resource = >_pci_io_mem1_resource,
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.io_offset = 0x10000000UL
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},
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.config_addr = PCI_1CONFIGURATION_ADDRESS,
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.config_vreg = PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER,
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};
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static __init int __init ocelot_g_pci_init(void)
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{
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unsigned long io_v_base;
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if (gt_io_size) {
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io_v_base = (unsigned long) ioremap(gt_io_base, gt_io_size);
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if (!io_v_base)
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panic("Could not ioremap I/O port range");
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set_io_port_base(io_v_base);
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}
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register_pci_controller(>_bus0_controller.pcic);
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register_pci_controller(>_bus1_controller.pcic);
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return 0;
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}
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arch_initcall(ocelot_g_pci_init);
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