2005-04-17 06:20:36 +08:00
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/* $Id: icc.c,v 1.8.2.3 2004/01/13 14:31:25 keil Exp $
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*
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* ICC specific routines
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*
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* Author Matt Henderson & Guy Ellis
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* Copyright by Traverse Technologies Pty Ltd, www.travers.com.au
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*
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* This software may be used and distributed according to the terms
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* of the GNU General Public License, incorporated herein by reference.
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*
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* 1999.6.25 Initial implementation of routines for Siemens ISDN
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* Communication Controller PEB 2070 based on the ISAC routines
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* written by Karsten Keil.
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*
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*/
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#include <linux/init.h>
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#include "hisax.h"
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#include "icc.h"
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// #include "arcofi.h"
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#include "isdnl1.h"
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#include <linux/interrupt.h>
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#define DBUSY_TIMER_VALUE 80
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#define ARCOFI_USE 0
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2006-07-10 19:44:11 +08:00
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static char *ICCVer[] =
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2005-04-17 06:20:36 +08:00
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{"2070 A1/A3", "2070 B1", "2070 B2/B3", "2070 V2.4"};
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2006-07-10 19:44:11 +08:00
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void
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2005-04-17 06:20:36 +08:00
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ICCVersion(struct IsdnCardState *cs, char *s)
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{
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int val;
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val = cs->readisac(cs, ICC_RBCH);
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printk(KERN_INFO "%s ICC version (%x): %s\n", s, val, ICCVer[(val >> 5) & 3]);
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}
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static void
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ph_command(struct IsdnCardState *cs, unsigned int command)
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{
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if (cs->debug & L1_DEB_ISAC)
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debugl1(cs, "ph_command %x", command);
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cs->writeisac(cs, ICC_CIX0, (command << 2) | 3);
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}
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static void
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icc_new_ph(struct IsdnCardState *cs)
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{
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switch (cs->dc.icc.ph_state) {
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case (ICC_IND_EI1):
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ph_command(cs, ICC_CMD_DI);
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l1_msg(cs, HW_RESET | INDICATION, NULL);
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break;
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case (ICC_IND_DC):
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l1_msg(cs, HW_DEACTIVATE | CONFIRM, NULL);
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break;
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case (ICC_IND_DR):
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l1_msg(cs, HW_DEACTIVATE | INDICATION, NULL);
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break;
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case (ICC_IND_PU):
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l1_msg(cs, HW_POWERUP | CONFIRM, NULL);
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break;
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case (ICC_IND_FJ):
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l1_msg(cs, HW_RSYNC | INDICATION, NULL);
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break;
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case (ICC_IND_AR):
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l1_msg(cs, HW_INFO2 | INDICATION, NULL);
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break;
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case (ICC_IND_AI):
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l1_msg(cs, HW_INFO4 | INDICATION, NULL);
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break;
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default:
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break;
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}
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}
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static void
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2006-11-22 22:57:56 +08:00
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icc_bh(struct work_struct *work)
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2005-04-17 06:20:36 +08:00
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{
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2006-11-22 22:57:56 +08:00
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struct IsdnCardState *cs =
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container_of(work, struct IsdnCardState, tqueue);
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2005-04-17 06:20:36 +08:00
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struct PStack *stptr;
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if (test_and_clear_bit(D_CLEARBUSY, &cs->event)) {
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if (cs->debug)
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debugl1(cs, "D-Channel Busy cleared");
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stptr = cs->stlist;
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while (stptr != NULL) {
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stptr->l1.l1l2(stptr, PH_PAUSE | CONFIRM, NULL);
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stptr = stptr->next;
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}
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}
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if (test_and_clear_bit(D_L1STATECHANGE, &cs->event))
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icc_new_ph(cs);
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if (test_and_clear_bit(D_RCVBUFREADY, &cs->event))
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DChannel_proc_rcv(cs);
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if (test_and_clear_bit(D_XMTBUFREADY, &cs->event))
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DChannel_proc_xmt(cs);
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#if ARCOFI_USE
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if (!test_bit(HW_ARCOFI, &cs->HW_Flags))
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return;
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if (test_and_clear_bit(D_RX_MON1, &cs->event))
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arcofi_fsm(cs, ARCOFI_RX_END, NULL);
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if (test_and_clear_bit(D_TX_MON1, &cs->event))
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arcofi_fsm(cs, ARCOFI_TX_END, NULL);
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#endif
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}
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2005-06-26 05:59:18 +08:00
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static void
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2005-04-17 06:20:36 +08:00
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icc_empty_fifo(struct IsdnCardState *cs, int count)
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{
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u_char *ptr;
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if ((cs->debug & L1_DEB_ISAC) && !(cs->debug & L1_DEB_ISAC_FIFO))
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debugl1(cs, "icc_empty_fifo");
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if ((cs->rcvidx + count) >= MAX_DFRAME_LEN_L1) {
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if (cs->debug & L1_DEB_WARN)
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debugl1(cs, "icc_empty_fifo overrun %d",
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cs->rcvidx + count);
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cs->writeisac(cs, ICC_CMDR, 0x80);
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cs->rcvidx = 0;
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return;
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}
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ptr = cs->rcvbuf + cs->rcvidx;
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cs->rcvidx += count;
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cs->readisacfifo(cs, ptr, count);
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cs->writeisac(cs, ICC_CMDR, 0x80);
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if (cs->debug & L1_DEB_ISAC_FIFO) {
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char *t = cs->dlog;
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t += sprintf(t, "icc_empty_fifo cnt %d", count);
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QuickHex(t, ptr, count);
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debugl1(cs, cs->dlog);
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}
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}
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static void
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icc_fill_fifo(struct IsdnCardState *cs)
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{
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int count, more;
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u_char *ptr;
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if ((cs->debug & L1_DEB_ISAC) && !(cs->debug & L1_DEB_ISAC_FIFO))
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debugl1(cs, "icc_fill_fifo");
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if (!cs->tx_skb)
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return;
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count = cs->tx_skb->len;
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if (count <= 0)
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return;
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more = 0;
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if (count > 32) {
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more = !0;
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count = 32;
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}
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ptr = cs->tx_skb->data;
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skb_pull(cs->tx_skb, count);
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cs->tx_cnt += count;
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cs->writeisacfifo(cs, ptr, count);
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cs->writeisac(cs, ICC_CMDR, more ? 0x8 : 0xa);
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if (test_and_set_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) {
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debugl1(cs, "icc_fill_fifo dbusytimer running");
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del_timer(&cs->dbusytimer);
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}
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init_timer(&cs->dbusytimer);
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cs->dbusytimer.expires = jiffies + ((DBUSY_TIMER_VALUE * HZ)/1000);
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add_timer(&cs->dbusytimer);
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if (cs->debug & L1_DEB_ISAC_FIFO) {
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char *t = cs->dlog;
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t += sprintf(t, "icc_fill_fifo cnt %d", count);
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QuickHex(t, ptr, count);
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debugl1(cs, cs->dlog);
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}
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}
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void
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icc_interrupt(struct IsdnCardState *cs, u_char val)
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{
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u_char exval, v1;
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struct sk_buff *skb;
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unsigned int count;
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if (cs->debug & L1_DEB_ISAC)
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debugl1(cs, "ICC interrupt %x", val);
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if (val & 0x80) { /* RME */
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exval = cs->readisac(cs, ICC_RSTA);
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if ((exval & 0x70) != 0x20) {
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if (exval & 0x40) {
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if (cs->debug & L1_DEB_WARN)
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debugl1(cs, "ICC RDO");
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#ifdef ERROR_STATISTIC
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cs->err_rx++;
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#endif
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}
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if (!(exval & 0x20)) {
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if (cs->debug & L1_DEB_WARN)
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debugl1(cs, "ICC CRC error");
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#ifdef ERROR_STATISTIC
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cs->err_crc++;
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#endif
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}
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cs->writeisac(cs, ICC_CMDR, 0x80);
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} else {
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count = cs->readisac(cs, ICC_RBCL) & 0x1f;
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if (count == 0)
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count = 32;
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icc_empty_fifo(cs, count);
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if ((count = cs->rcvidx) > 0) {
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cs->rcvidx = 0;
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if (!(skb = alloc_skb(count, GFP_ATOMIC)))
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printk(KERN_WARNING "HiSax: D receive out of memory\n");
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else {
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memcpy(skb_put(skb, count), cs->rcvbuf, count);
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skb_queue_tail(&cs->rq, skb);
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}
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}
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}
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cs->rcvidx = 0;
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schedule_event(cs, D_RCVBUFREADY);
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}
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if (val & 0x40) { /* RPF */
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icc_empty_fifo(cs, 32);
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}
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if (val & 0x20) { /* RSC */
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/* never */
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if (cs->debug & L1_DEB_WARN)
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debugl1(cs, "ICC RSC interrupt");
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}
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if (val & 0x10) { /* XPR */
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if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags))
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del_timer(&cs->dbusytimer);
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if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags))
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schedule_event(cs, D_CLEARBUSY);
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if (cs->tx_skb) {
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if (cs->tx_skb->len) {
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icc_fill_fifo(cs);
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goto afterXPR;
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} else {
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dev_kfree_skb_irq(cs->tx_skb);
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cs->tx_cnt = 0;
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cs->tx_skb = NULL;
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}
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}
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if ((cs->tx_skb = skb_dequeue(&cs->sq))) {
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cs->tx_cnt = 0;
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icc_fill_fifo(cs);
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} else
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schedule_event(cs, D_XMTBUFREADY);
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}
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afterXPR:
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if (val & 0x04) { /* CISQ */
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exval = cs->readisac(cs, ICC_CIR0);
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if (cs->debug & L1_DEB_ISAC)
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debugl1(cs, "ICC CIR0 %02X", exval );
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if (exval & 2) {
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cs->dc.icc.ph_state = (exval >> 2) & 0xf;
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if (cs->debug & L1_DEB_ISAC)
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debugl1(cs, "ph_state change %x", cs->dc.icc.ph_state);
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schedule_event(cs, D_L1STATECHANGE);
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}
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if (exval & 1) {
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exval = cs->readisac(cs, ICC_CIR1);
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if (cs->debug & L1_DEB_ISAC)
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debugl1(cs, "ICC CIR1 %02X", exval );
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}
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}
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if (val & 0x02) { /* SIN */
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/* never */
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if (cs->debug & L1_DEB_WARN)
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debugl1(cs, "ICC SIN interrupt");
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}
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if (val & 0x01) { /* EXI */
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exval = cs->readisac(cs, ICC_EXIR);
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if (cs->debug & L1_DEB_WARN)
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debugl1(cs, "ICC EXIR %02x", exval);
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if (exval & 0x80) { /* XMR */
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debugl1(cs, "ICC XMR");
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printk(KERN_WARNING "HiSax: ICC XMR\n");
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}
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if (exval & 0x40) { /* XDU */
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debugl1(cs, "ICC XDU");
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printk(KERN_WARNING "HiSax: ICC XDU\n");
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#ifdef ERROR_STATISTIC
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cs->err_tx++;
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#endif
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if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags))
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del_timer(&cs->dbusytimer);
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if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags))
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schedule_event(cs, D_CLEARBUSY);
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if (cs->tx_skb) { /* Restart frame */
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skb_push(cs->tx_skb, cs->tx_cnt);
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cs->tx_cnt = 0;
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icc_fill_fifo(cs);
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} else {
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printk(KERN_WARNING "HiSax: ICC XDU no skb\n");
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debugl1(cs, "ICC XDU no skb");
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}
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}
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if (exval & 0x04) { /* MOS */
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v1 = cs->readisac(cs, ICC_MOSR);
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if (cs->debug & L1_DEB_MONITOR)
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debugl1(cs, "ICC MOSR %02x", v1);
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#if ARCOFI_USE
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if (v1 & 0x08) {
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if (!cs->dc.icc.mon_rx) {
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if (!(cs->dc.icc.mon_rx = kmalloc(MAX_MON_FRAME, GFP_ATOMIC))) {
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if (cs->debug & L1_DEB_WARN)
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debugl1(cs, "ICC MON RX out of memory!");
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cs->dc.icc.mocr &= 0xf0;
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cs->dc.icc.mocr |= 0x0a;
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cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr);
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goto afterMONR0;
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} else
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cs->dc.icc.mon_rxp = 0;
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}
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if (cs->dc.icc.mon_rxp >= MAX_MON_FRAME) {
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cs->dc.icc.mocr &= 0xf0;
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cs->dc.icc.mocr |= 0x0a;
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cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr);
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cs->dc.icc.mon_rxp = 0;
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if (cs->debug & L1_DEB_WARN)
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debugl1(cs, "ICC MON RX overflow!");
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goto afterMONR0;
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}
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cs->dc.icc.mon_rx[cs->dc.icc.mon_rxp++] = cs->readisac(cs, ICC_MOR0);
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if (cs->debug & L1_DEB_MONITOR)
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debugl1(cs, "ICC MOR0 %02x", cs->dc.icc.mon_rx[cs->dc.icc.mon_rxp -1]);
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if (cs->dc.icc.mon_rxp == 1) {
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cs->dc.icc.mocr |= 0x04;
|
|
|
|
cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
afterMONR0:
|
|
|
|
if (v1 & 0x80) {
|
|
|
|
if (!cs->dc.icc.mon_rx) {
|
|
|
|
if (!(cs->dc.icc.mon_rx = kmalloc(MAX_MON_FRAME, GFP_ATOMIC))) {
|
|
|
|
if (cs->debug & L1_DEB_WARN)
|
|
|
|
debugl1(cs, "ICC MON RX out of memory!");
|
|
|
|
cs->dc.icc.mocr &= 0x0f;
|
|
|
|
cs->dc.icc.mocr |= 0xa0;
|
|
|
|
cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr);
|
|
|
|
goto afterMONR1;
|
|
|
|
} else
|
|
|
|
cs->dc.icc.mon_rxp = 0;
|
|
|
|
}
|
|
|
|
if (cs->dc.icc.mon_rxp >= MAX_MON_FRAME) {
|
|
|
|
cs->dc.icc.mocr &= 0x0f;
|
|
|
|
cs->dc.icc.mocr |= 0xa0;
|
|
|
|
cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr);
|
|
|
|
cs->dc.icc.mon_rxp = 0;
|
|
|
|
if (cs->debug & L1_DEB_WARN)
|
|
|
|
debugl1(cs, "ICC MON RX overflow!");
|
|
|
|
goto afterMONR1;
|
|
|
|
}
|
|
|
|
cs->dc.icc.mon_rx[cs->dc.icc.mon_rxp++] = cs->readisac(cs, ICC_MOR1);
|
|
|
|
if (cs->debug & L1_DEB_MONITOR)
|
|
|
|
debugl1(cs, "ICC MOR1 %02x", cs->dc.icc.mon_rx[cs->dc.icc.mon_rxp -1]);
|
|
|
|
cs->dc.icc.mocr |= 0x40;
|
|
|
|
cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr);
|
|
|
|
}
|
|
|
|
afterMONR1:
|
|
|
|
if (v1 & 0x04) {
|
|
|
|
cs->dc.icc.mocr &= 0xf0;
|
|
|
|
cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr);
|
|
|
|
cs->dc.icc.mocr |= 0x0a;
|
|
|
|
cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr);
|
|
|
|
schedule_event(cs, D_RX_MON0);
|
|
|
|
}
|
|
|
|
if (v1 & 0x40) {
|
|
|
|
cs->dc.icc.mocr &= 0x0f;
|
|
|
|
cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr);
|
|
|
|
cs->dc.icc.mocr |= 0xa0;
|
|
|
|
cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr);
|
|
|
|
schedule_event(cs, D_RX_MON1);
|
|
|
|
}
|
|
|
|
if (v1 & 0x02) {
|
|
|
|
if ((!cs->dc.icc.mon_tx) || (cs->dc.icc.mon_txc &&
|
|
|
|
(cs->dc.icc.mon_txp >= cs->dc.icc.mon_txc) &&
|
|
|
|
!(v1 & 0x08))) {
|
|
|
|
cs->dc.icc.mocr &= 0xf0;
|
|
|
|
cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr);
|
|
|
|
cs->dc.icc.mocr |= 0x0a;
|
|
|
|
cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr);
|
|
|
|
if (cs->dc.icc.mon_txc &&
|
|
|
|
(cs->dc.icc.mon_txp >= cs->dc.icc.mon_txc))
|
|
|
|
schedule_event(cs, D_TX_MON0);
|
|
|
|
goto AfterMOX0;
|
|
|
|
}
|
|
|
|
if (cs->dc.icc.mon_txc && (cs->dc.icc.mon_txp >= cs->dc.icc.mon_txc)) {
|
|
|
|
schedule_event(cs, D_TX_MON0);
|
|
|
|
goto AfterMOX0;
|
|
|
|
}
|
|
|
|
cs->writeisac(cs, ICC_MOX0,
|
|
|
|
cs->dc.icc.mon_tx[cs->dc.icc.mon_txp++]);
|
|
|
|
if (cs->debug & L1_DEB_MONITOR)
|
|
|
|
debugl1(cs, "ICC %02x -> MOX0", cs->dc.icc.mon_tx[cs->dc.icc.mon_txp -1]);
|
|
|
|
}
|
|
|
|
AfterMOX0:
|
|
|
|
if (v1 & 0x20) {
|
|
|
|
if ((!cs->dc.icc.mon_tx) || (cs->dc.icc.mon_txc &&
|
|
|
|
(cs->dc.icc.mon_txp >= cs->dc.icc.mon_txc) &&
|
|
|
|
!(v1 & 0x80))) {
|
|
|
|
cs->dc.icc.mocr &= 0x0f;
|
|
|
|
cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr);
|
|
|
|
cs->dc.icc.mocr |= 0xa0;
|
|
|
|
cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr);
|
|
|
|
if (cs->dc.icc.mon_txc &&
|
|
|
|
(cs->dc.icc.mon_txp >= cs->dc.icc.mon_txc))
|
|
|
|
schedule_event(cs, D_TX_MON1);
|
|
|
|
goto AfterMOX1;
|
|
|
|
}
|
|
|
|
if (cs->dc.icc.mon_txc && (cs->dc.icc.mon_txp >= cs->dc.icc.mon_txc)) {
|
|
|
|
schedule_event(cs, D_TX_MON1);
|
|
|
|
goto AfterMOX1;
|
|
|
|
}
|
|
|
|
cs->writeisac(cs, ICC_MOX1,
|
|
|
|
cs->dc.icc.mon_tx[cs->dc.icc.mon_txp++]);
|
|
|
|
if (cs->debug & L1_DEB_MONITOR)
|
|
|
|
debugl1(cs, "ICC %02x -> MOX1", cs->dc.icc.mon_tx[cs->dc.icc.mon_txp -1]);
|
|
|
|
}
|
|
|
|
AfterMOX1:
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
ICC_l1hw(struct PStack *st, int pr, void *arg)
|
|
|
|
{
|
|
|
|
struct IsdnCardState *cs = (struct IsdnCardState *) st->l1.hardware;
|
|
|
|
struct sk_buff *skb = arg;
|
|
|
|
u_long flags;
|
|
|
|
int val;
|
|
|
|
|
|
|
|
switch (pr) {
|
|
|
|
case (PH_DATA |REQUEST):
|
|
|
|
if (cs->debug & DEB_DLOG_HEX)
|
|
|
|
LogFrame(cs, skb->data, skb->len);
|
|
|
|
if (cs->debug & DEB_DLOG_VERBOSE)
|
|
|
|
dlogframe(cs, skb, 0);
|
|
|
|
spin_lock_irqsave(&cs->lock, flags);
|
|
|
|
if (cs->tx_skb) {
|
|
|
|
skb_queue_tail(&cs->sq, skb);
|
|
|
|
#ifdef L2FRAME_DEBUG /* psa */
|
|
|
|
if (cs->debug & L1_DEB_LAPD)
|
|
|
|
Logl2Frame(cs, skb, "PH_DATA Queued", 0);
|
|
|
|
#endif
|
|
|
|
} else {
|
|
|
|
cs->tx_skb = skb;
|
|
|
|
cs->tx_cnt = 0;
|
|
|
|
#ifdef L2FRAME_DEBUG /* psa */
|
|
|
|
if (cs->debug & L1_DEB_LAPD)
|
|
|
|
Logl2Frame(cs, skb, "PH_DATA", 0);
|
|
|
|
#endif
|
|
|
|
icc_fill_fifo(cs);
|
|
|
|
}
|
|
|
|
spin_unlock_irqrestore(&cs->lock, flags);
|
|
|
|
break;
|
|
|
|
case (PH_PULL |INDICATION):
|
|
|
|
spin_lock_irqsave(&cs->lock, flags);
|
|
|
|
if (cs->tx_skb) {
|
|
|
|
if (cs->debug & L1_DEB_WARN)
|
|
|
|
debugl1(cs, " l2l1 tx_skb exist this shouldn't happen");
|
|
|
|
skb_queue_tail(&cs->sq, skb);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
if (cs->debug & DEB_DLOG_HEX)
|
|
|
|
LogFrame(cs, skb->data, skb->len);
|
|
|
|
if (cs->debug & DEB_DLOG_VERBOSE)
|
|
|
|
dlogframe(cs, skb, 0);
|
|
|
|
cs->tx_skb = skb;
|
|
|
|
cs->tx_cnt = 0;
|
|
|
|
#ifdef L2FRAME_DEBUG /* psa */
|
|
|
|
if (cs->debug & L1_DEB_LAPD)
|
|
|
|
Logl2Frame(cs, skb, "PH_DATA_PULLED", 0);
|
|
|
|
#endif
|
|
|
|
icc_fill_fifo(cs);
|
|
|
|
spin_unlock_irqrestore(&cs->lock, flags);
|
|
|
|
break;
|
|
|
|
case (PH_PULL | REQUEST):
|
|
|
|
#ifdef L2FRAME_DEBUG /* psa */
|
|
|
|
if (cs->debug & L1_DEB_LAPD)
|
|
|
|
debugl1(cs, "-> PH_REQUEST_PULL");
|
|
|
|
#endif
|
|
|
|
if (!cs->tx_skb) {
|
|
|
|
test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
|
|
|
|
st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
|
|
|
|
} else
|
|
|
|
test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
|
|
|
|
break;
|
|
|
|
case (HW_RESET | REQUEST):
|
|
|
|
spin_lock_irqsave(&cs->lock, flags);
|
|
|
|
if ((cs->dc.icc.ph_state == ICC_IND_EI1) ||
|
|
|
|
(cs->dc.icc.ph_state == ICC_IND_DR))
|
|
|
|
ph_command(cs, ICC_CMD_DI);
|
|
|
|
else
|
|
|
|
ph_command(cs, ICC_CMD_RES);
|
|
|
|
spin_unlock_irqrestore(&cs->lock, flags);
|
|
|
|
break;
|
|
|
|
case (HW_ENABLE | REQUEST):
|
|
|
|
spin_lock_irqsave(&cs->lock, flags);
|
|
|
|
ph_command(cs, ICC_CMD_DI);
|
|
|
|
spin_unlock_irqrestore(&cs->lock, flags);
|
|
|
|
break;
|
|
|
|
case (HW_INFO1 | REQUEST):
|
|
|
|
spin_lock_irqsave(&cs->lock, flags);
|
|
|
|
ph_command(cs, ICC_CMD_AR);
|
|
|
|
spin_unlock_irqrestore(&cs->lock, flags);
|
|
|
|
break;
|
|
|
|
case (HW_INFO3 | REQUEST):
|
|
|
|
spin_lock_irqsave(&cs->lock, flags);
|
|
|
|
ph_command(cs, ICC_CMD_AI);
|
|
|
|
spin_unlock_irqrestore(&cs->lock, flags);
|
|
|
|
break;
|
|
|
|
case (HW_TESTLOOP | REQUEST):
|
|
|
|
spin_lock_irqsave(&cs->lock, flags);
|
|
|
|
val = 0;
|
|
|
|
if (1 & (long) arg)
|
|
|
|
val |= 0x0c;
|
|
|
|
if (2 & (long) arg)
|
|
|
|
val |= 0x3;
|
|
|
|
if (test_bit(HW_IOM1, &cs->HW_Flags)) {
|
|
|
|
/* IOM 1 Mode */
|
|
|
|
if (!val) {
|
|
|
|
cs->writeisac(cs, ICC_SPCR, 0xa);
|
|
|
|
cs->writeisac(cs, ICC_ADF1, 0x2);
|
|
|
|
} else {
|
|
|
|
cs->writeisac(cs, ICC_SPCR, val);
|
|
|
|
cs->writeisac(cs, ICC_ADF1, 0xa);
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
/* IOM 2 Mode */
|
|
|
|
cs->writeisac(cs, ICC_SPCR, val);
|
|
|
|
if (val)
|
|
|
|
cs->writeisac(cs, ICC_ADF1, 0x8);
|
|
|
|
else
|
|
|
|
cs->writeisac(cs, ICC_ADF1, 0x0);
|
|
|
|
}
|
|
|
|
spin_unlock_irqrestore(&cs->lock, flags);
|
|
|
|
break;
|
|
|
|
case (HW_DEACTIVATE | RESPONSE):
|
|
|
|
skb_queue_purge(&cs->rq);
|
|
|
|
skb_queue_purge(&cs->sq);
|
|
|
|
if (cs->tx_skb) {
|
|
|
|
dev_kfree_skb_any(cs->tx_skb);
|
|
|
|
cs->tx_skb = NULL;
|
|
|
|
}
|
|
|
|
if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags))
|
|
|
|
del_timer(&cs->dbusytimer);
|
|
|
|
if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags))
|
|
|
|
schedule_event(cs, D_CLEARBUSY);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
if (cs->debug & L1_DEB_WARN)
|
|
|
|
debugl1(cs, "icc_l1hw unknown %04x", pr);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2005-06-26 05:59:18 +08:00
|
|
|
static void
|
2005-04-17 06:20:36 +08:00
|
|
|
setstack_icc(struct PStack *st, struct IsdnCardState *cs)
|
|
|
|
{
|
|
|
|
st->l1.l1hw = ICC_l1hw;
|
|
|
|
}
|
|
|
|
|
2005-06-26 05:59:18 +08:00
|
|
|
static void
|
2005-04-17 06:20:36 +08:00
|
|
|
DC_Close_icc(struct IsdnCardState *cs) {
|
2005-11-07 17:01:29 +08:00
|
|
|
kfree(cs->dc.icc.mon_rx);
|
|
|
|
cs->dc.icc.mon_rx = NULL;
|
|
|
|
kfree(cs->dc.icc.mon_tx);
|
|
|
|
cs->dc.icc.mon_tx = NULL;
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
dbusy_timer_handler(struct IsdnCardState *cs)
|
|
|
|
{
|
|
|
|
struct PStack *stptr;
|
|
|
|
int rbch, star;
|
|
|
|
|
|
|
|
if (test_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) {
|
|
|
|
rbch = cs->readisac(cs, ICC_RBCH);
|
|
|
|
star = cs->readisac(cs, ICC_STAR);
|
|
|
|
if (cs->debug)
|
|
|
|
debugl1(cs, "D-Channel Busy RBCH %02x STAR %02x",
|
|
|
|
rbch, star);
|
|
|
|
if (rbch & ICC_RBCH_XAC) { /* D-Channel Busy */
|
|
|
|
test_and_set_bit(FLG_L1_DBUSY, &cs->HW_Flags);
|
|
|
|
stptr = cs->stlist;
|
|
|
|
while (stptr != NULL) {
|
|
|
|
stptr->l1.l1l2(stptr, PH_PAUSE | INDICATION, NULL);
|
|
|
|
stptr = stptr->next;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
/* discard frame; reset transceiver */
|
|
|
|
test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags);
|
|
|
|
if (cs->tx_skb) {
|
|
|
|
dev_kfree_skb_any(cs->tx_skb);
|
|
|
|
cs->tx_cnt = 0;
|
|
|
|
cs->tx_skb = NULL;
|
|
|
|
} else {
|
|
|
|
printk(KERN_WARNING "HiSax: ICC D-Channel Busy no skb\n");
|
|
|
|
debugl1(cs, "D-Channel Busy no skb");
|
|
|
|
}
|
|
|
|
cs->writeisac(cs, ICC_CMDR, 0x01); /* Transmitter reset */
|
IRQ: Maintain regs pointer globally rather than passing to IRQ handlers
Maintain a per-CPU global "struct pt_regs *" variable which can be used instead
of passing regs around manually through all ~1800 interrupt handlers in the
Linux kernel.
The regs pointer is used in few places, but it potentially costs both stack
space and code to pass it around. On the FRV arch, removing the regs parameter
from all the genirq function results in a 20% speed up of the IRQ exit path
(ie: from leaving timer_interrupt() to leaving do_IRQ()).
Where appropriate, an arch may override the generic storage facility and do
something different with the variable. On FRV, for instance, the address is
maintained in GR28 at all times inside the kernel as part of general exception
handling.
Having looked over the code, it appears that the parameter may be handed down
through up to twenty or so layers of functions. Consider a USB character
device attached to a USB hub, attached to a USB controller that posts its
interrupts through a cascaded auxiliary interrupt controller. A character
device driver may want to pass regs to the sysrq handler through the input
layer which adds another few layers of parameter passing.
I've build this code with allyesconfig for x86_64 and i386. I've runtested the
main part of the code on FRV and i386, though I can't test most of the drivers.
I've also done partial conversion for powerpc and MIPS - these at least compile
with minimal configurations.
This will affect all archs. Mostly the changes should be relatively easy.
Take do_IRQ(), store the regs pointer at the beginning, saving the old one:
struct pt_regs *old_regs = set_irq_regs(regs);
And put the old one back at the end:
set_irq_regs(old_regs);
Don't pass regs through to generic_handle_irq() or __do_IRQ().
In timer_interrupt(), this sort of change will be necessary:
- update_process_times(user_mode(regs));
- profile_tick(CPU_PROFILING, regs);
+ update_process_times(user_mode(get_irq_regs()));
+ profile_tick(CPU_PROFILING);
I'd like to move update_process_times()'s use of get_irq_regs() into itself,
except that i386, alone of the archs, uses something other than user_mode().
Some notes on the interrupt handling in the drivers:
(*) input_dev() is now gone entirely. The regs pointer is no longer stored in
the input_dev struct.
(*) finish_unlinks() in drivers/usb/host/ohci-q.c needs checking. It does
something different depending on whether it's been supplied with a regs
pointer or not.
(*) Various IRQ handler function pointers have been moved to type
irq_handler_t.
Signed-Off-By: David Howells <dhowells@redhat.com>
(cherry picked from 1b16e7ac850969f38b375e511e3fa2f474a33867 commit)
2006-10-05 21:55:46 +08:00
|
|
|
cs->irq_func(cs->irq, cs);
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2006-07-10 19:44:11 +08:00
|
|
|
void
|
2005-04-17 06:20:36 +08:00
|
|
|
initicc(struct IsdnCardState *cs)
|
|
|
|
{
|
|
|
|
cs->setstack_d = setstack_icc;
|
|
|
|
cs->DC_Close = DC_Close_icc;
|
|
|
|
cs->dc.icc.mon_tx = NULL;
|
|
|
|
cs->dc.icc.mon_rx = NULL;
|
|
|
|
cs->writeisac(cs, ICC_MASK, 0xff);
|
|
|
|
cs->dc.icc.mocr = 0xaa;
|
|
|
|
if (test_bit(HW_IOM1, &cs->HW_Flags)) {
|
|
|
|
/* IOM 1 Mode */
|
|
|
|
cs->writeisac(cs, ICC_ADF2, 0x0);
|
|
|
|
cs->writeisac(cs, ICC_SPCR, 0xa);
|
|
|
|
cs->writeisac(cs, ICC_ADF1, 0x2);
|
|
|
|
cs->writeisac(cs, ICC_STCR, 0x70);
|
|
|
|
cs->writeisac(cs, ICC_MODE, 0xc9);
|
|
|
|
} else {
|
|
|
|
/* IOM 2 Mode */
|
|
|
|
if (!cs->dc.icc.adf2)
|
|
|
|
cs->dc.icc.adf2 = 0x80;
|
|
|
|
cs->writeisac(cs, ICC_ADF2, cs->dc.icc.adf2);
|
|
|
|
cs->writeisac(cs, ICC_SQXR, 0xa0);
|
|
|
|
cs->writeisac(cs, ICC_SPCR, 0x20);
|
|
|
|
cs->writeisac(cs, ICC_STCR, 0x70);
|
|
|
|
cs->writeisac(cs, ICC_MODE, 0xca);
|
|
|
|
cs->writeisac(cs, ICC_TIMR, 0x00);
|
|
|
|
cs->writeisac(cs, ICC_ADF1, 0x20);
|
|
|
|
}
|
|
|
|
ph_command(cs, ICC_CMD_RES);
|
|
|
|
cs->writeisac(cs, ICC_MASK, 0x0);
|
|
|
|
ph_command(cs, ICC_CMD_DI);
|
|
|
|
}
|
|
|
|
|
2006-07-10 19:44:11 +08:00
|
|
|
void
|
2005-04-17 06:20:36 +08:00
|
|
|
clear_pending_icc_ints(struct IsdnCardState *cs)
|
|
|
|
{
|
|
|
|
int val, eval;
|
|
|
|
|
|
|
|
val = cs->readisac(cs, ICC_STAR);
|
|
|
|
debugl1(cs, "ICC STAR %x", val);
|
|
|
|
val = cs->readisac(cs, ICC_MODE);
|
|
|
|
debugl1(cs, "ICC MODE %x", val);
|
|
|
|
val = cs->readisac(cs, ICC_ADF2);
|
|
|
|
debugl1(cs, "ICC ADF2 %x", val);
|
|
|
|
val = cs->readisac(cs, ICC_ISTA);
|
|
|
|
debugl1(cs, "ICC ISTA %x", val);
|
|
|
|
if (val & 0x01) {
|
|
|
|
eval = cs->readisac(cs, ICC_EXIR);
|
|
|
|
debugl1(cs, "ICC EXIR %x", eval);
|
|
|
|
}
|
|
|
|
val = cs->readisac(cs, ICC_CIR0);
|
|
|
|
debugl1(cs, "ICC CIR0 %x", val);
|
|
|
|
cs->dc.icc.ph_state = (val >> 2) & 0xf;
|
|
|
|
schedule_event(cs, D_L1STATECHANGE);
|
|
|
|
/* Disable all IRQ */
|
|
|
|
cs->writeisac(cs, ICC_MASK, 0xFF);
|
|
|
|
}
|
|
|
|
|
|
|
|
void __devinit
|
|
|
|
setup_icc(struct IsdnCardState *cs)
|
|
|
|
{
|
2006-11-22 22:57:56 +08:00
|
|
|
INIT_WORK(&cs->tqueue, icc_bh);
|
2005-04-17 06:20:36 +08:00
|
|
|
cs->dbusytimer.function = (void *) dbusy_timer_handler;
|
|
|
|
cs->dbusytimer.data = (long) cs;
|
|
|
|
init_timer(&cs->dbusytimer);
|
|
|
|
}
|