2010-03-01 08:18:39 +08:00
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#include "drmP.h"
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#include "drm.h"
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#include "nouveau_drv.h"
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#include "nouveau_drm.h"
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int
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nv50_fb_init(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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2010-06-07 11:59:40 +08:00
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/* Not a clue what this is exactly. Without pointing it at a
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* scratch page, VRAM->GART blits with M2MF (as in DDX DFS)
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* cause IOMMU "read from address 0" errors (rh#561267)
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*/
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nv_wr32(dev, 0x100c08, dev_priv->gart_info.sg_dummy_bus >> 8);
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/* This is needed to get meaningful information from 100c90
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* on traps. No idea what these values mean exactly. */
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2010-03-01 08:18:39 +08:00
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switch (dev_priv->chipset) {
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case 0x50:
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nv_wr32(dev, 0x100c90, 0x0707ff);
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break;
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case 0xa5:
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case 0xa8:
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nv_wr32(dev, 0x100c90, 0x0d0fff);
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break;
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default:
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nv_wr32(dev, 0x100c90, 0x1d07ff);
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break;
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}
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return 0;
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}
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void
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nv50_fb_takedown(struct drm_device *dev)
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{
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}
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