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linux_old1/arch/arm/mach-shmobile/include/mach/irqs.h

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ARM: mach-shmobile: SH-Mobile G3 support. This adds preliminary support for the SH-Mobile G-series. The SH-Mobile G-series is a series of ARM/SH multi-core CPUs that aside from the ARM MPU are primarily composed of existing SH IP blocks. This includes initial support for the SH7367 (SH-Mobile G3) CPU and the G3EVM reference board. Only timer, serial console, and NOR flash are supported at this point. Patches for the interrupt controller, pinmux support, clock framework and runtime pm will be submitted as feature patches on top of this. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2010-02-05 19:14:49 +08:00
#ifndef __ASM_MACH_IRQS_H
#define __ASM_MACH_IRQS_H
sh: intc: unify evt2irq/irq2evt macros for sh and arm Move evt2irq and irq2evt macros definitions out of sh and arm includes into a common location. Signed-off-by: Rob Herring <rob.herring@calxeda.com>
2012-01-18 01:20:23 +08:00
#include <linux/sh_intc.h>
ARM: mach-shmobile: Initial AG5 and AG5EVM support This patch adds initial support for Renesas SH-Mobile AG5. At this point the AG5 CPU support is limited to the ARM core, SCIF serial and a CMT timer together with L2 cache and the GIC. The AG5EVM board also supports Ethernet. Future patches will add support for GPIO, INTCS, CPGA and platform data / driver updates for devices such as IIC, LCDC, FSI, KEYSC, CEU and SDHI among others. The code in entry-macro.S will be cleaned up when the ARM IRQ demux code improvements have been merged. Depends on the AG5EVM mach-type recently registered but not yet present in arch/arm/tools/mach-types. As the AG5EVM board comes with 512MiB memory it is recommended to turn on HIGHMEM. Many thanks to Yoshii-san for initial bring up. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2010-11-17 18:59:31 +08:00
/* GIC */
#define gic_spi(nr) ((nr) + 32)
ARM: shmobile: add gic_iid macro for ICCIAR / interrupt ID R-Car H1 datasheet GIC number is indicating GIC ICCIAR / interrupt ID number, not SPI number, but current marzen board code is using gic_spi() with un-understandable calculation. This patch adds new gic_iid() macro which means ICCIAR / interrupt ID, and used the number currently written on datasheet. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> [ horms+renesas@verge.net.au: Split board-marzen.c portion into a separate patch ] Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-02-25 17:39:44 +08:00
#define gic_iid(nr) (nr) /* ICCIAR / interrupt ID */
ARM: mach-shmobile: Initial AG5 and AG5EVM support This patch adds initial support for Renesas SH-Mobile AG5. At this point the AG5 CPU support is limited to the ARM core, SCIF serial and a CMT timer together with L2 cache and the GIC. The AG5EVM board also supports Ethernet. Future patches will add support for GPIO, INTCS, CPGA and platform data / driver updates for devices such as IIC, LCDC, FSI, KEYSC, CEU and SDHI among others. The code in entry-macro.S will be cleaned up when the ARM IRQ demux code improvements have been merged. Depends on the AG5EVM mach-type recently registered but not yet present in arch/arm/tools/mach-types. As the AG5EVM board comes with 512MiB memory it is recommended to turn on HIGHMEM. Many thanks to Yoshii-san for initial bring up. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2010-11-17 18:59:31 +08:00
ARM: mach-shmobile: add INTCS macros Add SH-Mobile ARM INTCS macros for the INTCS controller. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2010-03-11 13:30:30 +08:00
/* INTCS */
ARM: mach-shmobile: Use 0x3400 as INTCS vector offset Update mach-shmobile to use 0x3400 as INTCS_VECT_BASE. Since the ARM architecture a little while back added support for 10 bit irqs we can now undo the previously merged commit 9b7c23adb350a108737a993c9c781463c1439dc6 and use 0x3400 as INTCS vector base. This change is necessary to avoid overlapping of interrupt ranges so separate IRQ domains can be used for different INTC instances. Without this fix the vectors used by various INTC instances are overlapping on for instance sh7372 which works at the moment but breaks upcoming IRQ domain support. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
2012-03-28 18:22:54 +08:00
#define INTCS_VECT_BASE 0x3400
ARM: mach-shmobile: add INTCS macros Add SH-Mobile ARM INTCS macros for the INTCS controller. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2010-03-11 13:30:30 +08:00
#define INTCS_VECT(n, vect) INTC_VECT((n), INTCS_VECT_BASE + (vect))
#define intcs_evt2irq(evt) evt2irq(INTCS_VECT_BASE + (evt))
ARM: mach-shmobile: SH-Mobile G3 support. This adds preliminary support for the SH-Mobile G-series. The SH-Mobile G-series is a series of ARM/SH multi-core CPUs that aside from the ARM MPU are primarily composed of existing SH IP blocks. This includes initial support for the SH7367 (SH-Mobile G3) CPU and the G3EVM reference board. Only timer, serial console, and NOR flash are supported at this point. Patches for the interrupt controller, pinmux support, clock framework and runtime pm will be submitted as feature patches on top of this. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2010-02-05 19:14:49 +08:00
#endif /* __ASM_MACH_IRQS_H */