117 lines
2.8 KiB
C
117 lines
2.8 KiB
C
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/*
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* Portions copyright (C) 2005-2009 Scientific Atlanta
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* Portions copyright (C) 2009 Cisco Systems, Inc.
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*
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* Modified from arch/mips/kernel/irq-rm7000.c:
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* Copyright (C) 2003 Ralf Baechle
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <asm/irq_cpu.h>
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#include <asm/mipsregs.h>
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#include <asm/system.h>
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#include <asm/mach-powertv/asic_regs.h>
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static inline void unmask_asic_irq(unsigned int irq)
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{
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unsigned long enable_bit;
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enable_bit = (1 << (irq & 0x1f));
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switch (irq >> 5) {
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case 0:
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asic_write(asic_read(ien_int_0) | enable_bit, ien_int_0);
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break;
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case 1:
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asic_write(asic_read(ien_int_1) | enable_bit, ien_int_1);
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break;
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case 2:
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asic_write(asic_read(ien_int_2) | enable_bit, ien_int_2);
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break;
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case 3:
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asic_write(asic_read(ien_int_3) | enable_bit, ien_int_3);
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break;
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default:
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BUG();
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}
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}
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static inline void mask_asic_irq(unsigned int irq)
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{
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unsigned long disable_mask;
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disable_mask = ~(1 << (irq & 0x1f));
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switch (irq >> 5) {
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case 0:
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asic_write(asic_read(ien_int_0) & disable_mask, ien_int_0);
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break;
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case 1:
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asic_write(asic_read(ien_int_1) & disable_mask, ien_int_1);
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break;
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case 2:
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asic_write(asic_read(ien_int_2) & disable_mask, ien_int_2);
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break;
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case 3:
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asic_write(asic_read(ien_int_3) & disable_mask, ien_int_3);
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break;
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default:
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BUG();
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}
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}
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static struct irq_chip asic_irq_chip = {
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.name = "ASIC Level",
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.ack = mask_asic_irq,
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.mask = mask_asic_irq,
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.mask_ack = mask_asic_irq,
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.unmask = unmask_asic_irq,
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.eoi = unmask_asic_irq,
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};
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void __init asic_irq_init(void)
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{
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int i;
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/* set priority to 0 */
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write_c0_status(read_c0_status() & ~(0x0000fc00));
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asic_write(0, ien_int_0);
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asic_write(0, ien_int_1);
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asic_write(0, ien_int_2);
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asic_write(0, ien_int_3);
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asic_write(0x0fffffff, int_level_3_3);
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asic_write(0xffffffff, int_level_3_2);
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asic_write(0xffffffff, int_level_3_1);
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asic_write(0xffffffff, int_level_3_0);
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asic_write(0xffffffff, int_level_2_3);
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asic_write(0xffffffff, int_level_2_2);
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asic_write(0xffffffff, int_level_2_1);
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asic_write(0xffffffff, int_level_2_0);
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asic_write(0xffffffff, int_level_1_3);
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asic_write(0xffffffff, int_level_1_2);
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asic_write(0xffffffff, int_level_1_1);
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asic_write(0xffffffff, int_level_1_0);
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asic_write(0xffffffff, int_level_0_3);
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asic_write(0xffffffff, int_level_0_2);
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asic_write(0xffffffff, int_level_0_1);
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asic_write(0xffffffff, int_level_0_0);
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asic_write(0xf, int_int_scan);
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/*
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* Initialize interrupt handlers.
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*/
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for (i = 0; i < NR_IRQS; i++)
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set_irq_chip_and_handler(i, &asic_irq_chip, handle_level_irq);
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}
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