2005-04-17 06:20:36 +08:00
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/* $Id: os_4bri.c,v 1.28.4.4 2005/02/11 19:40:25 armin Exp $ */
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#include "platform.h"
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#include "debuglib.h"
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#include "cardtype.h"
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#include "pc.h"
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#include "pr_pc.h"
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#include "di_defs.h"
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#include "dsp_defs.h"
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#include "di.h"
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#include "io.h"
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#include "xdi_msg.h"
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#include "xdi_adapter.h"
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#include "os_4bri.h"
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#include "diva_pci.h"
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#include "mi_pc.h"
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#include "dsrv4bri.h"
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2006-01-08 17:05:16 +08:00
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#include "helpers.h"
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2005-04-17 06:20:36 +08:00
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static void *diva_xdiLoadFileFile = NULL;
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static dword diva_xdiLoadFileLength = 0;
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/*
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** IMPORTS
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*/
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extern void prepare_qBri_functions(PISDN_ADAPTER IoAdapter);
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extern void prepare_qBri2_functions(PISDN_ADAPTER IoAdapter);
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extern void diva_xdi_display_adapter_features(int card);
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2012-02-20 11:52:38 +08:00
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extern void diva_add_slave_adapter(diva_os_xdi_adapter_t *a);
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2005-04-17 06:20:36 +08:00
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extern int qBri_FPGA_download(PISDN_ADAPTER IoAdapter);
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extern void start_qBri_hardware(PISDN_ADAPTER IoAdapter);
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2012-02-20 11:52:38 +08:00
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extern int diva_card_read_xlog(diva_os_xdi_adapter_t *a);
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2005-04-17 06:20:36 +08:00
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/*
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** LOCALS
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*/
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static unsigned long _4bri_bar_length[4] = {
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0x100,
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0x100, /* I/O */
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MQ_MEMORY_SIZE,
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0x2000
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};
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static unsigned long _4bri_v2_bar_length[4] = {
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0x100,
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0x100, /* I/O */
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MQ2_MEMORY_SIZE,
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0x10000
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};
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static unsigned long _4bri_v2_bri_bar_length[4] = {
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0x100,
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0x100, /* I/O */
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BRI2_MEMORY_SIZE,
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0x10000
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};
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2012-02-20 11:52:38 +08:00
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static int diva_4bri_cleanup_adapter(diva_os_xdi_adapter_t *a);
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static int _4bri_get_serial_number(diva_os_xdi_adapter_t *a);
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2005-04-17 06:20:36 +08:00
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static int diva_4bri_cmd_card_proc(struct _diva_os_xdi_adapter *a,
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2012-02-20 11:52:38 +08:00
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diva_xdi_um_cfg_cmd_t *cmd,
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2005-04-17 06:20:36 +08:00
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int length);
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2012-02-20 11:52:38 +08:00
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static int diva_4bri_cleanup_slave_adapters(diva_os_xdi_adapter_t *a);
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static int diva_4bri_write_fpga_image(diva_os_xdi_adapter_t *a,
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byte *data, dword length);
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2005-04-17 06:20:36 +08:00
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static int diva_4bri_reset_adapter(PISDN_ADAPTER IoAdapter);
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static int diva_4bri_write_sdram_block(PISDN_ADAPTER IoAdapter,
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dword address,
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2012-02-20 11:52:38 +08:00
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const byte *data,
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2005-04-17 06:20:36 +08:00
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dword length, dword limit);
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static int diva_4bri_start_adapter(PISDN_ADAPTER IoAdapter,
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dword start_address, dword features);
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static int check_qBri_interrupt(PISDN_ADAPTER IoAdapter);
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2012-02-20 11:52:38 +08:00
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static int diva_4bri_stop_adapter(diva_os_xdi_adapter_t *a);
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2005-04-17 06:20:36 +08:00
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static int _4bri_is_rev_2_card(int card_ordinal)
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{
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switch (card_ordinal) {
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case CARDTYPE_DIVASRV_Q_8M_V2_PCI:
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case CARDTYPE_DIVASRV_VOICE_Q_8M_V2_PCI:
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case CARDTYPE_DIVASRV_B_2M_V2_PCI:
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case CARDTYPE_DIVASRV_B_2F_PCI:
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case CARDTYPE_DIVASRV_VOICE_B_2M_V2_PCI:
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return (1);
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}
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return (0);
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}
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static int _4bri_is_rev_2_bri_card(int card_ordinal)
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{
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switch (card_ordinal) {
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case CARDTYPE_DIVASRV_B_2M_V2_PCI:
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case CARDTYPE_DIVASRV_B_2F_PCI:
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case CARDTYPE_DIVASRV_VOICE_B_2M_V2_PCI:
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return (1);
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}
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return (0);
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}
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static void diva_4bri_set_addresses(diva_os_xdi_adapter_t *a)
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{
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dword offset = a->resources.pci.qoffset;
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dword c_offset = offset * a->xdi_adapter.ControllerNumber;
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a->resources.pci.mem_type_id[MEM_TYPE_RAM] = 2;
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a->resources.pci.mem_type_id[MEM_TYPE_ADDRESS] = 2;
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a->resources.pci.mem_type_id[MEM_TYPE_CONTROL] = 2;
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a->resources.pci.mem_type_id[MEM_TYPE_RESET] = 0;
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a->resources.pci.mem_type_id[MEM_TYPE_CTLREG] = 3;
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a->resources.pci.mem_type_id[MEM_TYPE_PROM] = 0;
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/*
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2012-02-20 11:52:38 +08:00
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Set up hardware related pointers
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*/
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2005-04-17 06:20:36 +08:00
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a->xdi_adapter.Address = a->resources.pci.addr[2]; /* BAR2 SDRAM */
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a->xdi_adapter.Address += c_offset;
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a->xdi_adapter.Control = a->resources.pci.addr[2]; /* BAR2 SDRAM */
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a->xdi_adapter.ram = a->resources.pci.addr[2]; /* BAR2 SDRAM */
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a->xdi_adapter.ram += c_offset + (offset - MQ_SHARED_RAM_SIZE);
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2012-02-20 11:52:38 +08:00
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2005-04-17 06:20:36 +08:00
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a->xdi_adapter.reset = a->resources.pci.addr[0]; /* BAR0 CONFIG */
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/*
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2012-02-20 11:52:38 +08:00
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ctlReg contains the register address for the MIPS CPU reset control
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*/
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2005-04-17 06:20:36 +08:00
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a->xdi_adapter.ctlReg = a->resources.pci.addr[3]; /* BAR3 CNTRL */
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/*
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2012-02-20 11:52:38 +08:00
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prom contains the register address for FPGA and EEPROM programming
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*/
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2005-04-17 06:20:36 +08:00
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a->xdi_adapter.prom = &a->xdi_adapter.reset[0x6E];
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}
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/*
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** BAR0 - MEM - 0x100 - CONFIG MEM
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** BAR1 - I/O - 0x100 - UNUSED
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** BAR2 - MEM - MQ_MEMORY_SIZE (MQ2_MEMORY_SIZE on Rev.2) - SDRAM
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** BAR3 - MEM - 0x2000 (0x10000 on Rev.2) - CNTRL
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**
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** Called by master adapter, that will initialize and add slave adapters
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*/
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2012-02-20 11:52:38 +08:00
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int diva_4bri_init_card(diva_os_xdi_adapter_t *a)
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2005-04-17 06:20:36 +08:00
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{
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int bar, i;
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byte __iomem *p;
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PADAPTER_LIST_ENTRY quadro_list;
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diva_os_xdi_adapter_t *diva_current;
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diva_os_xdi_adapter_t *adapter_list[4];
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PISDN_ADAPTER Slave;
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2009-07-25 00:26:08 +08:00
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unsigned long bar_length[ARRAY_SIZE(_4bri_bar_length)];
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2005-04-17 06:20:36 +08:00
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int v2 = _4bri_is_rev_2_card(a->CardOrdinal);
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int tasks = _4bri_is_rev_2_bri_card(a->CardOrdinal) ? 1 : MQ_INSTANCE_COUNT;
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int factor = (tasks == 1) ? 1 : 2;
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if (v2) {
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if (_4bri_is_rev_2_bri_card(a->CardOrdinal)) {
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memcpy(bar_length, _4bri_v2_bri_bar_length,
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sizeof(bar_length));
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} else {
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memcpy(bar_length, _4bri_v2_bar_length,
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sizeof(bar_length));
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}
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} else {
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memcpy(bar_length, _4bri_bar_length, sizeof(bar_length));
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}
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DBG_TRC(("SDRAM_LENGTH=%08x, tasks=%d, factor=%d",
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bar_length[2], tasks, factor))
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2012-02-20 11:52:38 +08:00
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/*
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Get Serial Number
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The serial number of 4BRI is accessible in accordance with PCI spec
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via command register located in configuration space, also we do not
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have to map any BAR before we can access it
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*/
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if (!_4bri_get_serial_number(a)) {
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DBG_ERR(("A: 4BRI can't get Serial Number"))
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diva_4bri_cleanup_adapter(a);
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return (-1);
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}
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2005-04-17 06:20:36 +08:00
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/*
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2012-02-20 11:52:38 +08:00
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Set properties
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*/
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2005-04-17 06:20:36 +08:00
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a->xdi_adapter.Properties = CardProperties[a->CardOrdinal];
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DBG_LOG(("Load %s, SN:%ld, bus:%02x, func:%02x",
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a->xdi_adapter.Properties.Name,
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a->xdi_adapter.serialNo,
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a->resources.pci.bus, a->resources.pci.func))
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2012-02-20 11:52:38 +08:00
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/*
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First initialization step: get and check hardware resoures.
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Do not map resources and do not access card at this step
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*/
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for (bar = 0; bar < 4; bar++) {
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a->resources.pci.bar[bar] =
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divasa_get_pci_bar(a->resources.pci.bus,
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a->resources.pci.func, bar,
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a->resources.pci.hdev);
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if (!a->resources.pci.bar[bar]
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|| (a->resources.pci.bar[bar] == 0xFFFFFFF0)) {
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DBG_ERR(
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("A: invalid bar[%d]=%08x", bar,
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a->resources.pci.bar[bar]))
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return (-1);
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}
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2005-04-17 06:20:36 +08:00
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}
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a->resources.pci.irq =
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2012-02-20 11:52:38 +08:00
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(byte) divasa_get_pci_irq(a->resources.pci.bus,
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a->resources.pci.func,
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a->resources.pci.hdev);
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2005-04-17 06:20:36 +08:00
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if (!a->resources.pci.irq) {
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DBG_ERR(("A: invalid irq"));
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return (-1);
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}
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a->xdi_adapter.sdram_bar = a->resources.pci.bar[2];
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/*
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2012-02-20 11:52:38 +08:00
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Map all MEMORY BAR's
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*/
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2005-04-17 06:20:36 +08:00
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for (bar = 0; bar < 4; bar++) {
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if (bar != 1) { /* ignore I/O */
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a->resources.pci.addr[bar] =
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2012-02-20 11:52:38 +08:00
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divasa_remap_pci_bar(a, bar, a->resources.pci.bar[bar],
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bar_length[bar]);
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2005-04-17 06:20:36 +08:00
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if (!a->resources.pci.addr[bar]) {
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DBG_ERR(("A: 4BRI: can't map bar[%d]", bar))
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2012-02-20 11:52:38 +08:00
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diva_4bri_cleanup_adapter(a);
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2005-04-17 06:20:36 +08:00
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return (-1);
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}
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}
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}
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/*
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2012-02-20 11:52:38 +08:00
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Register I/O port
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*/
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2005-04-17 06:20:36 +08:00
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sprintf(&a->port_name[0], "DIVA 4BRI %ld", (long) a->xdi_adapter.serialNo);
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if (diva_os_register_io_port(a, 1, a->resources.pci.bar[1],
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bar_length[1], &a->port_name[0], 1)) {
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DBG_ERR(("A: 4BRI: can't register bar[1]"))
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2012-02-20 11:52:38 +08:00
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diva_4bri_cleanup_adapter(a);
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2005-04-17 06:20:36 +08:00
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return (-1);
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}
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a->resources.pci.addr[1] =
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(void *) (unsigned long) a->resources.pci.bar[1];
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/*
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2012-02-20 11:52:38 +08:00
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Set cleanup pointer for base adapter only, so slave adapter
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will be unable to get cleanup
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*/
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2005-04-17 06:20:36 +08:00
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a->interface.cleanup_adapter_proc = diva_4bri_cleanup_adapter;
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/*
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2012-02-20 11:52:38 +08:00
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Create slave adapters
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*/
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2005-04-17 06:20:36 +08:00
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if (tasks > 1) {
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if (!(a->slave_adapters[0] =
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2012-02-20 11:52:38 +08:00
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(diva_os_xdi_adapter_t *) diva_os_malloc(0, sizeof(*a))))
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2005-04-17 06:20:36 +08:00
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{
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diva_4bri_cleanup_adapter(a);
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return (-1);
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}
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if (!(a->slave_adapters[1] =
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2012-02-20 11:52:38 +08:00
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(diva_os_xdi_adapter_t *) diva_os_malloc(0, sizeof(*a))))
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2005-04-17 06:20:36 +08:00
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{
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diva_os_free(0, a->slave_adapters[0]);
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a->slave_adapters[0] = NULL;
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diva_4bri_cleanup_adapter(a);
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return (-1);
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}
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if (!(a->slave_adapters[2] =
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2012-02-20 11:52:38 +08:00
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(diva_os_xdi_adapter_t *) diva_os_malloc(0, sizeof(*a))))
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2005-04-17 06:20:36 +08:00
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{
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diva_os_free(0, a->slave_adapters[0]);
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diva_os_free(0, a->slave_adapters[1]);
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a->slave_adapters[0] = NULL;
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a->slave_adapters[1] = NULL;
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diva_4bri_cleanup_adapter(a);
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return (-1);
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}
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memset(a->slave_adapters[0], 0x00, sizeof(*a));
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memset(a->slave_adapters[1], 0x00, sizeof(*a));
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memset(a->slave_adapters[2], 0x00, sizeof(*a));
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}
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adapter_list[0] = a;
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adapter_list[1] = a->slave_adapters[0];
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adapter_list[2] = a->slave_adapters[1];
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adapter_list[3] = a->slave_adapters[2];
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/*
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2012-02-20 11:52:38 +08:00
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Allocate slave list
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*/
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2005-04-17 06:20:36 +08:00
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quadro_list =
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2012-02-20 11:52:38 +08:00
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(PADAPTER_LIST_ENTRY) diva_os_malloc(0, sizeof(*quadro_list));
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2005-04-17 06:20:36 +08:00
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if (!(a->slave_list = quadro_list)) {
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|
|
for (i = 0; i < (tasks - 1); i++) {
|
|
|
|
diva_os_free(0, a->slave_adapters[i]);
|
|
|
|
a->slave_adapters[i] = NULL;
|
|
|
|
}
|
|
|
|
diva_4bri_cleanup_adapter(a);
|
|
|
|
return (-1);
|
|
|
|
}
|
|
|
|
memset(quadro_list, 0x00, sizeof(*quadro_list));
|
|
|
|
|
|
|
|
/*
|
2012-02-20 11:52:38 +08:00
|
|
|
Set interfaces
|
|
|
|
*/
|
2005-04-17 06:20:36 +08:00
|
|
|
a->xdi_adapter.QuadroList = quadro_list;
|
|
|
|
for (i = 0; i < tasks; i++) {
|
|
|
|
adapter_list[i]->xdi_adapter.ControllerNumber = i;
|
|
|
|
adapter_list[i]->xdi_adapter.tasks = tasks;
|
|
|
|
quadro_list->QuadroAdapter[i] =
|
2012-02-20 11:52:38 +08:00
|
|
|
&adapter_list[i]->xdi_adapter;
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
for (i = 0; i < tasks; i++) {
|
|
|
|
diva_current = adapter_list[i];
|
|
|
|
|
|
|
|
diva_current->dsp_mask = 0x00000003;
|
|
|
|
|
|
|
|
diva_current->xdi_adapter.a.io =
|
2012-02-20 11:52:38 +08:00
|
|
|
&diva_current->xdi_adapter;
|
2005-04-17 06:20:36 +08:00
|
|
|
diva_current->xdi_adapter.DIRequest = request;
|
|
|
|
diva_current->interface.cmd_proc = diva_4bri_cmd_card_proc;
|
|
|
|
diva_current->xdi_adapter.Properties =
|
2012-02-20 11:52:38 +08:00
|
|
|
CardProperties[a->CardOrdinal];
|
2005-04-17 06:20:36 +08:00
|
|
|
diva_current->CardOrdinal = a->CardOrdinal;
|
|
|
|
|
|
|
|
diva_current->xdi_adapter.Channels =
|
2012-02-20 11:52:38 +08:00
|
|
|
CardProperties[a->CardOrdinal].Channels;
|
2005-04-17 06:20:36 +08:00
|
|
|
diva_current->xdi_adapter.e_max =
|
2012-02-20 11:52:38 +08:00
|
|
|
CardProperties[a->CardOrdinal].E_info;
|
2005-04-17 06:20:36 +08:00
|
|
|
diva_current->xdi_adapter.e_tbl =
|
2012-02-20 11:52:38 +08:00
|
|
|
diva_os_malloc(0,
|
|
|
|
diva_current->xdi_adapter.e_max *
|
|
|
|
sizeof(E_INFO));
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
if (!diva_current->xdi_adapter.e_tbl) {
|
|
|
|
diva_4bri_cleanup_slave_adapters(a);
|
|
|
|
diva_4bri_cleanup_adapter(a);
|
|
|
|
for (i = 1; i < (tasks - 1); i++) {
|
|
|
|
diva_os_free(0, adapter_list[i]);
|
|
|
|
}
|
|
|
|
return (-1);
|
|
|
|
}
|
|
|
|
memset(diva_current->xdi_adapter.e_tbl, 0x00,
|
|
|
|
diva_current->xdi_adapter.e_max * sizeof(E_INFO));
|
|
|
|
|
|
|
|
if (diva_os_initialize_spin_lock(&diva_current->xdi_adapter.isr_spin_lock, "isr")) {
|
|
|
|
diva_4bri_cleanup_slave_adapters(a);
|
|
|
|
diva_4bri_cleanup_adapter(a);
|
|
|
|
for (i = 1; i < (tasks - 1); i++) {
|
|
|
|
diva_os_free(0, adapter_list[i]);
|
|
|
|
}
|
|
|
|
return (-1);
|
|
|
|
}
|
|
|
|
if (diva_os_initialize_spin_lock(&diva_current->xdi_adapter.data_spin_lock, "data")) {
|
|
|
|
diva_4bri_cleanup_slave_adapters(a);
|
|
|
|
diva_4bri_cleanup_adapter(a);
|
|
|
|
for (i = 1; i < (tasks - 1); i++) {
|
|
|
|
diva_os_free(0, adapter_list[i]);
|
|
|
|
}
|
|
|
|
return (-1);
|
|
|
|
}
|
|
|
|
|
|
|
|
strcpy(diva_current->xdi_adapter.req_soft_isr. dpc_thread_name, "kdivas4brid");
|
|
|
|
|
2012-02-20 11:52:38 +08:00
|
|
|
if (diva_os_initialize_soft_isr(&diva_current->xdi_adapter.req_soft_isr, DIDpcRoutine,
|
|
|
|
&diva_current->xdi_adapter)) {
|
2005-04-17 06:20:36 +08:00
|
|
|
diva_4bri_cleanup_slave_adapters(a);
|
|
|
|
diva_4bri_cleanup_adapter(a);
|
|
|
|
for (i = 1; i < (tasks - 1); i++) {
|
|
|
|
diva_os_free(0, adapter_list[i]);
|
|
|
|
}
|
|
|
|
return (-1);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
2012-02-20 11:52:38 +08:00
|
|
|
Do not initialize second DPC - only one thread will be created
|
|
|
|
*/
|
2005-04-17 06:20:36 +08:00
|
|
|
diva_current->xdi_adapter.isr_soft_isr.object =
|
2012-02-20 11:52:38 +08:00
|
|
|
diva_current->xdi_adapter.req_soft_isr.object;
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
if (v2) {
|
|
|
|
prepare_qBri2_functions(&a->xdi_adapter);
|
|
|
|
} else {
|
|
|
|
prepare_qBri_functions(&a->xdi_adapter);
|
|
|
|
}
|
|
|
|
|
|
|
|
for (i = 0; i < tasks; i++) {
|
|
|
|
diva_current = adapter_list[i];
|
|
|
|
if (i)
|
|
|
|
memcpy(&diva_current->resources, &a->resources, sizeof(divas_card_resources_t));
|
2012-02-20 11:52:38 +08:00
|
|
|
diva_current->resources.pci.qoffset = (a->xdi_adapter.MemorySize >> factor);
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
2012-02-20 11:52:38 +08:00
|
|
|
Set up hardware related pointers
|
|
|
|
*/
|
2005-04-17 06:20:36 +08:00
|
|
|
a->xdi_adapter.cfg = (void *) (unsigned long) a->resources.pci.bar[0]; /* BAR0 CONFIG */
|
|
|
|
a->xdi_adapter.port = (void *) (unsigned long) a->resources.pci.bar[1]; /* BAR1 */
|
|
|
|
a->xdi_adapter.ctlReg = (void *) (unsigned long) a->resources.pci.bar[3]; /* BAR3 CNTRL */
|
|
|
|
|
|
|
|
for (i = 0; i < tasks; i++) {
|
|
|
|
diva_current = adapter_list[i];
|
|
|
|
diva_4bri_set_addresses(diva_current);
|
|
|
|
Slave = a->xdi_adapter.QuadroList->QuadroAdapter[i];
|
|
|
|
Slave->MultiMaster = &a->xdi_adapter;
|
|
|
|
Slave->sdram_bar = a->xdi_adapter.sdram_bar;
|
|
|
|
if (i) {
|
|
|
|
Slave->serialNo = ((dword) (Slave->ControllerNumber << 24)) |
|
2012-02-20 11:52:38 +08:00
|
|
|
a->xdi_adapter.serialNo;
|
2005-04-17 06:20:36 +08:00
|
|
|
Slave->cardType = a->xdi_adapter.cardType;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
2012-02-20 11:52:38 +08:00
|
|
|
reset contains the base address for the PLX 9054 register set
|
|
|
|
*/
|
2005-04-17 06:20:36 +08:00
|
|
|
p = DIVA_OS_MEM_ATTACH_RESET(&a->xdi_adapter);
|
|
|
|
WRITE_BYTE(&p[PLX9054_INTCSR], 0x00); /* disable PCI interrupts */
|
|
|
|
DIVA_OS_MEM_DETACH_RESET(&a->xdi_adapter, p);
|
|
|
|
|
|
|
|
/*
|
2012-02-20 11:52:38 +08:00
|
|
|
Set IRQ handler
|
|
|
|
*/
|
2005-04-17 06:20:36 +08:00
|
|
|
a->xdi_adapter.irq_info.irq_nr = a->resources.pci.irq;
|
|
|
|
sprintf(a->xdi_adapter.irq_info.irq_name, "DIVA 4BRI %ld",
|
|
|
|
(long) a->xdi_adapter.serialNo);
|
|
|
|
|
|
|
|
if (diva_os_register_irq(a, a->xdi_adapter.irq_info.irq_nr,
|
|
|
|
a->xdi_adapter.irq_info.irq_name)) {
|
|
|
|
diva_4bri_cleanup_slave_adapters(a);
|
|
|
|
diva_4bri_cleanup_adapter(a);
|
|
|
|
for (i = 1; i < (tasks - 1); i++) {
|
|
|
|
diva_os_free(0, adapter_list[i]);
|
|
|
|
}
|
|
|
|
return (-1);
|
|
|
|
}
|
|
|
|
|
|
|
|
a->xdi_adapter.irq_info.registered = 1;
|
|
|
|
|
|
|
|
/*
|
2012-02-20 11:52:38 +08:00
|
|
|
Add three slave adapters
|
|
|
|
*/
|
2005-04-17 06:20:36 +08:00
|
|
|
if (tasks > 1) {
|
|
|
|
diva_add_slave_adapter(adapter_list[1]);
|
|
|
|
diva_add_slave_adapter(adapter_list[2]);
|
|
|
|
diva_add_slave_adapter(adapter_list[3]);
|
|
|
|
}
|
|
|
|
|
|
|
|
diva_log_info("%s IRQ:%d SerNo:%d", a->xdi_adapter.Properties.Name,
|
|
|
|
a->resources.pci.irq, a->xdi_adapter.serialNo);
|
|
|
|
|
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
** Cleanup function will be called for master adapter only
|
2006-11-30 12:24:39 +08:00
|
|
|
** this is guaranteed by design: cleanup callback is set
|
2005-04-17 06:20:36 +08:00
|
|
|
** by master adapter only
|
|
|
|
*/
|
2012-02-20 11:52:38 +08:00
|
|
|
static int diva_4bri_cleanup_adapter(diva_os_xdi_adapter_t *a)
|
2005-04-17 06:20:36 +08:00
|
|
|
{
|
|
|
|
int bar;
|
|
|
|
|
|
|
|
/*
|
2012-02-20 11:52:38 +08:00
|
|
|
Stop adapter if running
|
|
|
|
*/
|
2005-04-17 06:20:36 +08:00
|
|
|
if (a->xdi_adapter.Initialized) {
|
|
|
|
diva_4bri_stop_adapter(a);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
2012-02-20 11:52:38 +08:00
|
|
|
Remove IRQ handler
|
|
|
|
*/
|
2005-04-17 06:20:36 +08:00
|
|
|
if (a->xdi_adapter.irq_info.registered) {
|
|
|
|
diva_os_remove_irq(a, a->xdi_adapter.irq_info.irq_nr);
|
|
|
|
}
|
|
|
|
a->xdi_adapter.irq_info.registered = 0;
|
|
|
|
|
|
|
|
/*
|
2012-02-20 11:52:38 +08:00
|
|
|
Free DPC's and spin locks on all adapters
|
|
|
|
*/
|
2005-04-17 06:20:36 +08:00
|
|
|
diva_4bri_cleanup_slave_adapters(a);
|
|
|
|
|
|
|
|
/*
|
2012-02-20 11:52:38 +08:00
|
|
|
Unmap all BARS
|
|
|
|
*/
|
2005-04-17 06:20:36 +08:00
|
|
|
for (bar = 0; bar < 4; bar++) {
|
|
|
|
if (bar != 1) {
|
|
|
|
if (a->resources.pci.bar[bar]
|
|
|
|
&& a->resources.pci.addr[bar]) {
|
|
|
|
divasa_unmap_pci_bar(a->resources.pci.addr[bar]);
|
|
|
|
a->resources.pci.bar[bar] = 0;
|
|
|
|
a->resources.pci.addr[bar] = NULL;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
2012-02-20 11:52:38 +08:00
|
|
|
Unregister I/O
|
|
|
|
*/
|
2005-04-17 06:20:36 +08:00
|
|
|
if (a->resources.pci.bar[1] && a->resources.pci.addr[1]) {
|
|
|
|
diva_os_register_io_port(a, 0, a->resources.pci.bar[1],
|
|
|
|
_4bri_is_rev_2_card(a->
|
|
|
|
CardOrdinal) ?
|
|
|
|
_4bri_v2_bar_length[1] :
|
|
|
|
_4bri_bar_length[1],
|
|
|
|
&a->port_name[0], 1);
|
|
|
|
a->resources.pci.bar[1] = 0;
|
|
|
|
a->resources.pci.addr[1] = NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (a->slave_list) {
|
|
|
|
diva_os_free(0, a->slave_list);
|
|
|
|
a->slave_list = NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
2012-02-20 11:52:38 +08:00
|
|
|
static int _4bri_get_serial_number(diva_os_xdi_adapter_t *a)
|
2005-04-17 06:20:36 +08:00
|
|
|
{
|
|
|
|
dword data[64];
|
|
|
|
dword serNo;
|
|
|
|
word addr, status, i, j;
|
|
|
|
byte Bus, Slot;
|
|
|
|
void *hdev;
|
|
|
|
|
|
|
|
Bus = a->resources.pci.bus;
|
|
|
|
Slot = a->resources.pci.func;
|
|
|
|
hdev = a->resources.pci.hdev;
|
|
|
|
|
|
|
|
for (i = 0; i < 64; ++i) {
|
|
|
|
addr = i * 4;
|
|
|
|
for (j = 0; j < 5; ++j) {
|
|
|
|
PCIwrite(Bus, Slot, 0x4E, &addr, sizeof(addr),
|
|
|
|
hdev);
|
|
|
|
diva_os_wait(1);
|
|
|
|
PCIread(Bus, Slot, 0x4E, &status, sizeof(status),
|
|
|
|
hdev);
|
|
|
|
if (status & 0x8000)
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
if (j >= 5) {
|
|
|
|
DBG_ERR(("EEPROM[%d] read failed (0x%x)", i * 4, addr))
|
2012-02-20 11:52:38 +08:00
|
|
|
return (0);
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
|
|
|
PCIread(Bus, Slot, 0x50, &data[i], sizeof(data[i]), hdev);
|
|
|
|
}
|
|
|
|
DBG_BLK(((char *) &data[0], sizeof(data)))
|
|
|
|
|
2012-02-20 11:52:38 +08:00
|
|
|
serNo = data[32];
|
2005-04-17 06:20:36 +08:00
|
|
|
if (serNo == 0 || serNo == 0xffffffff)
|
|
|
|
serNo = data[63];
|
|
|
|
|
|
|
|
if (!serNo) {
|
|
|
|
DBG_LOG(("W: Serial Number == 0, create one serial number"));
|
|
|
|
serNo = a->resources.pci.bar[1] & 0xffff0000;
|
|
|
|
serNo |= a->resources.pci.bus << 8;
|
|
|
|
serNo |= a->resources.pci.func;
|
|
|
|
}
|
|
|
|
|
|
|
|
a->xdi_adapter.serialNo = serNo;
|
|
|
|
|
|
|
|
DBG_REG(("Serial No. : %ld", a->xdi_adapter.serialNo))
|
|
|
|
|
2012-02-20 11:52:38 +08:00
|
|
|
return (serNo);
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
** Release resources of slave adapters
|
|
|
|
*/
|
2012-02-20 11:52:38 +08:00
|
|
|
static int diva_4bri_cleanup_slave_adapters(diva_os_xdi_adapter_t *a)
|
2005-04-17 06:20:36 +08:00
|
|
|
{
|
|
|
|
diva_os_xdi_adapter_t *adapter_list[4];
|
|
|
|
diva_os_xdi_adapter_t *diva_current;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
adapter_list[0] = a;
|
|
|
|
adapter_list[1] = a->slave_adapters[0];
|
|
|
|
adapter_list[2] = a->slave_adapters[1];
|
|
|
|
adapter_list[3] = a->slave_adapters[2];
|
|
|
|
|
|
|
|
for (i = 0; i < a->xdi_adapter.tasks; i++) {
|
|
|
|
diva_current = adapter_list[i];
|
|
|
|
if (diva_current) {
|
|
|
|
diva_os_destroy_spin_lock(&diva_current->
|
|
|
|
xdi_adapter.
|
|
|
|
isr_spin_lock, "unload");
|
|
|
|
diva_os_destroy_spin_lock(&diva_current->
|
|
|
|
xdi_adapter.
|
|
|
|
data_spin_lock,
|
|
|
|
"unload");
|
|
|
|
|
|
|
|
diva_os_cancel_soft_isr(&diva_current->xdi_adapter.
|
|
|
|
req_soft_isr);
|
|
|
|
diva_os_cancel_soft_isr(&diva_current->xdi_adapter.
|
|
|
|
isr_soft_isr);
|
|
|
|
|
|
|
|
diva_os_remove_soft_isr(&diva_current->xdi_adapter.
|
|
|
|
req_soft_isr);
|
|
|
|
diva_current->xdi_adapter.isr_soft_isr.object = NULL;
|
|
|
|
|
|
|
|
if (diva_current->xdi_adapter.e_tbl) {
|
|
|
|
diva_os_free(0,
|
|
|
|
diva_current->xdi_adapter.
|
|
|
|
e_tbl);
|
|
|
|
}
|
|
|
|
diva_current->xdi_adapter.e_tbl = NULL;
|
|
|
|
diva_current->xdi_adapter.e_max = 0;
|
|
|
|
diva_current->xdi_adapter.e_count = 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
diva_4bri_cmd_card_proc(struct _diva_os_xdi_adapter *a,
|
2012-02-20 11:52:38 +08:00
|
|
|
diva_xdi_um_cfg_cmd_t *cmd, int length)
|
2005-04-17 06:20:36 +08:00
|
|
|
{
|
|
|
|
int ret = -1;
|
|
|
|
|
|
|
|
if (cmd->adapter != a->controller) {
|
|
|
|
DBG_ERR(("A: 4bri_cmd, invalid controller=%d != %d",
|
|
|
|
cmd->adapter, a->controller))
|
2012-02-20 11:52:38 +08:00
|
|
|
return (-1);
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
switch (cmd->command) {
|
|
|
|
case DIVA_XDI_UM_CMD_GET_CARD_ORDINAL:
|
|
|
|
a->xdi_mbox.data_length = sizeof(dword);
|
|
|
|
a->xdi_mbox.data =
|
2012-02-20 11:52:38 +08:00
|
|
|
diva_os_malloc(0, a->xdi_mbox.data_length);
|
2005-04-17 06:20:36 +08:00
|
|
|
if (a->xdi_mbox.data) {
|
|
|
|
*(dword *) a->xdi_mbox.data =
|
2012-02-20 11:52:38 +08:00
|
|
|
(dword) a->CardOrdinal;
|
2005-04-17 06:20:36 +08:00
|
|
|
a->xdi_mbox.status = DIVA_XDI_MBOX_BUSY;
|
|
|
|
ret = 0;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
case DIVA_XDI_UM_CMD_GET_SERIAL_NR:
|
|
|
|
a->xdi_mbox.data_length = sizeof(dword);
|
|
|
|
a->xdi_mbox.data =
|
2012-02-20 11:52:38 +08:00
|
|
|
diva_os_malloc(0, a->xdi_mbox.data_length);
|
2005-04-17 06:20:36 +08:00
|
|
|
if (a->xdi_mbox.data) {
|
|
|
|
*(dword *) a->xdi_mbox.data =
|
2012-02-20 11:52:38 +08:00
|
|
|
(dword) a->xdi_adapter.serialNo;
|
2005-04-17 06:20:36 +08:00
|
|
|
a->xdi_mbox.status = DIVA_XDI_MBOX_BUSY;
|
|
|
|
ret = 0;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
case DIVA_XDI_UM_CMD_GET_PCI_HW_CONFIG:
|
|
|
|
if (!a->xdi_adapter.ControllerNumber) {
|
|
|
|
/*
|
2012-02-20 11:52:38 +08:00
|
|
|
Only master adapter can access hardware config
|
|
|
|
*/
|
2005-04-17 06:20:36 +08:00
|
|
|
a->xdi_mbox.data_length = sizeof(dword) * 9;
|
|
|
|
a->xdi_mbox.data =
|
2012-02-20 11:52:38 +08:00
|
|
|
diva_os_malloc(0, a->xdi_mbox.data_length);
|
2005-04-17 06:20:36 +08:00
|
|
|
if (a->xdi_mbox.data) {
|
|
|
|
int i;
|
|
|
|
dword *data = (dword *) a->xdi_mbox.data;
|
|
|
|
|
|
|
|
for (i = 0; i < 8; i++) {
|
|
|
|
*data++ = a->resources.pci.bar[i];
|
|
|
|
}
|
|
|
|
*data++ = (dword) a->resources.pci.irq;
|
|
|
|
a->xdi_mbox.status = DIVA_XDI_MBOX_BUSY;
|
|
|
|
ret = 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
case DIVA_XDI_UM_CMD_GET_CARD_STATE:
|
|
|
|
if (!a->xdi_adapter.ControllerNumber) {
|
|
|
|
a->xdi_mbox.data_length = sizeof(dword);
|
|
|
|
a->xdi_mbox.data =
|
2012-02-20 11:52:38 +08:00
|
|
|
diva_os_malloc(0, a->xdi_mbox.data_length);
|
2005-04-17 06:20:36 +08:00
|
|
|
if (a->xdi_mbox.data) {
|
|
|
|
dword *data = (dword *) a->xdi_mbox.data;
|
|
|
|
if (!a->xdi_adapter.ram
|
|
|
|
|| !a->xdi_adapter.reset
|
|
|
|
|| !a->xdi_adapter.cfg) {
|
|
|
|
*data = 3;
|
|
|
|
} else if (a->xdi_adapter.trapped) {
|
|
|
|
*data = 2;
|
|
|
|
} else if (a->xdi_adapter.Initialized) {
|
|
|
|
*data = 1;
|
|
|
|
} else {
|
|
|
|
*data = 0;
|
|
|
|
}
|
|
|
|
a->xdi_mbox.status = DIVA_XDI_MBOX_BUSY;
|
|
|
|
ret = 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
case DIVA_XDI_UM_CMD_WRITE_FPGA:
|
|
|
|
if (!a->xdi_adapter.ControllerNumber) {
|
|
|
|
ret =
|
2012-02-20 11:52:38 +08:00
|
|
|
diva_4bri_write_fpga_image(a,
|
|
|
|
(byte *)&cmd[1],
|
|
|
|
cmd->command_data.
|
|
|
|
write_fpga.
|
|
|
|
image_length);
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
case DIVA_XDI_UM_CMD_RESET_ADAPTER:
|
|
|
|
if (!a->xdi_adapter.ControllerNumber) {
|
|
|
|
ret = diva_4bri_reset_adapter(&a->xdi_adapter);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
case DIVA_XDI_UM_CMD_WRITE_SDRAM_BLOCK:
|
|
|
|
if (!a->xdi_adapter.ControllerNumber) {
|
|
|
|
ret = diva_4bri_write_sdram_block(&a->xdi_adapter,
|
|
|
|
cmd->
|
|
|
|
command_data.
|
|
|
|
write_sdram.
|
|
|
|
offset,
|
|
|
|
(byte *) &
|
|
|
|
cmd[1],
|
|
|
|
cmd->
|
|
|
|
command_data.
|
|
|
|
write_sdram.
|
|
|
|
length,
|
|
|
|
a->xdi_adapter.
|
|
|
|
MemorySize);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
case DIVA_XDI_UM_CMD_START_ADAPTER:
|
|
|
|
if (!a->xdi_adapter.ControllerNumber) {
|
|
|
|
ret = diva_4bri_start_adapter(&a->xdi_adapter,
|
|
|
|
cmd->command_data.
|
|
|
|
start.offset,
|
|
|
|
cmd->command_data.
|
|
|
|
start.features);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
case DIVA_XDI_UM_CMD_SET_PROTOCOL_FEATURES:
|
|
|
|
if (!a->xdi_adapter.ControllerNumber) {
|
|
|
|
a->xdi_adapter.features =
|
2012-02-20 11:52:38 +08:00
|
|
|
cmd->command_data.features.features;
|
2005-04-17 06:20:36 +08:00
|
|
|
a->xdi_adapter.a.protocol_capabilities =
|
2012-02-20 11:52:38 +08:00
|
|
|
a->xdi_adapter.features;
|
2005-04-17 06:20:36 +08:00
|
|
|
DBG_TRC(("Set raw protocol features (%08x)",
|
|
|
|
a->xdi_adapter.features))
|
2012-02-20 11:52:38 +08:00
|
|
|
ret = 0;
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
case DIVA_XDI_UM_CMD_STOP_ADAPTER:
|
|
|
|
if (!a->xdi_adapter.ControllerNumber) {
|
|
|
|
ret = diva_4bri_stop_adapter(a);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
case DIVA_XDI_UM_CMD_READ_XLOG_ENTRY:
|
|
|
|
ret = diva_card_read_xlog(a);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case DIVA_XDI_UM_CMD_READ_SDRAM:
|
|
|
|
if (!a->xdi_adapter.ControllerNumber
|
|
|
|
&& a->xdi_adapter.Address) {
|
|
|
|
if (
|
2012-02-20 11:52:38 +08:00
|
|
|
(a->xdi_mbox.data_length =
|
|
|
|
cmd->command_data.read_sdram.length)) {
|
2005-04-17 06:20:36 +08:00
|
|
|
if (
|
2012-02-20 11:52:38 +08:00
|
|
|
(a->xdi_mbox.data_length +
|
|
|
|
cmd->command_data.read_sdram.offset) <
|
|
|
|
a->xdi_adapter.MemorySize) {
|
2005-04-17 06:20:36 +08:00
|
|
|
a->xdi_mbox.data =
|
2012-02-20 11:52:38 +08:00
|
|
|
diva_os_malloc(0,
|
|
|
|
a->xdi_mbox.
|
|
|
|
data_length);
|
2005-04-17 06:20:36 +08:00
|
|
|
if (a->xdi_mbox.data) {
|
|
|
|
byte __iomem *p = DIVA_OS_MEM_ATTACH_ADDRESS(&a->xdi_adapter);
|
|
|
|
byte __iomem *src = p;
|
|
|
|
byte *dst = a->xdi_mbox.data;
|
|
|
|
dword len = a->xdi_mbox.data_length;
|
|
|
|
|
|
|
|
src += cmd->command_data.read_sdram.offset;
|
|
|
|
|
|
|
|
while (len--) {
|
|
|
|
*dst++ = READ_BYTE(src++);
|
|
|
|
}
|
|
|
|
DIVA_OS_MEM_DETACH_ADDRESS(&a->xdi_adapter, p);
|
|
|
|
a->xdi_mbox.status = DIVA_XDI_MBOX_BUSY;
|
|
|
|
ret = 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
DBG_ERR(("A: A(%d) invalid cmd=%d", a->controller,
|
|
|
|
cmd->command))
|
2012-02-20 11:52:38 +08:00
|
|
|
}
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
return (ret);
|
|
|
|
}
|
|
|
|
|
2006-01-08 17:05:16 +08:00
|
|
|
void *xdiLoadFile(char *FileName, dword *FileLength,
|
2005-04-17 06:20:36 +08:00
|
|
|
unsigned long lim)
|
|
|
|
{
|
|
|
|
void *ret = diva_xdiLoadFileFile;
|
|
|
|
|
|
|
|
if (FileLength) {
|
|
|
|
*FileLength = diva_xdiLoadFileLength;
|
|
|
|
}
|
|
|
|
diva_xdiLoadFileFile = NULL;
|
|
|
|
diva_xdiLoadFileLength = 0;
|
|
|
|
|
|
|
|
return (ret);
|
|
|
|
}
|
|
|
|
|
|
|
|
void diva_os_set_qBri_functions(PISDN_ADAPTER IoAdapter)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
|
|
|
void diva_os_set_qBri2_functions(PISDN_ADAPTER IoAdapter)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
2012-02-20 11:52:38 +08:00
|
|
|
diva_4bri_write_fpga_image(diva_os_xdi_adapter_t *a, byte *data,
|
2005-04-17 06:20:36 +08:00
|
|
|
dword length)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
diva_xdiLoadFileFile = data;
|
|
|
|
diva_xdiLoadFileLength = length;
|
|
|
|
|
|
|
|
ret = qBri_FPGA_download(&a->xdi_adapter);
|
|
|
|
|
|
|
|
diva_xdiLoadFileFile = NULL;
|
|
|
|
diva_xdiLoadFileLength = 0;
|
|
|
|
|
|
|
|
return (ret ? 0 : -1);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int diva_4bri_reset_adapter(PISDN_ADAPTER IoAdapter)
|
|
|
|
{
|
|
|
|
PISDN_ADAPTER Slave;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
if (!IoAdapter->Address || !IoAdapter->reset) {
|
|
|
|
return (-1);
|
|
|
|
}
|
|
|
|
if (IoAdapter->Initialized) {
|
|
|
|
DBG_ERR(("A: A(%d) can't reset 4BRI adapter - please stop first",
|
|
|
|
IoAdapter->ANum))
|
2012-02-20 11:52:38 +08:00
|
|
|
return (-1);
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
2012-02-20 11:52:38 +08:00
|
|
|
Forget all entities on all adapters
|
|
|
|
*/
|
2005-04-17 06:20:36 +08:00
|
|
|
for (i = 0; ((i < IoAdapter->tasks) && IoAdapter->QuadroList); i++) {
|
|
|
|
Slave = IoAdapter->QuadroList->QuadroAdapter[i];
|
|
|
|
Slave->e_count = 0;
|
|
|
|
if (Slave->e_tbl) {
|
|
|
|
memset(Slave->e_tbl, 0x00,
|
|
|
|
Slave->e_max * sizeof(E_INFO));
|
|
|
|
}
|
|
|
|
Slave->head = 0;
|
|
|
|
Slave->tail = 0;
|
|
|
|
Slave->assign = 0;
|
|
|
|
Slave->trapped = 0;
|
|
|
|
|
|
|
|
memset(&Slave->a.IdTable[0], 0x00,
|
|
|
|
sizeof(Slave->a.IdTable));
|
|
|
|
memset(&Slave->a.IdTypeTable[0], 0x00,
|
|
|
|
sizeof(Slave->a.IdTypeTable));
|
|
|
|
memset(&Slave->a.FlowControlIdTable[0], 0x00,
|
|
|
|
sizeof(Slave->a.FlowControlIdTable));
|
|
|
|
memset(&Slave->a.FlowControlSkipTable[0], 0x00,
|
|
|
|
sizeof(Slave->a.FlowControlSkipTable));
|
|
|
|
memset(&Slave->a.misc_flags_table[0], 0x00,
|
|
|
|
sizeof(Slave->a.misc_flags_table));
|
|
|
|
memset(&Slave->a.rx_stream[0], 0x00,
|
|
|
|
sizeof(Slave->a.rx_stream));
|
|
|
|
memset(&Slave->a.tx_stream[0], 0x00,
|
|
|
|
sizeof(Slave->a.tx_stream));
|
|
|
|
memset(&Slave->a.tx_pos[0], 0x00, sizeof(Slave->a.tx_pos));
|
|
|
|
memset(&Slave->a.rx_pos[0], 0x00, sizeof(Slave->a.rx_pos));
|
|
|
|
}
|
|
|
|
|
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
static int
|
|
|
|
diva_4bri_write_sdram_block(PISDN_ADAPTER IoAdapter,
|
|
|
|
dword address,
|
2012-02-20 11:52:38 +08:00
|
|
|
const byte *data, dword length, dword limit)
|
2005-04-17 06:20:36 +08:00
|
|
|
{
|
|
|
|
byte __iomem *p = DIVA_OS_MEM_ATTACH_ADDRESS(IoAdapter);
|
|
|
|
byte __iomem *mem = p;
|
|
|
|
|
|
|
|
if (((address + length) >= limit) || !mem) {
|
|
|
|
DIVA_OS_MEM_DETACH_ADDRESS(IoAdapter, p);
|
|
|
|
DBG_ERR(("A: A(%d) write 4BRI address=0x%08lx",
|
|
|
|
IoAdapter->ANum, address + length))
|
2012-02-20 11:52:38 +08:00
|
|
|
return (-1);
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
|
|
|
mem += address;
|
|
|
|
|
|
|
|
while (length--) {
|
|
|
|
WRITE_BYTE(mem++, *data++);
|
|
|
|
}
|
|
|
|
|
|
|
|
DIVA_OS_MEM_DETACH_ADDRESS(IoAdapter, p);
|
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
diva_4bri_start_adapter(PISDN_ADAPTER IoAdapter,
|
|
|
|
dword start_address, dword features)
|
|
|
|
{
|
|
|
|
volatile word __iomem *signature;
|
|
|
|
int started = 0;
|
|
|
|
int i;
|
|
|
|
byte __iomem *p;
|
|
|
|
|
|
|
|
/*
|
2012-02-20 11:52:38 +08:00
|
|
|
start adapter
|
|
|
|
*/
|
2005-04-17 06:20:36 +08:00
|
|
|
start_qBri_hardware(IoAdapter);
|
|
|
|
|
|
|
|
p = DIVA_OS_MEM_ATTACH_RAM(IoAdapter);
|
|
|
|
/*
|
2012-02-20 11:52:38 +08:00
|
|
|
wait for signature in shared memory (max. 3 seconds)
|
|
|
|
*/
|
2005-04-17 06:20:36 +08:00
|
|
|
signature = (volatile word __iomem *) (&p[0x1E]);
|
|
|
|
|
|
|
|
for (i = 0; i < 300; ++i) {
|
|
|
|
diva_os_wait(10);
|
|
|
|
if (READ_WORD(&signature[0]) == 0x4447) {
|
|
|
|
DBG_TRC(("Protocol startup time %d.%02d seconds",
|
|
|
|
(i / 100), (i % 100)))
|
2012-02-20 11:52:38 +08:00
|
|
|
started = 1;
|
2005-04-17 06:20:36 +08:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
for (i = 1; i < IoAdapter->tasks; i++) {
|
|
|
|
IoAdapter->QuadroList->QuadroAdapter[i]->features =
|
2012-02-20 11:52:38 +08:00
|
|
|
IoAdapter->features;
|
2005-04-17 06:20:36 +08:00
|
|
|
IoAdapter->QuadroList->QuadroAdapter[i]->a.
|
2012-02-20 11:52:38 +08:00
|
|
|
protocol_capabilities = IoAdapter->features;
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
if (!started) {
|
|
|
|
DBG_FTL(("%s: Adapter selftest failed, signature=%04x",
|
|
|
|
IoAdapter->Properties.Name,
|
|
|
|
READ_WORD(&signature[0])))
|
2012-02-20 11:52:38 +08:00
|
|
|
DIVA_OS_MEM_DETACH_RAM(IoAdapter, p);
|
2005-04-17 06:20:36 +08:00
|
|
|
(*(IoAdapter->trapFnc)) (IoAdapter);
|
|
|
|
IoAdapter->stop(IoAdapter);
|
|
|
|
return (-1);
|
|
|
|
}
|
|
|
|
DIVA_OS_MEM_DETACH_RAM(IoAdapter, p);
|
|
|
|
|
|
|
|
for (i = 0; i < IoAdapter->tasks; i++) {
|
|
|
|
IoAdapter->QuadroList->QuadroAdapter[i]->Initialized = 1;
|
|
|
|
IoAdapter->QuadroList->QuadroAdapter[i]->IrqCount = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (check_qBri_interrupt(IoAdapter)) {
|
|
|
|
DBG_ERR(("A: A(%d) interrupt test failed",
|
|
|
|
IoAdapter->ANum))
|
2012-02-20 11:52:38 +08:00
|
|
|
for (i = 0; i < IoAdapter->tasks; i++) {
|
|
|
|
IoAdapter->QuadroList->QuadroAdapter[i]->Initialized = 0;
|
|
|
|
}
|
2005-04-17 06:20:36 +08:00
|
|
|
IoAdapter->stop(IoAdapter);
|
|
|
|
return (-1);
|
|
|
|
}
|
|
|
|
|
|
|
|
IoAdapter->Properties.Features = (word) features;
|
|
|
|
diva_xdi_display_adapter_features(IoAdapter->ANum);
|
|
|
|
|
|
|
|
for (i = 0; i < IoAdapter->tasks; i++) {
|
2009-01-08 10:09:16 +08:00
|
|
|
DBG_LOG(("A(%d) %s adapter successfully started",
|
2005-04-17 06:20:36 +08:00
|
|
|
IoAdapter->QuadroList->QuadroAdapter[i]->ANum,
|
|
|
|
(IoAdapter->tasks == 1) ? "BRI 2.0" : "4BRI"))
|
2012-02-20 11:52:38 +08:00
|
|
|
diva_xdi_didd_register_adapter(IoAdapter->QuadroList->QuadroAdapter[i]->ANum);
|
2005-04-17 06:20:36 +08:00
|
|
|
IoAdapter->QuadroList->QuadroAdapter[i]->Properties.Features = (word) features;
|
|
|
|
}
|
|
|
|
|
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int check_qBri_interrupt(PISDN_ADAPTER IoAdapter)
|
|
|
|
{
|
|
|
|
#ifdef SUPPORT_INTERRUPT_TEST_ON_4BRI
|
|
|
|
int i;
|
|
|
|
ADAPTER *a = &IoAdapter->a;
|
|
|
|
byte __iomem *p;
|
|
|
|
|
|
|
|
IoAdapter->IrqCount = 0;
|
|
|
|
|
|
|
|
if (IoAdapter->ControllerNumber > 0)
|
|
|
|
return (-1);
|
|
|
|
|
|
|
|
p = DIVA_OS_MEM_ATTACH_RESET(IoAdapter);
|
|
|
|
WRITE_BYTE(&p[PLX9054_INTCSR], PLX9054_INT_ENABLE);
|
|
|
|
DIVA_OS_MEM_DETACH_RESET(IoAdapter, p);
|
|
|
|
/*
|
2012-02-20 11:52:38 +08:00
|
|
|
interrupt test
|
|
|
|
*/
|
2005-04-17 06:20:36 +08:00
|
|
|
a->ReadyInt = 1;
|
|
|
|
a->ram_out(a, &PR_RAM->ReadyInt, 1);
|
|
|
|
|
|
|
|
for (i = 100; !IoAdapter->IrqCount && (i-- > 0); diva_os_wait(10));
|
|
|
|
|
|
|
|
return ((IoAdapter->IrqCount > 0) ? 0 : -1);
|
|
|
|
#else
|
|
|
|
dword volatile __iomem *qBriIrq;
|
|
|
|
byte __iomem *p;
|
|
|
|
/*
|
2012-02-20 11:52:38 +08:00
|
|
|
Reset on-board interrupt register
|
|
|
|
*/
|
2005-04-17 06:20:36 +08:00
|
|
|
IoAdapter->IrqCount = 0;
|
|
|
|
p = DIVA_OS_MEM_ATTACH_CTLREG(IoAdapter);
|
|
|
|
qBriIrq = (dword volatile __iomem *) (&p[_4bri_is_rev_2_card
|
2012-02-20 11:52:38 +08:00
|
|
|
(IoAdapter->
|
|
|
|
cardType) ? (MQ2_BREG_IRQ_TEST)
|
|
|
|
: (MQ_BREG_IRQ_TEST)]);
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
WRITE_DWORD(qBriIrq, MQ_IRQ_REQ_OFF);
|
|
|
|
DIVA_OS_MEM_DETACH_CTLREG(IoAdapter, p);
|
|
|
|
|
|
|
|
p = DIVA_OS_MEM_ATTACH_RESET(IoAdapter);
|
|
|
|
WRITE_BYTE(&p[PLX9054_INTCSR], PLX9054_INT_ENABLE);
|
|
|
|
DIVA_OS_MEM_DETACH_RESET(IoAdapter, p);
|
|
|
|
|
|
|
|
diva_os_wait(100);
|
|
|
|
|
|
|
|
return (0);
|
|
|
|
#endif /* SUPPORT_INTERRUPT_TEST_ON_4BRI */
|
|
|
|
}
|
|
|
|
|
2012-02-20 11:52:38 +08:00
|
|
|
static void diva_4bri_clear_interrupts(diva_os_xdi_adapter_t *a)
|
2005-04-17 06:20:36 +08:00
|
|
|
{
|
|
|
|
PISDN_ADAPTER IoAdapter = &a->xdi_adapter;
|
|
|
|
|
|
|
|
/*
|
2012-02-20 11:52:38 +08:00
|
|
|
clear any pending interrupt
|
|
|
|
*/
|
2005-04-17 06:20:36 +08:00
|
|
|
IoAdapter->disIrq(IoAdapter);
|
|
|
|
|
|
|
|
IoAdapter->tst_irq(&IoAdapter->a);
|
|
|
|
IoAdapter->clr_irq(&IoAdapter->a);
|
|
|
|
IoAdapter->tst_irq(&IoAdapter->a);
|
|
|
|
|
|
|
|
/*
|
2012-02-20 11:52:38 +08:00
|
|
|
kill pending dpcs
|
|
|
|
*/
|
2005-04-17 06:20:36 +08:00
|
|
|
diva_os_cancel_soft_isr(&IoAdapter->req_soft_isr);
|
|
|
|
diva_os_cancel_soft_isr(&IoAdapter->isr_soft_isr);
|
|
|
|
}
|
|
|
|
|
2012-02-20 11:52:38 +08:00
|
|
|
static int diva_4bri_stop_adapter(diva_os_xdi_adapter_t *a)
|
2005-04-17 06:20:36 +08:00
|
|
|
{
|
|
|
|
PISDN_ADAPTER IoAdapter = &a->xdi_adapter;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
if (!IoAdapter->ram) {
|
|
|
|
return (-1);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!IoAdapter->Initialized) {
|
|
|
|
DBG_ERR(("A: A(%d) can't stop PRI adapter - not running",
|
|
|
|
IoAdapter->ANum))
|
2012-02-20 11:52:38 +08:00
|
|
|
return (-1); /* nothing to stop */
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
for (i = 0; i < IoAdapter->tasks; i++) {
|
|
|
|
IoAdapter->QuadroList->QuadroAdapter[i]->Initialized = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
2012-02-20 11:52:38 +08:00
|
|
|
Disconnect Adapters from DIDD
|
|
|
|
*/
|
2005-04-17 06:20:36 +08:00
|
|
|
for (i = 0; i < IoAdapter->tasks; i++) {
|
|
|
|
diva_xdi_didd_remove_adapter(IoAdapter->QuadroList->QuadroAdapter[i]->ANum);
|
|
|
|
}
|
|
|
|
|
|
|
|
i = 100;
|
|
|
|
|
|
|
|
/*
|
2012-02-20 11:52:38 +08:00
|
|
|
Stop interrupts
|
|
|
|
*/
|
2005-04-17 06:20:36 +08:00
|
|
|
a->clear_interrupts_proc = diva_4bri_clear_interrupts;
|
|
|
|
IoAdapter->a.ReadyInt = 1;
|
|
|
|
IoAdapter->a.ram_inc(&IoAdapter->a, &PR_RAM->ReadyInt);
|
|
|
|
do {
|
|
|
|
diva_os_sleep(10);
|
|
|
|
} while (i-- && a->clear_interrupts_proc);
|
|
|
|
|
|
|
|
if (a->clear_interrupts_proc) {
|
|
|
|
diva_4bri_clear_interrupts(a);
|
|
|
|
a->clear_interrupts_proc = NULL;
|
|
|
|
DBG_ERR(("A: A(%d) no final interrupt from 4BRI adapter",
|
|
|
|
IoAdapter->ANum))
|
2012-02-20 11:52:38 +08:00
|
|
|
}
|
2005-04-17 06:20:36 +08:00
|
|
|
IoAdapter->a.ReadyInt = 0;
|
|
|
|
|
|
|
|
/*
|
2012-02-20 11:52:38 +08:00
|
|
|
Stop and reset adapter
|
|
|
|
*/
|
2005-04-17 06:20:36 +08:00
|
|
|
IoAdapter->stop(IoAdapter);
|
|
|
|
|
|
|
|
return (0);
|
|
|
|
}
|