linux_old1/include/linux/micrel_phy.h

#ifndef _MICREL_PHY_H
#define _MICREL_PHY_H

#define MICREL_PHY_ID_MASK	0x00fffff0

#define PHY_ID_KSZ9021		0x00221610
#define PHY_ID_KS8737		0x00221720
#define PHY_ID_KSZ8021		0x00221555
#define PHY_ID_KSZ8041		0x00221510
#define PHY_ID_KSZ8051		0x00221550
/* both for ks8001 Rev. A/B, and for ks8721 Rev 3. */
#define PHY_ID_KSZ8001		0x0022161A

/* struct phy_device dev_flags definitions */
#define MICREL_PHY_50MHZ_CLK	0x00000001

#endif /* _MICREL_PHY_H */
phy/micrel: add ability to support 50MHz RMII clock on KZS8051RNL Platform code can now set the MICREL_PHY_50MHZ_CLK bit of dev_flags in a fixup routine (registered with phy_register_fixup_for_uid()), to make the KZS8051RNL PHY work with 50MHz RMII reference clock. Cc: David J. Choi <david.choi@micrel.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: David S. Miller <davem@davemloft.net> 2011-02-14 10:05:33 +08:00			`#ifndef _MICREL_PHY_H`
			`#define _MICREL_PHY_H`

			`#define MICREL_PHY_ID_MASK 0x00fffff0`

phy/micrel: Fix ID of KSZ9021 Right ID of KSZ9021 is 0x00221610. Because lower 4bit is a revision number, it varies according to a chip. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Cc: David J. Choi <david.choi@micrel.com> Signed-off-by: David S. Miller <davem@davemloft.net> 2012-05-21 22:20:08 +08:00			`#define PHY_ID_KSZ9021 0x00221610`
phy/micrel: add ability to support 50MHz RMII clock on KZS8051RNL Platform code can now set the MICREL_PHY_50MHZ_CLK bit of dev_flags in a fixup routine (registered with phy_register_fixup_for_uid()), to make the KZS8051RNL PHY work with 50MHz RMII reference clock. Cc: David J. Choi <david.choi@micrel.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: David S. Miller <davem@davemloft.net> 2011-02-14 10:05:33 +08:00			`#define PHY_ID_KS8737 0x00221720`
phy/micrel: Implement support for KSZ8021 The KSZ8021 PHY was previously caught by KS8051, which is not correct. This PHY needs additional setup if it is strapped for address 0. In such case an reserved bit must be written in the 0x16, "Operation Mode Strap Override" register. According to the KS8051 datasheet, that bit means "PHY Address 0 in non-broadcast" and it indeed behaves as such on KSZ8021. The issue where the ethernet controller (Freescale FEC) did not communicate with network is fixed by writing this bit as 1. Signed-off-by: Marek Vasut <marex@denx.de> Cc: David J. Choi <david.choi@micrel.com> Cc: David S. Miller <davem@davemloft.net> Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: David S. Miller <davem@davemloft.net> 2012-09-24 00:58:49 +08:00			`#define PHY_ID_KSZ8021 0x00221555`
phy/micrel: Rename KS80xx to KSZ80xx There is no such part as KS8001, KS8041 or KS8051. There are only KSZ8001, KSZ8041 and KSZ8051. Rename these parts as such to match the Micrel naming. Signed-off-by: Marek Vasut <marex@denx.de> Cc: David J. Choi <david.choi@micrel.com> Cc: David S. Miller <davem@davemloft.net> Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Cc: Linux ARM kernel <linux-arm-kernel@lists.infradead.org> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: David S. Miller <davem@davemloft.net> 2012-09-24 00:58:50 +08:00			`#define PHY_ID_KSZ8041 0x00221510`
			`#define PHY_ID_KSZ8051 0x00221550`
phy/micrel: add ability to support 50MHz RMII clock on KZS8051RNL Platform code can now set the MICREL_PHY_50MHZ_CLK bit of dev_flags in a fixup routine (registered with phy_register_fixup_for_uid()), to make the KZS8051RNL PHY work with 50MHz RMII reference clock. Cc: David J. Choi <david.choi@micrel.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: David S. Miller <davem@davemloft.net> 2011-02-14 10:05:33 +08:00			`/* both for ks8001 Rev. A/B, and for ks8721 Rev 3. */`
phy/micrel: Rename KS80xx to KSZ80xx There is no such part as KS8001, KS8041 or KS8051. There are only KSZ8001, KSZ8041 and KSZ8051. Rename these parts as such to match the Micrel naming. Signed-off-by: Marek Vasut <marex@denx.de> Cc: David J. Choi <david.choi@micrel.com> Cc: David S. Miller <davem@davemloft.net> Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Cc: Linux ARM kernel <linux-arm-kernel@lists.infradead.org> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: David S. Miller <davem@davemloft.net> 2012-09-24 00:58:50 +08:00			`#define PHY_ID_KSZ8001 0x0022161A`
phy/micrel: add ability to support 50MHz RMII clock on KZS8051RNL Platform code can now set the MICREL_PHY_50MHZ_CLK bit of dev_flags in a fixup routine (registered with phy_register_fixup_for_uid()), to make the KZS8051RNL PHY work with 50MHz RMII reference clock. Cc: David J. Choi <david.choi@micrel.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: David S. Miller <davem@davemloft.net> 2011-02-14 10:05:33 +08:00
			`/* struct phy_device dev_flags definitions */`
			`#define MICREL_PHY_50MHZ_CLK 0x00000001`

			`#endif /* _MICREL_PHY_H */`