2007-10-22 07:41:41 +08:00
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/*
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* Copyright (c) 2006, Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc., 59 Temple
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* Place - Suite 330, Boston, MA 02111-1307 USA.
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*
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* Copyright (C) Ashok Raj <ashok.raj@intel.com>
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* Copyright (C) Shaohua Li <shaohua.li@intel.com>
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*/
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#ifndef __DMAR_H__
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#define __DMAR_H__
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#include <linux/acpi.h>
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#include <linux/types.h>
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2007-10-22 07:41:49 +08:00
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#include <linux/msi.h>
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2007-10-22 07:41:41 +08:00
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2007-10-22 07:41:49 +08:00
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#ifdef CONFIG_DMAR
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struct intel_iommu;
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2008-02-08 20:18:39 +08:00
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extern const char *dmar_get_fault_reason(u8 fault_reason);
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2007-10-22 07:41:54 +08:00
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/* Can't use the common MSI interrupt functions
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* since DMAR is not a pci device
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*/
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extern void dmar_msi_unmask(unsigned int irq);
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extern void dmar_msi_mask(unsigned int irq);
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extern void dmar_msi_read(int irq, struct msi_msg *msg);
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extern void dmar_msi_write(int irq, struct msi_msg *msg);
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extern int dmar_set_interrupt(struct intel_iommu *iommu);
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extern int arch_setup_dmar_msi(unsigned int irq);
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2007-10-22 07:41:49 +08:00
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/* Intel IOMMU detection and initialization functions */
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extern void detect_intel_iommu(void);
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extern int intel_iommu_init(void);
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2007-10-22 07:41:41 +08:00
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extern int dmar_table_init(void);
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extern int early_dmar_detect(void);
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extern struct list_head dmar_drhd_units;
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extern struct list_head dmar_rmrr_units;
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struct dmar_drhd_unit {
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struct list_head list; /* list of drhd units */
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u64 reg_base_addr; /* register base address*/
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struct pci_dev **devices; /* target device array */
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int devices_cnt; /* target device count */
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u8 ignored:1; /* ignore drhd */
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u8 include_all:1;
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struct intel_iommu *iommu;
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};
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struct dmar_rmrr_unit {
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struct list_head list; /* list of rmrr units */
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u64 base_address; /* reserved base address*/
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u64 end_address; /* reserved end address */
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struct pci_dev **devices; /* target devices */
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int devices_cnt; /* target device count */
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};
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2007-10-22 07:41:49 +08:00
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#define for_each_drhd_unit(drhd) \
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list_for_each_entry(drhd, &dmar_drhd_units, list)
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#define for_each_rmrr_units(rmrr) \
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list_for_each_entry(rmrr, &dmar_rmrr_units, list)
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#else
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static inline void detect_intel_iommu(void)
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{
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return;
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}
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static inline int intel_iommu_init(void)
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{
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return -ENODEV;
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}
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#endif /* !CONFIG_DMAR */
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2007-10-22 07:41:41 +08:00
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#endif /* __DMAR_H__ */
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