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linux_old1/arch/blackfin/mach-bf538/include/mach/portmux.h

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Blackfin: mass clean up of copyright/licensing info Bill Gatliff & David Brownell pointed out we were missing some copyrights, and licensing terms in some of the files in ./arch/blackfin, so this fixes things, and cleans them up. It also removes: - verbose GPL text(refer to the top level ./COPYING file) - file names (you are looking at the file) - bug url (it's in the ./MAINTAINERS file) - "or later" on GPL-2, when we did not have that right It also allows some Blackfin-specific assembly files to be under a BSD like license (for people to use them outside of Linux). Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-09-24 22:11:24 +08:00
/*
* Copyright 2008-2009 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
Blackfin arch: BF538/9 Linux kernel Support Add supporing for Blackfin BF538 and BF539 processors. Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
2008-11-18 17:48:22 +08:00
#ifndef _MACH_PORTMUX_H_
#define _MACH_PORTMUX_H_
Blackfin: bf538: add support for extended GPIO banks The GPIOs on ports C/D/E on the BF538/BF539 do not behave the same way as the other ports on the part and the same way as all other Blackfin parts. The MMRs are programmed slightly different and they cannot be used to generate interrupts or wakeup a sleeping system. Since these guys don't fit into the existing code, create a simple gpiolib driver for them. Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-09-28 20:23:41 +08:00
#define MAX_RESOURCES 64
Blackfin arch: BF538/9 Linux kernel Support Add supporing for Blackfin BF538 and BF539 processors. Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
2008-11-18 17:48:22 +08:00
#define P_TMR2 (P_DONTCARE)
#define P_TMR1 (P_DONTCARE)
#define P_TMR0 (P_DONTCARE)
#define P_TMRCLK (P_DONTCARE)
#define P_PPI0_CLK (P_DONTCARE)
#define P_PPI0_FS1 (P_DONTCARE)
#define P_PPI0_FS2 (P_DONTCARE)
#define P_TWI0_SCL (P_DONTCARE)
#define P_TWI0_SDA (P_DONTCARE)
#define P_TWI1_SCL (P_DONTCARE)
#define P_TWI1_SDA (P_DONTCARE)
#define P_SPORT1_TSCLK (P_DONTCARE)
#define P_SPORT1_RSCLK (P_DONTCARE)
#define P_SPORT0_TSCLK (P_DONTCARE)
#define P_SPORT0_RSCLK (P_DONTCARE)
#define P_SPORT1_DRSEC (P_DONTCARE)
#define P_SPORT1_RFS (P_DONTCARE)
#define P_SPORT1_DTPRI (P_DONTCARE)
#define P_SPORT1_DTSEC (P_DONTCARE)
#define P_SPORT1_TFS (P_DONTCARE)
#define P_SPORT1_DRPRI (P_DONTCARE)
#define P_SPORT0_DRSEC (P_DONTCARE)
#define P_SPORT0_RFS (P_DONTCARE)
#define P_SPORT0_DTPRI (P_DONTCARE)
#define P_SPORT0_DTSEC (P_DONTCARE)
#define P_SPORT0_TFS (P_DONTCARE)
#define P_SPORT0_DRPRI (P_DONTCARE)
#define P_UART0_RX (P_DONTCARE)
#define P_UART0_TX (P_DONTCARE)
#define P_SPI0_MOSI (P_DONTCARE)
#define P_SPI0_MISO (P_DONTCARE)
#define P_SPI0_SCK (P_DONTCARE)
#define P_PPI0_D0 (P_DONTCARE)
#define P_PPI0_D1 (P_DONTCARE)
#define P_PPI0_D2 (P_DONTCARE)
#define P_PPI0_D3 (P_DONTCARE)
#define P_CAN0_TX (P_DEFINED | P_IDENT(GPIO_PC0))
#define P_CAN0_RX (P_DEFINED | P_IDENT(GPIO_PC1))
#define P_SPI1_MOSI (P_DEFINED | P_IDENT(GPIO_PD0))
#define P_SPI1_MISO (P_DEFINED | P_IDENT(GPIO_PD1))
#define P_SPI1_SCK (P_DEFINED | P_IDENT(GPIO_PD2))
#define P_SPI1_SS (P_DEFINED | P_IDENT(GPIO_PD3))
#define P_SPI1_SSEL1 (P_DEFINED | P_IDENT(GPIO_PD4))
#define P_SPI2_MOSI (P_DEFINED | P_IDENT(GPIO_PD5))
#define P_SPI2_MISO (P_DEFINED | P_IDENT(GPIO_PD6))
#define P_SPI2_SCK (P_DEFINED | P_IDENT(GPIO_PD7))
#define P_SPI2_SS (P_DEFINED | P_IDENT(GPIO_PD8))
#define P_SPI2_SSEL1 (P_DEFINED | P_IDENT(GPIO_PD9))
#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PD10))
#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PD11))
#define P_UART2_RX (P_DEFINED | P_IDENT(GPIO_PD12))
#define P_UART2_TX (P_DEFINED | P_IDENT(GPIO_PD13))
#define P_SPORT2_RSCLK (P_DEFINED | P_IDENT(GPIO_PE0))
#define P_SPORT2_RFS (P_DEFINED | P_IDENT(GPIO_PE1))
#define P_SPORT2_DRPRI (P_DEFINED | P_IDENT(GPIO_PE2))
#define P_SPORT2_DRSEC (P_DEFINED | P_IDENT(GPIO_PE3))
#define P_SPORT2_TSCLK (P_DEFINED | P_IDENT(GPIO_PE4))
#define P_SPORT2_TFS (P_DEFINED | P_IDENT(GPIO_PE5))
#define P_SPORT2_DTPRI (P_DEFINED | P_IDENT(GPIO_PE6))
#define P_SPORT2_DTSEC (P_DEFINED | P_IDENT(GPIO_PE7))
#define P_SPORT3_RSCLK (P_DEFINED | P_IDENT(GPIO_PE8))
#define P_SPORT3_RFS (P_DEFINED | P_IDENT(GPIO_PE9))
#define P_SPORT3_DRPRI (P_DEFINED | P_IDENT(GPIO_PE10))
#define P_SPORT3_DRSEC (P_DEFINED | P_IDENT(GPIO_PE11))
#define P_SPORT3_TSCLK (P_DEFINED | P_IDENT(GPIO_PE12))
#define P_SPORT3_TFS (P_DEFINED | P_IDENT(GPIO_PE13))
#define P_SPORT3_DTPRI (P_DEFINED | P_IDENT(GPIO_PE14))
#define P_SPORT3_DTSEC (P_DEFINED | P_IDENT(GPIO_PE15))
#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PF3))
#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF4))
#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF5))
#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF6))
#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF7))
#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF8))
#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF9))
#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF10))
#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF11))
#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF15))
#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF14))
#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF13))
#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF12))
#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PF7))
#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF6))
#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF5))
#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF4))
#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PF3))
#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF2))
#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF1))
#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF0))
Blackfin: add a GPIO_DEFAULT_BOOT_SPI_CS This is parallel to the existing P_DEFAULT_BOOT_SPI_CS, but in terms of the GPIO value so it can be used with the normal gpio API. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-06-09 03:53:45 +08:00
#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PF2
Blackfin arch: Fix bug - Run "reboot" hangs bf518-ezbrd [Mike Frysinger <vapier.adi@gmail.com>: - setup P_DEFAULT_BOOT_SPI_CS for every arch based on the default bootrom behavior and convert all our boards to it - revert previous anomaly change ... bf51x is not affected by anomaly 05000353] Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Mike Frysinger <vapier.adi@gmail.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
2009-02-04 16:49:45 +08:00
#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL2
Blackfin arch: BF538/9 Linux kernel Support Add supporing for Blackfin BF538 and BF539 processors. Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
2008-11-18 17:48:22 +08:00
#endif /* _MACH_PORTMUX_H_ */