2011-05-10 00:56:46 +08:00
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/*
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* Broadcom specific AMBA
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* Core ops
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*
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* Licensed under the GNU/GPL. See COPYING for details.
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*/
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#include "bcma_private.h"
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#include <linux/bcma/bcma.h>
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bool bcma_core_is_enabled(struct bcma_device *core)
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{
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if ((bcma_aread32(core, BCMA_IOCTL) & (BCMA_IOCTL_CLK | BCMA_IOCTL_FGC))
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!= BCMA_IOCTL_CLK)
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return false;
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if (bcma_aread32(core, BCMA_RESET_CTL) & BCMA_RESET_CTL_RESET)
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return false;
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return true;
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}
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EXPORT_SYMBOL_GPL(bcma_core_is_enabled);
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2011-06-10 02:07:20 +08:00
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void bcma_core_disable(struct bcma_device *core, u32 flags)
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2011-05-10 00:56:46 +08:00
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{
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if (bcma_aread32(core, BCMA_RESET_CTL) & BCMA_RESET_CTL_RESET)
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return;
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bcma_awrite32(core, BCMA_IOCTL, flags);
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bcma_aread32(core, BCMA_IOCTL);
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udelay(10);
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bcma_awrite32(core, BCMA_RESET_CTL, BCMA_RESET_CTL_RESET);
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udelay(1);
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}
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2011-06-10 02:07:20 +08:00
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EXPORT_SYMBOL_GPL(bcma_core_disable);
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2011-05-10 00:56:46 +08:00
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int bcma_core_enable(struct bcma_device *core, u32 flags)
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{
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bcma_core_disable(core, flags);
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bcma_awrite32(core, BCMA_IOCTL, (BCMA_IOCTL_CLK | BCMA_IOCTL_FGC | flags));
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bcma_aread32(core, BCMA_IOCTL);
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bcma_awrite32(core, BCMA_RESET_CTL, 0);
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udelay(1);
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bcma_awrite32(core, BCMA_IOCTL, (BCMA_IOCTL_CLK | flags));
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bcma_aread32(core, BCMA_IOCTL);
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udelay(1);
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return 0;
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}
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EXPORT_SYMBOL_GPL(bcma_core_enable);
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2011-07-17 07:06:04 +08:00
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void bcma_core_set_clockmode(struct bcma_device *core,
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enum bcma_clkmode clkmode)
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{
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u16 i;
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WARN_ON(core->id.id != BCMA_CORE_CHIPCOMMON &&
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core->id.id != BCMA_CORE_PCIE &&
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core->id.id != BCMA_CORE_80211);
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switch (clkmode) {
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case BCMA_CLKMODE_FAST:
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bcma_set32(core, BCMA_CLKCTLST, BCMA_CLKCTLST_FORCEHT);
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udelay(64);
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for (i = 0; i < 1500; i++) {
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if (bcma_read32(core, BCMA_CLKCTLST) &
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BCMA_CLKCTLST_HAVEHT) {
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i = 0;
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break;
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}
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udelay(10);
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}
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if (i)
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pr_err("HT force timeout\n");
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break;
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case BCMA_CLKMODE_DYNAMIC:
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pr_warn("Dynamic clockmode not supported yet!\n");
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break;
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}
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}
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EXPORT_SYMBOL_GPL(bcma_core_set_clockmode);
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