2018-01-27 01:45:16 +08:00
|
|
|
# SPDX-License-Identifier: GPL-2.0
|
|
|
|
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
menu "PCI host controller drivers"
|
|
|
|
depends on PCI
|
|
|
|
|
|
|
|
config PCI_MVEBU
|
|
|
|
bool "Marvell EBU PCIe controller"
|
2014-07-11 05:36:29 +08:00
|
|
|
depends on ARCH_MVEBU || ARCH_DOVE
|
2016-02-18 21:32:10 +08:00
|
|
|
depends on ARM
|
2013-08-09 18:35:50 +08:00
|
|
|
depends on OF
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
|
2016-06-30 17:32:31 +08:00
|
|
|
config PCI_AARDVARK
|
|
|
|
bool "Aardvark PCIe controller"
|
|
|
|
depends on ARCH_MVEBU && ARM64
|
|
|
|
depends on OF
|
|
|
|
depends on PCI_MSI_IRQ_DOMAIN
|
|
|
|
help
|
|
|
|
Add support for Aardvark 64bit PCIe Host Controller. This
|
|
|
|
controller is part of the South Bridge of the Marvel Armada
|
|
|
|
3700 SoC.
|
2016-03-15 21:55:52 +08:00
|
|
|
|
2016-03-07 00:32:14 +08:00
|
|
|
config PCIE_XILINX_NWL
|
|
|
|
bool "NWL PCIe Core"
|
|
|
|
depends on ARCH_ZYNQMP
|
2016-06-16 04:47:33 +08:00
|
|
|
depends on PCI_MSI_IRQ_DOMAIN
|
2016-03-07 00:32:14 +08:00
|
|
|
help
|
|
|
|
Say 'Y' here if you want kernel support for Xilinx
|
|
|
|
NWL PCIe controller. The controller can act as Root Port
|
|
|
|
or End Point. The current option selection will only
|
|
|
|
support root port enabling.
|
|
|
|
|
PCI: faraday: Add Faraday Technology FTPCI100 PCI Host Bridge driver
Add a host bridge driver for the Faraday Technology FPPCI100 host bridge,
used for Cortina Systems Gemini SoC (SL3516) PCI Host Bridge.
This code is inspired by the out-of-tree OpenWRT patch and then extensively
rewritten for device tree and using the modern helpers to cut down and
modernize the code to all new PCI frameworks. A driver exists in U-Boot as
well.
Tested on the ITian Square One SQ201 NAS with the following result in the
boot log (trimmed to relevant parts):
OF: PCI: host bridge /soc/pci@50000000 ranges:
OF: PCI: IO 0x50000000..0x500fffff -> 0x00000000
OF: PCI: MEM 0x58000000..0x5fffffff -> 0x58000000
ftpci100 50000000.pci: PCI host bridge to bus 0000:00
pci_bus 0000:00: root bus resource [bus 00-ff]
pci_bus 0000:00: root bus resource [io 0x0000-0xfffff]
pci_bus 0000:00: root bus resource [mem 0x58000000-0x5fffffff]
ftpci100 50000000.pci:
DMA MEM1 BASE: 0x0000000000000000 -> 0x0000000007ffffff config 00070000
ftpci100 50000000.pci:
DMA MEM2 BASE: 0x0000000000000000 -> 0x0000000003ffffff config 00060000
ftpci100 50000000.pci:
DMA MEM3 BASE: 0x0000000000000000 -> 0x0000000003ffffff config 00060000
PCI: bus0: Fast back to back transfers disabled
pci 0000:00:00.0: of_irq_parse_pci() failed with rc=-22
pci 0000:00:0c.0: BAR 0: assigned [mem 0x58000000-0x58007fff]
pci 0000:00:09.2: BAR 0: assigned [mem 0x58008000-0x580080ff]
pci 0000:00:09.0: BAR 4: assigned [io 0x1000-0x101f]
pci 0000:00:09.1: BAR 4: assigned [io 0x1020-0x103f]
pci 0000:00:09.0: enabling device (0140 -> 0141)
pci 0000:00:09.0: HCRESET not completed yet!
pci 0000:00:09.1: enabling device (0140 -> 0141)
pci 0000:00:09.1: HCRESET not completed yet!
pci 0000:00:09.2: enabling device (0140 -> 0142)
rt61pci 0000:00:0c.0: enabling device (0140 -> 0142)
ieee80211 phy0: rt2x00_set_chip: Info - Chipset detected -
rt: 2561, rf: 0003, rev: 000c
ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
ehci-pci: EHCI PCI platform driver
ehci-pci 0000:00:09.2: EHCI Host Controller
ehci-pci 0000:00:09.2: new USB bus registered, assigned bus number 1
ehci-pci 0000:00:09.2: irq 125, io mem 0x58008000
ehci-pci 0000:00:09.2: USB 2.0 started, EHCI 1.00
hub 1-0:1.0: USB hub found
hub 1-0:1.0: 4 ports detected
uhci_hcd: USB Universal Host Controller Interface driver
uhci_hcd 0000:00:09.0: UHCI Host Controller
uhci_hcd 0000:00:09.0: new USB bus registered, assigned bus number 2
uhci_hcd 0000:00:09.0: HCRESET not completed yet!
uhci_hcd 0000:00:09.0: irq 123, io base 0x00001000
hub 2-0:1.0: USB hub found
hub 2-0:1.0: config failed, hub doesn't have any ports! (err -19)
uhci_hcd 0000:00:09.1: UHCI Host Controller
uhci_hcd 0000:00:09.1: new USB bus registered, assigned bus number 3
uhci_hcd 0000:00:09.1: HCRESET not completed yet!
uhci_hcd 0000:00:09.1: irq 124, io base 0x00001020
hub 3-0:1.0: USB hub found
hub 3-0:1.0: config failed, hub doesn't have any ports! (err -19)
scsi 0:0:0:0: Direct-Access USB Flash Disk 1.00 PQ: 0 ANSI: 2
sd 0:0:0:0: [sda] 7900336 512-byte logical blocks: (4.04 GB/3.77 GiB)
sd 0:0:0:0: [sda] Write Protect is off
sd 0:0:0:0: [sda] No Caching mode page found
sd 0:0:0:0: [sda] Assuming drive cache: write through
sda: sda1 sda2 sda3
sd 0:0:0:0: [sda] Attached SCSI removable disk
ieee80211 phy0: rt2x00lib_request_firmware: Info -
Loading firmware file 'rt2561s.bin'
ieee80211 phy0: rt2x00lib_request_firmware: Info -
Firmware detected - version: 0.8
IPv6: ADDRCONF(NETDEV_UP): wlan0: link is not ready
$ lspci
00:00.0 Class 0600: 159b:4321
00:09.2 Class 0c03: 1106:3104
00:09.0 Class 0c03: 1106:3038
00:09.1 Class 0c03: 1106:3038
00:0c.0 Class 0280: 1814:0301
$ cat /proc/interrupts
CPU0
123: 0 PCI 0 Edge uhci_hcd:usb2
124: 0 PCI 1 Edge uhci_hcd:usb3
125: 159 PCI 2 Edge ehci_hcd:usb1
126: 1082 PCI 3 Edge rt61pci
$ cat /proc/iomem
50000000-500000ff : /soc/pci@50000000
58000000-5fffffff : Gemini PCI MEM
58000000-58007fff : 0000:00:0c.0
58000000-58007fff : 0000:00:0c.0
58008000-580080ff : 0000:00:09.2
58008000-580080ff : ehci_hcd
The EHCI USB hub works fine; I can mount and manage files and the IRQs just
keep ticking up. I can issue iwlist wlan0 scanning and see all the WLANs
here. I don't have wpa_supplicant so have not tried connecting to them.
[bhelgaas: fold in %pap change from Arnd Bergmann <arnd@arndb.de>]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
CC: Janos Laube <janos.dev@gmail.com>
CC: Paulius Zaleckas <paulius.zaleckas@gmail.com>
CC: Hans Ulli Kroll <ulli.kroll@googlemail.com>
CC: Florian Fainelli <f.fainelli@gmail.com>
CC: Feng-Hsin Chiang <john453@faraday-tech.com>
CC: Greentime Hu <green.hu@gmail.com>
2017-03-13 06:24:03 +08:00
|
|
|
config PCI_FTPCI100
|
|
|
|
bool "Faraday Technology FTPCI100 PCI controller"
|
|
|
|
depends on OF
|
|
|
|
depends on ARM
|
|
|
|
default ARCH_GEMINI
|
|
|
|
|
2013-08-09 22:49:19 +08:00
|
|
|
config PCI_TEGRA
|
|
|
|
bool "NVIDIA Tegra PCIe controller"
|
2016-11-25 18:57:16 +08:00
|
|
|
depends on ARCH_TEGRA
|
2018-03-14 02:23:06 +08:00
|
|
|
depends on PCI_MSI_IRQ_DOMAIN
|
2014-11-12 21:53:38 +08:00
|
|
|
help
|
|
|
|
Say Y here if you want support for the PCIe host controller found
|
|
|
|
on NVIDIA Tegra SoCs.
|
2013-08-09 22:49:19 +08:00
|
|
|
|
2013-10-30 00:12:51 +08:00
|
|
|
config PCI_RCAR_GEN2
|
|
|
|
bool "Renesas R-Car Gen2 Internal PCI controller"
|
2015-10-30 21:08:17 +08:00
|
|
|
depends on ARM
|
2016-02-25 08:45:56 +08:00
|
|
|
depends on ARCH_RENESAS || COMPILE_TEST
|
2013-10-30 00:12:51 +08:00
|
|
|
help
|
|
|
|
Say Y here if you want internal PCI support on R-Car Gen2 SoC.
|
|
|
|
There are 3 internal PCI controllers available with a single
|
|
|
|
built-in EHCI/OHCI host controller present on each one.
|
|
|
|
|
2016-04-21 11:51:55 +08:00
|
|
|
config PCIE_RCAR
|
2014-05-12 18:57:48 +08:00
|
|
|
bool "Renesas R-Car PCIe controller"
|
2016-02-25 08:45:56 +08:00
|
|
|
depends on ARCH_RENESAS || (ARM && COMPILE_TEST)
|
2016-06-16 04:47:33 +08:00
|
|
|
depends on PCI_MSI_IRQ_DOMAIN
|
2014-05-12 18:57:48 +08:00
|
|
|
help
|
2016-04-21 11:51:55 +08:00
|
|
|
Say Y here if you want PCIe controller support on R-Car SoCs.
|
2014-05-12 18:57:48 +08:00
|
|
|
|
2016-03-12 05:35:55 +08:00
|
|
|
config PCI_HOST_COMMON
|
|
|
|
bool
|
2016-05-12 06:34:46 +08:00
|
|
|
select PCI_ECAM
|
2016-03-12 05:35:55 +08:00
|
|
|
|
2013-11-23 00:14:41 +08:00
|
|
|
config PCI_HOST_GENERIC
|
|
|
|
bool "Generic PCI host controller"
|
2015-08-05 04:53:40 +08:00
|
|
|
depends on (ARM || ARM64) && OF
|
2016-03-12 05:35:55 +08:00
|
|
|
select PCI_HOST_COMMON
|
2016-05-18 22:15:53 +08:00
|
|
|
select IRQ_DOMAIN
|
2013-11-23 00:14:41 +08:00
|
|
|
help
|
|
|
|
Say Y here if you want to support a simple generic PCI host
|
|
|
|
controller, such as the one emulated by kvmtool.
|
|
|
|
|
2014-08-21 00:26:02 +08:00
|
|
|
config PCIE_XILINX
|
|
|
|
bool "Xilinx AXI PCIe host bridge support"
|
2017-08-16 05:25:29 +08:00
|
|
|
depends on ARCH_ZYNQ || MICROBLAZE || (MIPS && PCI_DRIVERS_GENERIC)
|
2014-08-21 00:26:02 +08:00
|
|
|
help
|
|
|
|
Say 'Y' here if you want kernel to support the Xilinx AXI PCIe
|
|
|
|
Host Bridge driver.
|
|
|
|
|
2014-10-02 03:01:35 +08:00
|
|
|
config PCI_XGENE
|
|
|
|
bool "X-Gene PCIe controller"
|
2016-12-02 10:27:07 +08:00
|
|
|
depends on ARM64
|
|
|
|
depends on OF || (ACPI && PCI_QUIRKS)
|
2014-10-02 03:01:35 +08:00
|
|
|
select PCIEPORTBUS
|
|
|
|
help
|
|
|
|
Say Y here if you want internal PCI support on APM X-Gene SoC.
|
|
|
|
There are 5 internal PCIe ports available. Each port is GEN3 capable
|
|
|
|
and have varied lanes from x1 to x8.
|
|
|
|
|
2015-06-06 04:56:34 +08:00
|
|
|
config PCI_XGENE_MSI
|
|
|
|
bool "X-Gene v1 PCIe MSI feature"
|
2016-06-16 04:47:33 +08:00
|
|
|
depends on PCI_XGENE
|
|
|
|
depends on PCI_MSI_IRQ_DOMAIN
|
2015-06-06 04:56:34 +08:00
|
|
|
default y
|
|
|
|
help
|
|
|
|
Say Y here if you want PCIe MSI support for the APM X-Gene v1 SoC.
|
|
|
|
This MSI driver supports 5 PCIe ports on the APM X-Gene v1 SoC.
|
|
|
|
|
2017-09-27 02:02:20 +08:00
|
|
|
config PCI_V3_SEMI
|
|
|
|
bool "V3 Semiconductor PCI controller"
|
|
|
|
depends on OF
|
|
|
|
depends on ARM
|
|
|
|
default ARCH_INTEGRATOR_AP
|
|
|
|
|
2015-01-29 00:16:18 +08:00
|
|
|
config PCI_VERSATILE
|
|
|
|
bool "ARM Versatile PB PCI controller"
|
|
|
|
depends on ARCH_VERSATILE
|
|
|
|
|
2015-04-09 02:21:35 +08:00
|
|
|
config PCIE_IPROC
|
2015-11-25 05:28:48 +08:00
|
|
|
tristate
|
2017-03-01 23:53:13 +08:00
|
|
|
select PCI_DOMAINS
|
2015-04-09 02:21:35 +08:00
|
|
|
help
|
|
|
|
This enables the iProc PCIe core controller support for Broadcom's
|
2015-11-25 05:28:48 +08:00
|
|
|
iProc family of SoCs. An appropriate bus interface driver needs
|
|
|
|
to be enabled to select this.
|
2015-04-09 02:21:35 +08:00
|
|
|
|
|
|
|
config PCIE_IPROC_PLATFORM
|
|
|
|
tristate "Broadcom iProc PCIe platform bus driver"
|
|
|
|
depends on ARCH_BCM_IPROC || (ARM && COMPILE_TEST)
|
|
|
|
depends on OF
|
|
|
|
select PCIE_IPROC
|
|
|
|
default ARCH_BCM_IPROC
|
|
|
|
help
|
|
|
|
Say Y here if you want to use the Broadcom iProc PCIe controller
|
|
|
|
through the generic platform bus interface
|
|
|
|
|
2015-05-13 05:23:01 +08:00
|
|
|
config PCIE_IPROC_BCMA
|
2015-07-26 03:15:24 +08:00
|
|
|
tristate "Broadcom iProc PCIe BCMA bus driver"
|
2015-07-30 01:12:53 +08:00
|
|
|
depends on ARM && (ARCH_BCM_IPROC || COMPILE_TEST)
|
2015-05-13 05:23:01 +08:00
|
|
|
select PCIE_IPROC
|
|
|
|
select BCMA
|
|
|
|
default ARCH_BCM_5301X
|
|
|
|
help
|
|
|
|
Say Y here if you want to use the Broadcom iProc PCIe controller
|
|
|
|
through the BCMA bus interface
|
|
|
|
|
2016-01-07 08:04:35 +08:00
|
|
|
config PCIE_IPROC_MSI
|
|
|
|
bool "Broadcom iProc PCIe MSI support"
|
|
|
|
depends on PCIE_IPROC_PLATFORM || PCIE_IPROC_BCMA
|
2016-06-16 04:47:33 +08:00
|
|
|
depends on PCI_MSI_IRQ_DOMAIN
|
2016-01-07 08:04:35 +08:00
|
|
|
default ARCH_BCM_IPROC
|
|
|
|
help
|
|
|
|
Say Y here if you want to enable MSI support for Broadcom's iProc
|
|
|
|
PCIe controller
|
|
|
|
|
2015-10-23 18:27:12 +08:00
|
|
|
config PCIE_ALTERA
|
|
|
|
bool "Altera PCIe controller"
|
|
|
|
depends on ARM || NIOS2
|
|
|
|
depends on OF_PCI
|
|
|
|
select PCI_DOMAINS
|
|
|
|
help
|
|
|
|
Say Y here if you want to enable PCIe controller support on Altera
|
|
|
|
FPGA.
|
|
|
|
|
2015-10-23 18:27:13 +08:00
|
|
|
config PCIE_ALTERA_MSI
|
|
|
|
bool "Altera PCIe MSI feature"
|
2016-06-16 04:47:33 +08:00
|
|
|
depends on PCIE_ALTERA
|
|
|
|
depends on PCI_MSI_IRQ_DOMAIN
|
2015-10-23 18:27:13 +08:00
|
|
|
help
|
|
|
|
Say Y here if you want PCIe MSI support for the Altera FPGA.
|
|
|
|
This MSI driver supports Altera MSI to GIC controller IP.
|
|
|
|
|
2016-03-05 06:31:47 +08:00
|
|
|
config PCI_HOST_THUNDER_PEM
|
|
|
|
bool "Cavium Thunder PCIe controller to off-chip devices"
|
2016-12-01 14:07:56 +08:00
|
|
|
depends on ARM64
|
|
|
|
depends on OF || (ACPI && PCI_QUIRKS)
|
2016-03-05 06:31:47 +08:00
|
|
|
select PCI_HOST_COMMON
|
|
|
|
help
|
|
|
|
Say Y here if you want PCIe support for CN88XX Cavium Thunder SoCs.
|
|
|
|
|
2016-03-05 06:31:48 +08:00
|
|
|
config PCI_HOST_THUNDER_ECAM
|
|
|
|
bool "Cavium Thunder ECAM controller to on-chip devices on pass-1.x silicon"
|
2016-12-01 13:16:34 +08:00
|
|
|
depends on ARM64
|
|
|
|
depends on OF || (ACPI && PCI_QUIRKS)
|
2016-03-05 06:31:48 +08:00
|
|
|
select PCI_HOST_COMMON
|
|
|
|
help
|
|
|
|
Say Y here if you want ECAM support for CN88XX-Pass-1.x Cavium Thunder SoCs.
|
|
|
|
|
2016-09-04 00:41:09 +08:00
|
|
|
config PCIE_ROCKCHIP
|
2017-03-10 10:46:17 +08:00
|
|
|
tristate "Rockchip PCIe controller"
|
2016-12-08 05:05:59 +08:00
|
|
|
depends on ARCH_ROCKCHIP || COMPILE_TEST
|
2016-09-04 00:41:09 +08:00
|
|
|
depends on OF
|
|
|
|
depends on PCI_MSI_IRQ_DOMAIN
|
|
|
|
select MFD_SYSCON
|
|
|
|
help
|
|
|
|
Say Y here if you want internal PCI support on Rockchip SoC.
|
|
|
|
There is 1 internal PCIe port available to support GEN2 with
|
|
|
|
4 slots.
|
|
|
|
|
2017-05-21 11:42:24 +08:00
|
|
|
config PCIE_MEDIATEK
|
|
|
|
bool "MediaTek PCIe controller"
|
2017-08-10 14:34:59 +08:00
|
|
|
depends on (ARM || ARM64) && (ARCH_MEDIATEK || COMPILE_TEST)
|
2017-05-21 11:42:24 +08:00
|
|
|
depends on OF
|
|
|
|
depends on PCI
|
|
|
|
select PCIEPORTBUS
|
|
|
|
help
|
|
|
|
Say Y here if you want to enable PCIe controller support on
|
2017-08-10 14:34:59 +08:00
|
|
|
MediaTek SoCs.
|
2017-05-21 11:42:24 +08:00
|
|
|
|
2017-06-20 16:17:40 +08:00
|
|
|
config PCIE_TANGO_SMP8759
|
|
|
|
bool "Tango SMP8759 PCIe controller (DANGEROUS)"
|
|
|
|
depends on ARCH_TANGO && PCI_MSI && OF
|
|
|
|
depends on BROKEN
|
|
|
|
select PCI_HOST_COMMON
|
|
|
|
help
|
|
|
|
Say Y here to enable PCIe controller support for Sigma Designs
|
|
|
|
Tango SMP8759-based systems.
|
|
|
|
|
|
|
|
Note: The SMP8759 controller multiplexes PCI config and MMIO
|
|
|
|
accesses, and Linux doesn't provide a way to serialize them.
|
|
|
|
This can lead to data corruption if drivers perform concurrent
|
|
|
|
config and MMIO accesses.
|
|
|
|
|
2016-10-05 01:26:37 +08:00
|
|
|
config VMD
|
2016-11-12 07:08:45 +08:00
|
|
|
depends on PCI_MSI && X86_64 && SRCU
|
2016-10-05 01:26:37 +08:00
|
|
|
tristate "Intel Volume Management Device Driver"
|
|
|
|
---help---
|
|
|
|
Adds support for the Intel Volume Management Device (VMD). VMD is a
|
|
|
|
secondary PCI host bridge that allows PCI Express root ports,
|
|
|
|
and devices attached to them, to be removed from the default
|
|
|
|
PCI domain and placed within the VMD domain. This provides
|
|
|
|
more bus resources than are otherwise possible with a
|
|
|
|
single domain. If you know your system provides one of these and
|
|
|
|
has devices attached to it, say Y; if you are not sure, say N.
|
|
|
|
|
|
|
|
To compile this driver as a module, choose M here: the
|
|
|
|
module will be called vmd.
|
|
|
|
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 23:55:22 +08:00
|
|
|
endmenu
|