2006-09-27 22:27:33 +08:00
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/*
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* linux/arch/arm/mm/mmu.c
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*
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* Copyright (C) 1995-2005 Russell King
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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2006-09-27 22:38:34 +08:00
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#include <linux/module.h>
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2006-09-27 22:27:33 +08:00
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/init.h>
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#include <linux/mman.h>
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#include <linux/nodemask.h>
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2010-07-09 23:27:52 +08:00
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#include <linux/memblock.h>
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2010-09-13 23:01:24 +08:00
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#include <linux/fs.h>
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2006-09-27 22:27:33 +08:00
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2008-08-11 01:08:10 +08:00
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#include <asm/cputype.h>
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2008-12-01 19:53:07 +08:00
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#include <asm/sections.h>
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2008-11-04 13:48:42 +08:00
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#include <asm/cachetype.h>
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2006-09-27 22:27:33 +08:00
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#include <asm/setup.h>
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#include <asm/sizes.h>
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2009-09-28 03:55:43 +08:00
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#include <asm/smp_plat.h>
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2006-09-27 22:27:33 +08:00
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#include <asm/tlb.h>
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2008-09-16 04:44:55 +08:00
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#include <asm/highmem.h>
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2010-09-13 23:03:21 +08:00
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#include <asm/traps.h>
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2006-09-27 22:27:33 +08:00
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include "mm.h"
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/*
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* empty_zero_page is a special page that is used for
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* zero-initialized data and COW.
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*/
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struct page *empty_zero_page;
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2008-04-29 20:11:12 +08:00
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EXPORT_SYMBOL(empty_zero_page);
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2006-09-27 22:27:33 +08:00
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/*
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* The pmd table for the upper-most set of pages.
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*/
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pmd_t *top_pmd;
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2006-09-27 22:38:34 +08:00
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#define CPOLICY_UNCACHED 0
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#define CPOLICY_BUFFERED 1
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#define CPOLICY_WRITETHROUGH 2
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#define CPOLICY_WRITEBACK 3
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#define CPOLICY_WRITEALLOC 4
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static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK;
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static unsigned int ecc_mask __initdata = 0;
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2007-02-11 20:45:13 +08:00
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pgprot_t pgprot_user;
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2006-09-27 22:38:34 +08:00
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pgprot_t pgprot_kernel;
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2007-02-11 20:45:13 +08:00
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EXPORT_SYMBOL(pgprot_user);
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2006-09-27 22:38:34 +08:00
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EXPORT_SYMBOL(pgprot_kernel);
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struct cachepolicy {
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const char policy[16];
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unsigned int cr_mask;
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unsigned int pmd;
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2010-11-16 08:22:09 +08:00
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pteval_t pte;
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2006-09-27 22:38:34 +08:00
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};
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static struct cachepolicy cache_policies[] __initdata = {
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{
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.policy = "uncached",
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.cr_mask = CR_W|CR_C,
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.pmd = PMD_SECT_UNCACHED,
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2008-09-07 03:04:59 +08:00
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.pte = L_PTE_MT_UNCACHED,
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2006-09-27 22:38:34 +08:00
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}, {
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.policy = "buffered",
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.cr_mask = CR_C,
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.pmd = PMD_SECT_BUFFERED,
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2008-09-07 03:04:59 +08:00
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.pte = L_PTE_MT_BUFFERABLE,
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2006-09-27 22:38:34 +08:00
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}, {
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.policy = "writethrough",
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.cr_mask = 0,
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.pmd = PMD_SECT_WT,
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2008-09-07 03:04:59 +08:00
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.pte = L_PTE_MT_WRITETHROUGH,
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2006-09-27 22:38:34 +08:00
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}, {
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.policy = "writeback",
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.cr_mask = 0,
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.pmd = PMD_SECT_WB,
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2008-09-07 03:04:59 +08:00
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.pte = L_PTE_MT_WRITEBACK,
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2006-09-27 22:38:34 +08:00
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}, {
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.policy = "writealloc",
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.cr_mask = 0,
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.pmd = PMD_SECT_WBWA,
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2008-09-07 03:04:59 +08:00
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.pte = L_PTE_MT_WRITEALLOC,
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2006-09-27 22:38:34 +08:00
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}
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};
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/*
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2007-05-12 03:40:30 +08:00
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* These are useful for identifying cache coherency
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2006-09-27 22:38:34 +08:00
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* problems by allowing the cache or the cache and
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* writebuffer to be turned off. (Note: the write
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* buffer should not be on and the cache off).
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*/
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2010-01-12 06:17:34 +08:00
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static int __init early_cachepolicy(char *p)
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2006-09-27 22:38:34 +08:00
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(cache_policies); i++) {
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int len = strlen(cache_policies[i].policy);
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2010-01-12 06:17:34 +08:00
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if (memcmp(p, cache_policies[i].policy, len) == 0) {
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2006-09-27 22:38:34 +08:00
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cachepolicy = i;
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cr_alignment &= ~cache_policies[i].cr_mask;
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cr_no_alignment &= ~cache_policies[i].cr_mask;
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break;
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}
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}
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if (i == ARRAY_SIZE(cache_policies))
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printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n");
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2009-11-02 01:44:24 +08:00
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/*
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* This restriction is partly to do with the way we boot; it is
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* unpredictable to have memory mapped using two different sets of
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* memory attributes (shared, type, and cache attribs). We can not
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* change these attributes once the initial assembly has setup the
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* page tables.
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*/
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2007-07-20 18:42:24 +08:00
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if (cpu_architecture() >= CPU_ARCH_ARMv6) {
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printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6 and later\n");
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cachepolicy = CPOLICY_WRITEBACK;
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}
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2006-09-27 22:38:34 +08:00
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flush_cache_all();
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set_cr(cr_alignment);
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2010-01-12 06:17:34 +08:00
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return 0;
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2006-09-27 22:38:34 +08:00
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}
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2010-01-12 06:17:34 +08:00
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early_param("cachepolicy", early_cachepolicy);
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2006-09-27 22:38:34 +08:00
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2010-01-12 06:17:34 +08:00
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static int __init early_nocache(char *__unused)
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2006-09-27 22:38:34 +08:00
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{
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char *p = "buffered";
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printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p);
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2010-01-12 06:17:34 +08:00
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early_cachepolicy(p);
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return 0;
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2006-09-27 22:38:34 +08:00
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}
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2010-01-12 06:17:34 +08:00
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early_param("nocache", early_nocache);
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2006-09-27 22:38:34 +08:00
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2010-01-12 06:17:34 +08:00
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static int __init early_nowrite(char *__unused)
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2006-09-27 22:38:34 +08:00
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{
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char *p = "uncached";
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printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p);
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2010-01-12 06:17:34 +08:00
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early_cachepolicy(p);
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return 0;
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2006-09-27 22:38:34 +08:00
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}
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2010-01-12 06:17:34 +08:00
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early_param("nowb", early_nowrite);
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2006-09-27 22:38:34 +08:00
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2010-01-12 06:17:34 +08:00
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static int __init early_ecc(char *p)
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2006-09-27 22:38:34 +08:00
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{
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2010-01-12 06:17:34 +08:00
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if (memcmp(p, "on", 2) == 0)
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2006-09-27 22:38:34 +08:00
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ecc_mask = PMD_PROTECTION;
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2010-01-12 06:17:34 +08:00
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else if (memcmp(p, "off", 3) == 0)
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2006-09-27 22:38:34 +08:00
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ecc_mask = 0;
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2010-01-12 06:17:34 +08:00
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return 0;
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2006-09-27 22:38:34 +08:00
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}
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2010-01-12 06:17:34 +08:00
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early_param("ecc", early_ecc);
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2006-09-27 22:38:34 +08:00
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static int __init noalign_setup(char *__unused)
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{
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cr_alignment &= ~CR_A;
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cr_no_alignment &= ~CR_A;
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set_cr(cr_alignment);
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return 1;
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}
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__setup("noalign", noalign_setup);
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2006-12-18 08:12:47 +08:00
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#ifndef CONFIG_SMP
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void adjust_cr(unsigned long mask, unsigned long set)
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{
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unsigned long flags;
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mask &= ~CR_A;
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set &= mask;
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local_irq_save(flags);
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cr_no_alignment = (cr_no_alignment & ~mask) | set;
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cr_alignment = (cr_alignment & ~mask) | set;
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set_cr((get_cr() & ~mask) | set);
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local_irq_restore(flags);
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}
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#endif
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2010-11-16 16:40:36 +08:00
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#define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN
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[ARM] mm: fix page table initialization
As a result of the ptebits changes, we ended up marking device mappings
as normal memory on ARMv7 CPUs, resulting in undesirable behaviour with
serial ports and the like. While reviewing the section mapping table
entries, other errors in the memory type settings for devices were
detected and confirmed to prevent Xscale3 platforms booting.
Tested on:
OMAP34xx (ARMv7),
OMAP24xx (ARMv6),
OMAP16xx (ARM926T, ARMv5),
PXA311 (Xscale3),
PXA272 (Xscale),
PXA255 (Xscale),
IXP42x (Xscale),
S3C2410 (ARM920T, ARMv4T),
ARM720T (ARMv4T)
StrongARM-110 (ARMv4)
Acked-by: Tony Lindgren <tony@atomide.com>
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr>
Tested-by: Mike Rapoport <mike@compulab.co.il>
Tested-by: Ben Dooks <ben-linux@fluff.org>
Tested-by: Anders Grafström <grfstrm@users.sourceforge.net>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-11-04 18:52:28 +08:00
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#define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_AP_WRITE
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2007-05-06 03:28:16 +08:00
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2007-04-21 17:47:29 +08:00
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static struct mem_type mem_types[] = {
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2007-05-06 03:28:16 +08:00
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[MT_DEVICE] = { /* Strongly ordered / ARMv6 shared device */
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2008-09-07 03:04:59 +08:00
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.prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED |
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L_PTE_SHARED,
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2007-05-06 03:28:16 +08:00
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.prot_l1 = PMD_TYPE_TABLE,
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[ARM] mm: fix page table initialization
As a result of the ptebits changes, we ended up marking device mappings
as normal memory on ARMv7 CPUs, resulting in undesirable behaviour with
serial ports and the like. While reviewing the section mapping table
entries, other errors in the memory type settings for devices were
detected and confirmed to prevent Xscale3 platforms booting.
Tested on:
OMAP34xx (ARMv7),
OMAP24xx (ARMv6),
OMAP16xx (ARM926T, ARMv5),
PXA311 (Xscale3),
PXA272 (Xscale),
PXA255 (Xscale),
IXP42x (Xscale),
S3C2410 (ARM920T, ARMv4T),
ARM720T (ARMv4T)
StrongARM-110 (ARMv4)
Acked-by: Tony Lindgren <tony@atomide.com>
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr>
Tested-by: Mike Rapoport <mike@compulab.co.il>
Tested-by: Ben Dooks <ben-linux@fluff.org>
Tested-by: Anders Grafström <grfstrm@users.sourceforge.net>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-11-04 18:52:28 +08:00
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.prot_sect = PROT_SECT_DEVICE | PMD_SECT_S,
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2007-05-06 03:28:16 +08:00
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.domain = DOMAIN_IO,
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},
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[MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */
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2008-09-07 03:04:59 +08:00
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.prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED,
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2007-05-06 03:28:16 +08:00
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.prot_l1 = PMD_TYPE_TABLE,
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[ARM] mm: fix page table initialization
As a result of the ptebits changes, we ended up marking device mappings
as normal memory on ARMv7 CPUs, resulting in undesirable behaviour with
serial ports and the like. While reviewing the section mapping table
entries, other errors in the memory type settings for devices were
detected and confirmed to prevent Xscale3 platforms booting.
Tested on:
OMAP34xx (ARMv7),
OMAP24xx (ARMv6),
OMAP16xx (ARM926T, ARMv5),
PXA311 (Xscale3),
PXA272 (Xscale),
PXA255 (Xscale),
IXP42x (Xscale),
S3C2410 (ARM920T, ARMv4T),
ARM720T (ARMv4T)
StrongARM-110 (ARMv4)
Acked-by: Tony Lindgren <tony@atomide.com>
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr>
Tested-by: Mike Rapoport <mike@compulab.co.il>
Tested-by: Ben Dooks <ben-linux@fluff.org>
Tested-by: Anders Grafström <grfstrm@users.sourceforge.net>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-11-04 18:52:28 +08:00
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.prot_sect = PROT_SECT_DEVICE,
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2007-05-06 03:28:16 +08:00
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.domain = DOMAIN_IO,
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},
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[MT_DEVICE_CACHED] = { /* ioremap_cached */
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2008-09-07 03:04:59 +08:00
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.prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED,
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2007-05-06 03:28:16 +08:00
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.prot_l1 = PMD_TYPE_TABLE,
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.prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB,
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.domain = DOMAIN_IO,
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},
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[ARM] 5241/1: provide ioremap_wc()
This patch provides an ARM implementation of ioremap_wc().
We use different page table attributes depending on which CPU we
are running on:
- Non-XScale ARMv5 and earlier systems: The ARMv5 ARM documents four
possible mapping types (CB=00/01/10/11). We can't use any of the
cached memory types (CB=10/11), since that breaks coherency with
peripheral devices. Both CB=00 and CB=01 are suitable for _wc, and
CB=01 (Uncached/Buffered) allows the hardware more freedom than
CB=00, so we'll use that.
(The ARMv5 ARM seems to suggest that CB=01 is allowed to delay stores
but isn't allowed to merge them, but there is no other mapping type
we can use that allows the hardware to delay and merge stores, so
we'll go with CB=01.)
- XScale v1/v2 (ARMv5): same as the ARMv5 case above, with the slight
difference that on these platforms, CB=01 actually _does_ allow
merging stores. (If you want noncoalescing bufferable behavior
on Xscale v1/v2, you need to use XCB=101.)
- Xscale v3 (ARMv5) and ARMv6+: on these systems, we use TEXCB=00100
mappings (Inner/Outer Uncacheable in xsc3 parlance, Uncached Normal
in ARMv6 parlance).
The ARMv6 ARM explicitly says that any accesses to Normal memory can
be merged, which makes Normal memory more suitable for _wc mappings
than Device or Strongly Ordered memory, as the latter two mapping
types are guaranteed to maintain transaction number, size and order.
We use the Uncached variety of Normal mappings for the same reason
that we can't use C=1 mappings on ARMv5.
The xsc3 Architecture Specification documents TEXCB=00100 as being
Uncacheable and allowing coalescing of writes, which is also just
what we need.
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-09-05 20:17:11 +08:00
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[MT_DEVICE_WC] = { /* ioremap_wc */
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2008-09-07 03:04:59 +08:00
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.prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC,
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2007-05-06 03:28:16 +08:00
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|
|
.prot_l1 = PMD_TYPE_TABLE,
|
[ARM] mm: fix page table initialization
As a result of the ptebits changes, we ended up marking device mappings
as normal memory on ARMv7 CPUs, resulting in undesirable behaviour with
serial ports and the like. While reviewing the section mapping table
entries, other errors in the memory type settings for devices were
detected and confirmed to prevent Xscale3 platforms booting.
Tested on:
OMAP34xx (ARMv7),
OMAP24xx (ARMv6),
OMAP16xx (ARM926T, ARMv5),
PXA311 (Xscale3),
PXA272 (Xscale),
PXA255 (Xscale),
IXP42x (Xscale),
S3C2410 (ARM920T, ARMv4T),
ARM720T (ARMv4T)
StrongARM-110 (ARMv4)
Acked-by: Tony Lindgren <tony@atomide.com>
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr>
Tested-by: Mike Rapoport <mike@compulab.co.il>
Tested-by: Ben Dooks <ben-linux@fluff.org>
Tested-by: Anders Grafström <grfstrm@users.sourceforge.net>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-11-04 18:52:28 +08:00
|
|
|
.prot_sect = PROT_SECT_DEVICE,
|
2007-05-06 03:28:16 +08:00
|
|
|
.domain = DOMAIN_IO,
|
2006-09-27 22:38:34 +08:00
|
|
|
},
|
2008-11-09 19:18:36 +08:00
|
|
|
[MT_UNCACHED] = {
|
|
|
|
|
.prot_pte = PROT_PTE_DEVICE,
|
|
|
|
|
.prot_l1 = PMD_TYPE_TABLE,
|
|
|
|
|
.prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
|
|
|
|
|
.domain = DOMAIN_IO,
|
|
|
|
|
},
|
2006-09-27 22:38:34 +08:00
|
|
|
[MT_CACHECLEAN] = {
|
2007-05-06 03:03:35 +08:00
|
|
|
.prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
|
2006-09-27 22:38:34 +08:00
|
|
|
.domain = DOMAIN_KERNEL,
|
|
|
|
|
},
|
|
|
|
|
[MT_MINICLEAN] = {
|
2007-05-06 03:03:35 +08:00
|
|
|
.prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE,
|
2006-09-27 22:38:34 +08:00
|
|
|
.domain = DOMAIN_KERNEL,
|
|
|
|
|
},
|
|
|
|
|
[MT_LOW_VECTORS] = {
|
|
|
|
|
.prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
|
2010-11-16 16:40:36 +08:00
|
|
|
L_PTE_RDONLY,
|
2006-09-27 22:38:34 +08:00
|
|
|
.prot_l1 = PMD_TYPE_TABLE,
|
|
|
|
|
.domain = DOMAIN_USER,
|
|
|
|
|
},
|
|
|
|
|
[MT_HIGH_VECTORS] = {
|
|
|
|
|
.prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
|
2010-11-16 16:40:36 +08:00
|
|
|
L_PTE_USER | L_PTE_RDONLY,
|
2006-09-27 22:38:34 +08:00
|
|
|
.prot_l1 = PMD_TYPE_TABLE,
|
|
|
|
|
.domain = DOMAIN_USER,
|
|
|
|
|
},
|
|
|
|
|
[MT_MEMORY] = {
|
2010-11-16 16:40:36 +08:00
|
|
|
.prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
|
2010-09-24 14:18:22 +08:00
|
|
|
.prot_l1 = PMD_TYPE_TABLE,
|
2007-05-06 03:03:35 +08:00
|
|
|
.prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
|
2006-09-27 22:38:34 +08:00
|
|
|
.domain = DOMAIN_KERNEL,
|
|
|
|
|
},
|
|
|
|
|
[MT_ROM] = {
|
2007-05-06 03:03:35 +08:00
|
|
|
.prot_sect = PMD_TYPE_SECT,
|
2006-09-27 22:38:34 +08:00
|
|
|
.domain = DOMAIN_KERNEL,
|
|
|
|
|
},
|
[ARM] 5422/1: ARM: MMU: add a Non-cacheable Normal executable memory type
This patch adds a Non-cacheable Normal ARM executable memory type,
MT_MEMORY_NONCACHED.
On OMAP3, this is used for rapid dynamic voltage/frequency scaling in
the VDD2 voltage domain. OMAP3's SDRAM controller (SDRC) is in the
VDD2 voltage domain, and its clock frequency must change along with
voltage. The SDRC clock change code cannot run from SDRAM itself,
since SDRAM accesses are paused during the clock change. So the
current implementation of the DVFS code executes from OMAP on-chip
SRAM, aka "OCM RAM."
If the OCM RAM pages are marked as Cacheable, the ARM cache controller
will attempt to flush dirty cache lines to the SDRC, so it can fill
those lines with OCM RAM instruction code. The problem is that the
SDRC is paused during DVFS, and so any SDRAM access causes the ARM MPU
subsystem to hang.
TI's original solution to this problem was to mark the OCM RAM
sections as Strongly Ordered memory, thus preventing caching. This is
overkill: since the memory is marked as non-bufferable, OCM RAM writes
become needlessly slow. The idea of "Strongly Ordered SRAM" is also
conceptually disturbing. Previous LAKML list discussion is here:
http://www.spinics.net/lists/arm-kernel/msg54312.html
This memory type MT_MEMORY_NONCACHED is used for OCM RAM by a future
patch.
Cc: Richard Woodruff <r-woodruff2@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-03-13 03:11:43 +08:00
|
|
|
[MT_MEMORY_NONCACHED] = {
|
2010-09-24 14:18:22 +08:00
|
|
|
.prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
|
2010-11-16 16:40:36 +08:00
|
|
|
L_PTE_MT_BUFFERABLE,
|
2010-09-24 14:18:22 +08:00
|
|
|
.prot_l1 = PMD_TYPE_TABLE,
|
[ARM] 5422/1: ARM: MMU: add a Non-cacheable Normal executable memory type
This patch adds a Non-cacheable Normal ARM executable memory type,
MT_MEMORY_NONCACHED.
On OMAP3, this is used for rapid dynamic voltage/frequency scaling in
the VDD2 voltage domain. OMAP3's SDRAM controller (SDRC) is in the
VDD2 voltage domain, and its clock frequency must change along with
voltage. The SDRC clock change code cannot run from SDRAM itself,
since SDRAM accesses are paused during the clock change. So the
current implementation of the DVFS code executes from OMAP on-chip
SRAM, aka "OCM RAM."
If the OCM RAM pages are marked as Cacheable, the ARM cache controller
will attempt to flush dirty cache lines to the SDRC, so it can fill
those lines with OCM RAM instruction code. The problem is that the
SDRC is paused during DVFS, and so any SDRAM access causes the ARM MPU
subsystem to hang.
TI's original solution to this problem was to mark the OCM RAM
sections as Strongly Ordered memory, thus preventing caching. This is
overkill: since the memory is marked as non-bufferable, OCM RAM writes
become needlessly slow. The idea of "Strongly Ordered SRAM" is also
conceptually disturbing. Previous LAKML list discussion is here:
http://www.spinics.net/lists/arm-kernel/msg54312.html
This memory type MT_MEMORY_NONCACHED is used for OCM RAM by a future
patch.
Cc: Richard Woodruff <r-woodruff2@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-03-13 03:11:43 +08:00
|
|
|
.prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
|
|
|
|
|
.domain = DOMAIN_KERNEL,
|
|
|
|
|
},
|
2010-07-13 04:50:59 +08:00
|
|
|
[MT_MEMORY_DTCM] = {
|
2010-10-18 16:03:03 +08:00
|
|
|
.prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
|
2010-11-16 16:40:36 +08:00
|
|
|
L_PTE_XN,
|
2010-10-18 16:03:03 +08:00
|
|
|
.prot_l1 = PMD_TYPE_TABLE,
|
|
|
|
|
.prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
|
|
|
|
|
.domain = DOMAIN_KERNEL,
|
2010-07-13 04:50:59 +08:00
|
|
|
},
|
|
|
|
|
[MT_MEMORY_ITCM] = {
|
2010-11-16 16:40:36 +08:00
|
|
|
.prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
|
2010-07-13 04:50:59 +08:00
|
|
|
.prot_l1 = PMD_TYPE_TABLE,
|
2010-10-18 16:03:03 +08:00
|
|
|
.domain = DOMAIN_KERNEL,
|
2010-07-13 04:50:59 +08:00
|
|
|
},
|
2006-09-27 22:38:34 +08:00
|
|
|
};
|
|
|
|
|
|
2007-04-21 17:47:29 +08:00
|
|
|
const struct mem_type *get_mem_type(unsigned int type)
|
|
|
|
|
{
|
|
|
|
|
return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL;
|
|
|
|
|
}
|
2009-01-29 03:32:08 +08:00
|
|
|
EXPORT_SYMBOL(get_mem_type);
|
2007-04-21 17:47:29 +08:00
|
|
|
|
2006-09-27 22:38:34 +08:00
|
|
|
/*
|
|
|
|
|
* Adjust the PMD section entries according to the CPU in use.
|
|
|
|
|
*/
|
|
|
|
|
static void __init build_mem_type_table(void)
|
|
|
|
|
{
|
|
|
|
|
struct cachepolicy *cp;
|
|
|
|
|
unsigned int cr = get_cr();
|
2008-09-07 03:04:59 +08:00
|
|
|
unsigned int user_pgprot, kern_pgprot, vecs_pgprot;
|
2006-09-27 22:38:34 +08:00
|
|
|
int cpu_arch = cpu_architecture();
|
|
|
|
|
int i;
|
|
|
|
|
|
2007-07-20 18:42:24 +08:00
|
|
|
if (cpu_arch < CPU_ARCH_ARMv6) {
|
2006-09-27 22:38:34 +08:00
|
|
|
#if defined(CONFIG_CPU_DCACHE_DISABLE)
|
2007-07-20 18:42:24 +08:00
|
|
|
if (cachepolicy > CPOLICY_BUFFERED)
|
|
|
|
|
cachepolicy = CPOLICY_BUFFERED;
|
2006-09-27 22:38:34 +08:00
|
|
|
#elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
|
2007-07-20 18:42:24 +08:00
|
|
|
if (cachepolicy > CPOLICY_WRITETHROUGH)
|
|
|
|
|
cachepolicy = CPOLICY_WRITETHROUGH;
|
2006-09-27 22:38:34 +08:00
|
|
|
#endif
|
2007-07-20 18:42:24 +08:00
|
|
|
}
|
2006-09-27 22:38:34 +08:00
|
|
|
if (cpu_arch < CPU_ARCH_ARMv5) {
|
|
|
|
|
if (cachepolicy >= CPOLICY_WRITEALLOC)
|
|
|
|
|
cachepolicy = CPOLICY_WRITEBACK;
|
|
|
|
|
ecc_mask = 0;
|
|
|
|
|
}
|
2010-09-04 17:47:48 +08:00
|
|
|
if (is_smp())
|
|
|
|
|
cachepolicy = CPOLICY_WRITEALLOC;
|
2006-09-27 22:38:34 +08:00
|
|
|
|
[ARM] 5241/1: provide ioremap_wc()
This patch provides an ARM implementation of ioremap_wc().
We use different page table attributes depending on which CPU we
are running on:
- Non-XScale ARMv5 and earlier systems: The ARMv5 ARM documents four
possible mapping types (CB=00/01/10/11). We can't use any of the
cached memory types (CB=10/11), since that breaks coherency with
peripheral devices. Both CB=00 and CB=01 are suitable for _wc, and
CB=01 (Uncached/Buffered) allows the hardware more freedom than
CB=00, so we'll use that.
(The ARMv5 ARM seems to suggest that CB=01 is allowed to delay stores
but isn't allowed to merge them, but there is no other mapping type
we can use that allows the hardware to delay and merge stores, so
we'll go with CB=01.)
- XScale v1/v2 (ARMv5): same as the ARMv5 case above, with the slight
difference that on these platforms, CB=01 actually _does_ allow
merging stores. (If you want noncoalescing bufferable behavior
on Xscale v1/v2, you need to use XCB=101.)
- Xscale v3 (ARMv5) and ARMv6+: on these systems, we use TEXCB=00100
mappings (Inner/Outer Uncacheable in xsc3 parlance, Uncached Normal
in ARMv6 parlance).
The ARMv6 ARM explicitly says that any accesses to Normal memory can
be merged, which makes Normal memory more suitable for _wc mappings
than Device or Strongly Ordered memory, as the latter two mapping
types are guaranteed to maintain transaction number, size and order.
We use the Uncached variety of Normal mappings for the same reason
that we can't use C=1 mappings on ARMv5.
The xsc3 Architecture Specification documents TEXCB=00100 as being
Uncacheable and allowing coalescing of writes, which is also just
what we need.
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-09-05 20:17:11 +08:00
|
|
|
/*
|
[ARM] mm: fix page table initialization
As a result of the ptebits changes, we ended up marking device mappings
as normal memory on ARMv7 CPUs, resulting in undesirable behaviour with
serial ports and the like. While reviewing the section mapping table
entries, other errors in the memory type settings for devices were
detected and confirmed to prevent Xscale3 platforms booting.
Tested on:
OMAP34xx (ARMv7),
OMAP24xx (ARMv6),
OMAP16xx (ARM926T, ARMv5),
PXA311 (Xscale3),
PXA272 (Xscale),
PXA255 (Xscale),
IXP42x (Xscale),
S3C2410 (ARM920T, ARMv4T),
ARM720T (ARMv4T)
StrongARM-110 (ARMv4)
Acked-by: Tony Lindgren <tony@atomide.com>
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr>
Tested-by: Mike Rapoport <mike@compulab.co.il>
Tested-by: Ben Dooks <ben-linux@fluff.org>
Tested-by: Anders Grafström <grfstrm@users.sourceforge.net>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-11-04 18:52:28 +08:00
|
|
|
* Strip out features not present on earlier architectures.
|
|
|
|
|
* Pre-ARMv5 CPUs don't have TEX bits. Pre-ARMv6 CPUs or those
|
|
|
|
|
* without extended page tables don't have the 'Shared' bit.
|
[ARM] 5241/1: provide ioremap_wc()
This patch provides an ARM implementation of ioremap_wc().
We use different page table attributes depending on which CPU we
are running on:
- Non-XScale ARMv5 and earlier systems: The ARMv5 ARM documents four
possible mapping types (CB=00/01/10/11). We can't use any of the
cached memory types (CB=10/11), since that breaks coherency with
peripheral devices. Both CB=00 and CB=01 are suitable for _wc, and
CB=01 (Uncached/Buffered) allows the hardware more freedom than
CB=00, so we'll use that.
(The ARMv5 ARM seems to suggest that CB=01 is allowed to delay stores
but isn't allowed to merge them, but there is no other mapping type
we can use that allows the hardware to delay and merge stores, so
we'll go with CB=01.)
- XScale v1/v2 (ARMv5): same as the ARMv5 case above, with the slight
difference that on these platforms, CB=01 actually _does_ allow
merging stores. (If you want noncoalescing bufferable behavior
on Xscale v1/v2, you need to use XCB=101.)
- Xscale v3 (ARMv5) and ARMv6+: on these systems, we use TEXCB=00100
mappings (Inner/Outer Uncacheable in xsc3 parlance, Uncached Normal
in ARMv6 parlance).
The ARMv6 ARM explicitly says that any accesses to Normal memory can
be merged, which makes Normal memory more suitable for _wc mappings
than Device or Strongly Ordered memory, as the latter two mapping
types are guaranteed to maintain transaction number, size and order.
We use the Uncached variety of Normal mappings for the same reason
that we can't use C=1 mappings on ARMv5.
The xsc3 Architecture Specification documents TEXCB=00100 as being
Uncacheable and allowing coalescing of writes, which is also just
what we need.
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-09-05 20:17:11 +08:00
|
|
|
*/
|
[ARM] mm: fix page table initialization
As a result of the ptebits changes, we ended up marking device mappings
as normal memory on ARMv7 CPUs, resulting in undesirable behaviour with
serial ports and the like. While reviewing the section mapping table
entries, other errors in the memory type settings for devices were
detected and confirmed to prevent Xscale3 platforms booting.
Tested on:
OMAP34xx (ARMv7),
OMAP24xx (ARMv6),
OMAP16xx (ARM926T, ARMv5),
PXA311 (Xscale3),
PXA272 (Xscale),
PXA255 (Xscale),
IXP42x (Xscale),
S3C2410 (ARM920T, ARMv4T),
ARM720T (ARMv4T)
StrongARM-110 (ARMv4)
Acked-by: Tony Lindgren <tony@atomide.com>
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr>
Tested-by: Mike Rapoport <mike@compulab.co.il>
Tested-by: Ben Dooks <ben-linux@fluff.org>
Tested-by: Anders Grafström <grfstrm@users.sourceforge.net>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-11-04 18:52:28 +08:00
|
|
|
if (cpu_arch < CPU_ARCH_ARMv5)
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(mem_types); i++)
|
|
|
|
|
mem_types[i].prot_sect &= ~PMD_SECT_TEX(7);
|
|
|
|
|
if ((cpu_arch < CPU_ARCH_ARMv6 || !(cr & CR_XP)) && !cpu_is_xsc3())
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(mem_types); i++)
|
|
|
|
|
mem_types[i].prot_sect &= ~PMD_SECT_S;
|
2006-09-27 22:38:34 +08:00
|
|
|
|
|
|
|
|
/*
|
[ARM] mm: fix page table initialization
As a result of the ptebits changes, we ended up marking device mappings
as normal memory on ARMv7 CPUs, resulting in undesirable behaviour with
serial ports and the like. While reviewing the section mapping table
entries, other errors in the memory type settings for devices were
detected and confirmed to prevent Xscale3 platforms booting.
Tested on:
OMAP34xx (ARMv7),
OMAP24xx (ARMv6),
OMAP16xx (ARM926T, ARMv5),
PXA311 (Xscale3),
PXA272 (Xscale),
PXA255 (Xscale),
IXP42x (Xscale),
S3C2410 (ARM920T, ARMv4T),
ARM720T (ARMv4T)
StrongARM-110 (ARMv4)
Acked-by: Tony Lindgren <tony@atomide.com>
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr>
Tested-by: Mike Rapoport <mike@compulab.co.il>
Tested-by: Ben Dooks <ben-linux@fluff.org>
Tested-by: Anders Grafström <grfstrm@users.sourceforge.net>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-11-04 18:52:28 +08:00
|
|
|
* ARMv5 and lower, bit 4 must be set for page tables (was: cache
|
|
|
|
|
* "update-able on write" bit on ARM610). However, Xscale and
|
|
|
|
|
* Xscale3 require this bit to be cleared.
|
2006-09-27 22:38:34 +08:00
|
|
|
*/
|
[ARM] mm: fix page table initialization
As a result of the ptebits changes, we ended up marking device mappings
as normal memory on ARMv7 CPUs, resulting in undesirable behaviour with
serial ports and the like. While reviewing the section mapping table
entries, other errors in the memory type settings for devices were
detected and confirmed to prevent Xscale3 platforms booting.
Tested on:
OMAP34xx (ARMv7),
OMAP24xx (ARMv6),
OMAP16xx (ARM926T, ARMv5),
PXA311 (Xscale3),
PXA272 (Xscale),
PXA255 (Xscale),
IXP42x (Xscale),
S3C2410 (ARM920T, ARMv4T),
ARM720T (ARMv4T)
StrongARM-110 (ARMv4)
Acked-by: Tony Lindgren <tony@atomide.com>
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr>
Tested-by: Mike Rapoport <mike@compulab.co.il>
Tested-by: Ben Dooks <ben-linux@fluff.org>
Tested-by: Anders Grafström <grfstrm@users.sourceforge.net>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-11-04 18:52:28 +08:00
|
|
|
if (cpu_is_xscale() || cpu_is_xsc3()) {
|
2007-05-06 03:03:35 +08:00
|
|
|
for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
|
2006-09-27 22:38:34 +08:00
|
|
|
mem_types[i].prot_sect &= ~PMD_BIT4;
|
2007-05-06 03:03:35 +08:00
|
|
|
mem_types[i].prot_l1 &= ~PMD_BIT4;
|
|
|
|
|
}
|
|
|
|
|
} else if (cpu_arch < CPU_ARCH_ARMv6) {
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
|
2006-09-27 22:38:34 +08:00
|
|
|
if (mem_types[i].prot_l1)
|
|
|
|
|
mem_types[i].prot_l1 |= PMD_BIT4;
|
2007-05-06 03:03:35 +08:00
|
|
|
if (mem_types[i].prot_sect)
|
|
|
|
|
mem_types[i].prot_sect |= PMD_BIT4;
|
|
|
|
|
}
|
|
|
|
|
}
|
2006-09-27 22:38:34 +08:00
|
|
|
|
[ARM] mm: fix page table initialization
As a result of the ptebits changes, we ended up marking device mappings
as normal memory on ARMv7 CPUs, resulting in undesirable behaviour with
serial ports and the like. While reviewing the section mapping table
entries, other errors in the memory type settings for devices were
detected and confirmed to prevent Xscale3 platforms booting.
Tested on:
OMAP34xx (ARMv7),
OMAP24xx (ARMv6),
OMAP16xx (ARM926T, ARMv5),
PXA311 (Xscale3),
PXA272 (Xscale),
PXA255 (Xscale),
IXP42x (Xscale),
S3C2410 (ARM920T, ARMv4T),
ARM720T (ARMv4T)
StrongARM-110 (ARMv4)
Acked-by: Tony Lindgren <tony@atomide.com>
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr>
Tested-by: Mike Rapoport <mike@compulab.co.il>
Tested-by: Ben Dooks <ben-linux@fluff.org>
Tested-by: Anders Grafström <grfstrm@users.sourceforge.net>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-11-04 18:52:28 +08:00
|
|
|
/*
|
|
|
|
|
* Mark the device areas according to the CPU/architecture.
|
|
|
|
|
*/
|
|
|
|
|
if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) {
|
|
|
|
|
if (!cpu_is_xsc3()) {
|
|
|
|
|
/*
|
|
|
|
|
* Mark device regions on ARMv6+ as execute-never
|
|
|
|
|
* to prevent speculative instruction fetches.
|
|
|
|
|
*/
|
|
|
|
|
mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN;
|
|
|
|
|
mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN;
|
|
|
|
|
mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN;
|
|
|
|
|
mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN;
|
|
|
|
|
}
|
|
|
|
|
if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
|
|
|
|
|
/*
|
|
|
|
|
* For ARMv7 with TEX remapping,
|
|
|
|
|
* - shared device is SXCB=1100
|
|
|
|
|
* - nonshared device is SXCB=0100
|
|
|
|
|
* - write combine device mem is SXCB=0001
|
|
|
|
|
* (Uncached Normal memory)
|
|
|
|
|
*/
|
|
|
|
|
mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1);
|
|
|
|
|
mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1);
|
|
|
|
|
mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
|
|
|
|
|
} else if (cpu_is_xsc3()) {
|
|
|
|
|
/*
|
|
|
|
|
* For Xscale3,
|
|
|
|
|
* - shared device is TEXCB=00101
|
|
|
|
|
* - nonshared device is TEXCB=01000
|
|
|
|
|
* - write combine device mem is TEXCB=00100
|
|
|
|
|
* (Inner/Outer Uncacheable in xsc3 parlance)
|
|
|
|
|
*/
|
|
|
|
|
mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED;
|
|
|
|
|
mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
|
|
|
|
|
mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
|
|
|
|
|
} else {
|
|
|
|
|
/*
|
|
|
|
|
* For ARMv6 and ARMv7 without TEX remapping,
|
|
|
|
|
* - shared device is TEXCB=00001
|
|
|
|
|
* - nonshared device is TEXCB=01000
|
|
|
|
|
* - write combine device mem is TEXCB=00100
|
|
|
|
|
* (Uncached Normal in ARMv6 parlance).
|
|
|
|
|
*/
|
|
|
|
|
mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
|
|
|
|
|
mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
|
|
|
|
|
mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
|
|
|
|
|
}
|
|
|
|
|
} else {
|
|
|
|
|
/*
|
|
|
|
|
* On others, write combining is "Uncached/Buffered"
|
|
|
|
|
*/
|
|
|
|
|
mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Now deal with the memory-type mappings
|
|
|
|
|
*/
|
2006-09-27 22:38:34 +08:00
|
|
|
cp = &cache_policies[cachepolicy];
|
2008-09-07 03:04:59 +08:00
|
|
|
vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Only use write-through for non-SMP systems
|
|
|
|
|
*/
|
2010-09-04 17:47:48 +08:00
|
|
|
if (!is_smp() && cpu_arch >= CPU_ARCH_ARMv5 && cachepolicy > CPOLICY_WRITETHROUGH)
|
2008-09-07 03:04:59 +08:00
|
|
|
vecs_pgprot = cache_policies[CPOLICY_WRITETHROUGH].pte;
|
2006-09-27 22:38:34 +08:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Enable CPU-specific coherency if supported.
|
|
|
|
|
* (Only available on XSC3 at the moment.)
|
|
|
|
|
*/
|
2010-09-24 14:18:22 +08:00
|
|
|
if (arch_is_coherent() && cpu_is_xsc3()) {
|
[ARM] mm: fix page table initialization
As a result of the ptebits changes, we ended up marking device mappings
as normal memory on ARMv7 CPUs, resulting in undesirable behaviour with
serial ports and the like. While reviewing the section mapping table
entries, other errors in the memory type settings for devices were
detected and confirmed to prevent Xscale3 platforms booting.
Tested on:
OMAP34xx (ARMv7),
OMAP24xx (ARMv6),
OMAP16xx (ARM926T, ARMv5),
PXA311 (Xscale3),
PXA272 (Xscale),
PXA255 (Xscale),
IXP42x (Xscale),
S3C2410 (ARM920T, ARMv4T),
ARM720T (ARMv4T)
StrongARM-110 (ARMv4)
Acked-by: Tony Lindgren <tony@atomide.com>
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr>
Tested-by: Mike Rapoport <mike@compulab.co.il>
Tested-by: Ben Dooks <ben-linux@fluff.org>
Tested-by: Anders Grafström <grfstrm@users.sourceforge.net>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-11-04 18:52:28 +08:00
|
|
|
mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
|
2010-09-24 14:18:22 +08:00
|
|
|
mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED;
|
|
|
|
|
mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
|
|
|
|
|
mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED;
|
|
|
|
|
}
|
2006-09-27 22:38:34 +08:00
|
|
|
/*
|
|
|
|
|
* ARMv6 and above have extended page tables.
|
|
|
|
|
*/
|
|
|
|
|
if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
|
|
|
|
|
/*
|
|
|
|
|
* Mark cache clean areas and XIP ROM read only
|
|
|
|
|
* from SVC mode and no access from userspace.
|
|
|
|
|
*/
|
|
|
|
|
mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
|
|
|
|
|
mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
|
|
|
|
|
mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
|
|
|
|
|
|
2010-09-04 17:47:48 +08:00
|
|
|
if (is_smp()) {
|
|
|
|
|
/*
|
|
|
|
|
* Mark memory with the "shared" attribute
|
|
|
|
|
* for SMP systems
|
|
|
|
|
*/
|
|
|
|
|
user_pgprot |= L_PTE_SHARED;
|
|
|
|
|
kern_pgprot |= L_PTE_SHARED;
|
|
|
|
|
vecs_pgprot |= L_PTE_SHARED;
|
|
|
|
|
mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
|
|
|
|
|
mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
|
|
|
|
|
mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
|
|
|
|
|
mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
|
|
|
|
|
mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
|
|
|
|
|
mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED;
|
|
|
|
|
mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
|
|
|
|
|
mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED;
|
|
|
|
|
}
|
2006-09-27 22:38:34 +08:00
|
|
|
}
|
|
|
|
|
|
[ARM] 5422/1: ARM: MMU: add a Non-cacheable Normal executable memory type
This patch adds a Non-cacheable Normal ARM executable memory type,
MT_MEMORY_NONCACHED.
On OMAP3, this is used for rapid dynamic voltage/frequency scaling in
the VDD2 voltage domain. OMAP3's SDRAM controller (SDRC) is in the
VDD2 voltage domain, and its clock frequency must change along with
voltage. The SDRC clock change code cannot run from SDRAM itself,
since SDRAM accesses are paused during the clock change. So the
current implementation of the DVFS code executes from OMAP on-chip
SRAM, aka "OCM RAM."
If the OCM RAM pages are marked as Cacheable, the ARM cache controller
will attempt to flush dirty cache lines to the SDRC, so it can fill
those lines with OCM RAM instruction code. The problem is that the
SDRC is paused during DVFS, and so any SDRAM access causes the ARM MPU
subsystem to hang.
TI's original solution to this problem was to mark the OCM RAM
sections as Strongly Ordered memory, thus preventing caching. This is
overkill: since the memory is marked as non-bufferable, OCM RAM writes
become needlessly slow. The idea of "Strongly Ordered SRAM" is also
conceptually disturbing. Previous LAKML list discussion is here:
http://www.spinics.net/lists/arm-kernel/msg54312.html
This memory type MT_MEMORY_NONCACHED is used for OCM RAM by a future
patch.
Cc: Richard Woodruff <r-woodruff2@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-03-13 03:11:43 +08:00
|
|
|
/*
|
|
|
|
|
* Non-cacheable Normal - intended for memory areas that must
|
|
|
|
|
* not cause dirty cache line writebacks when used
|
|
|
|
|
*/
|
|
|
|
|
if (cpu_arch >= CPU_ARCH_ARMv6) {
|
|
|
|
|
if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
|
|
|
|
|
/* Non-cacheable Normal is XCB = 001 */
|
|
|
|
|
mem_types[MT_MEMORY_NONCACHED].prot_sect |=
|
|
|
|
|
PMD_SECT_BUFFERED;
|
|
|
|
|
} else {
|
|
|
|
|
/* For both ARMv6 and non-TEX-remapping ARMv7 */
|
|
|
|
|
mem_types[MT_MEMORY_NONCACHED].prot_sect |=
|
|
|
|
|
PMD_SECT_TEX(1);
|
|
|
|
|
}
|
|
|
|
|
} else {
|
|
|
|
|
mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE;
|
|
|
|
|
}
|
|
|
|
|
|
2006-09-27 22:38:34 +08:00
|
|
|
for (i = 0; i < 16; i++) {
|
|
|
|
|
unsigned long v = pgprot_val(protection_map[i]);
|
2008-09-07 03:04:59 +08:00
|
|
|
protection_map[i] = __pgprot(v | user_pgprot);
|
2006-09-27 22:38:34 +08:00
|
|
|
}
|
|
|
|
|
|
2008-09-07 03:04:59 +08:00
|
|
|
mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot;
|
|
|
|
|
mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot;
|
2006-09-27 22:38:34 +08:00
|
|
|
|
2007-02-11 20:45:13 +08:00
|
|
|
pgprot_user = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot);
|
2006-09-27 22:38:34 +08:00
|
|
|
pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
|
2010-11-16 16:40:36 +08:00
|
|
|
L_PTE_DIRTY | kern_pgprot);
|
2006-09-27 22:38:34 +08:00
|
|
|
|
|
|
|
|
mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
|
|
|
|
|
mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
|
|
|
|
|
mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd;
|
2010-09-24 14:18:22 +08:00
|
|
|
mem_types[MT_MEMORY].prot_pte |= kern_pgprot;
|
|
|
|
|
mem_types[MT_MEMORY_NONCACHED].prot_sect |= ecc_mask;
|
2006-09-27 22:38:34 +08:00
|
|
|
mem_types[MT_ROM].prot_sect |= cp->pmd;
|
|
|
|
|
|
|
|
|
|
switch (cp->pmd) {
|
|
|
|
|
case PMD_SECT_WT:
|
|
|
|
|
mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT;
|
|
|
|
|
break;
|
|
|
|
|
case PMD_SECT_WB:
|
|
|
|
|
case PMD_SECT_WBWA:
|
|
|
|
|
mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
printk("Memory policy: ECC %sabled, Data cache %s\n",
|
|
|
|
|
ecc_mask ? "en" : "dis", cp->policy);
|
2007-04-21 16:59:44 +08:00
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
|
|
|
|
|
struct mem_type *t = &mem_types[i];
|
|
|
|
|
if (t->prot_l1)
|
|
|
|
|
t->prot_l1 |= PMD_DOMAIN(t->domain);
|
|
|
|
|
if (t->prot_sect)
|
|
|
|
|
t->prot_sect |= PMD_DOMAIN(t->domain);
|
|
|
|
|
}
|
2006-09-27 22:38:34 +08:00
|
|
|
}
|
|
|
|
|
|
2010-09-13 23:01:24 +08:00
|
|
|
#ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
|
|
|
|
|
pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
|
|
|
|
|
unsigned long size, pgprot_t vma_prot)
|
|
|
|
|
{
|
|
|
|
|
if (!pfn_valid(pfn))
|
|
|
|
|
return pgprot_noncached(vma_prot);
|
|
|
|
|
else if (file->f_flags & O_SYNC)
|
|
|
|
|
return pgprot_writecombine(vma_prot);
|
|
|
|
|
return vma_prot;
|
|
|
|
|
}
|
|
|
|
|
EXPORT_SYMBOL(phys_mem_access_prot);
|
|
|
|
|
#endif
|
|
|
|
|
|
2006-09-27 22:38:34 +08:00
|
|
|
#define vectors_base() (vectors_high() ? 0xffff0000 : 0)
|
|
|
|
|
|
2010-03-26 01:02:59 +08:00
|
|
|
static void __init *early_alloc(unsigned long sz)
|
|
|
|
|
{
|
2010-07-09 23:27:52 +08:00
|
|
|
void *ptr = __va(memblock_alloc(sz, sz));
|
|
|
|
|
memset(ptr, 0, sz);
|
|
|
|
|
return ptr;
|
2010-03-26 01:02:59 +08:00
|
|
|
}
|
|
|
|
|
|
2010-07-02 01:33:29 +08:00
|
|
|
static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr, unsigned long prot)
|
2006-09-27 22:38:34 +08:00
|
|
|
{
|
2007-04-21 17:21:28 +08:00
|
|
|
if (pmd_none(*pmd)) {
|
2011-02-14 19:58:04 +08:00
|
|
|
pte_t *pte = early_alloc(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE);
|
2010-11-16 08:16:01 +08:00
|
|
|
__pmd_populate(pmd, __pa(pte), prot);
|
2007-04-21 17:21:28 +08:00
|
|
|
}
|
2010-07-02 01:33:29 +08:00
|
|
|
BUG_ON(pmd_bad(*pmd));
|
|
|
|
|
return pte_offset_kernel(pmd, addr);
|
|
|
|
|
}
|
2006-09-27 22:38:34 +08:00
|
|
|
|
2010-07-02 01:33:29 +08:00
|
|
|
static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
|
|
|
|
|
unsigned long end, unsigned long pfn,
|
|
|
|
|
const struct mem_type *type)
|
|
|
|
|
{
|
|
|
|
|
pte_t *pte = early_pte_alloc(pmd, addr, type->prot_l1);
|
2007-04-21 17:21:28 +08:00
|
|
|
do {
|
2008-09-07 04:15:56 +08:00
|
|
|
set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), 0);
|
2007-04-21 17:21:28 +08:00
|
|
|
pfn++;
|
|
|
|
|
} while (pte++, addr += PAGE_SIZE, addr != end);
|
2006-09-27 22:38:34 +08:00
|
|
|
}
|
|
|
|
|
|
2010-11-22 00:27:49 +08:00
|
|
|
static void __init alloc_init_section(pud_t *pud, unsigned long addr,
|
2010-11-16 08:16:01 +08:00
|
|
|
unsigned long end, phys_addr_t phys,
|
2007-04-21 17:21:28 +08:00
|
|
|
const struct mem_type *type)
|
2006-09-27 22:38:34 +08:00
|
|
|
{
|
2010-11-22 00:27:49 +08:00
|
|
|
pmd_t *pmd = pmd_offset(pud, addr);
|
2006-09-27 22:38:34 +08:00
|
|
|
|
2007-04-21 17:21:28 +08:00
|
|
|
/*
|
|
|
|
|
* Try a section mapping - end, addr and phys must all be aligned
|
|
|
|
|
* to a section boundary. Note that PMDs refer to the individual
|
|
|
|
|
* L1 entries, whereas PGDs refer to a group of L1 entries making
|
|
|
|
|
* up one logical pointer to an L2 table.
|
|
|
|
|
*/
|
|
|
|
|
if (((addr | end | phys) & ~SECTION_MASK) == 0) {
|
|
|
|
|
pmd_t *p = pmd;
|
2006-09-27 22:38:34 +08:00
|
|
|
|
2007-04-21 17:21:28 +08:00
|
|
|
if (addr & SECTION_SIZE)
|
|
|
|
|
pmd++;
|
|
|
|
|
|
|
|
|
|
do {
|
|
|
|
|
*pmd = __pmd(phys | type->prot_sect);
|
|
|
|
|
phys += SECTION_SIZE;
|
|
|
|
|
} while (pmd++, addr += SECTION_SIZE, addr != end);
|
2006-09-27 22:38:34 +08:00
|
|
|
|
2007-04-21 17:21:28 +08:00
|
|
|
flush_pmd_entry(p);
|
|
|
|
|
} else {
|
|
|
|
|
/*
|
|
|
|
|
* No need to loop; pte's aren't interested in the
|
|
|
|
|
* individual L1 entries.
|
|
|
|
|
*/
|
|
|
|
|
alloc_init_pte(pmd, addr, end, __phys_to_pfn(phys), type);
|
|
|
|
|
}
|
2006-09-27 22:38:34 +08:00
|
|
|
}
|
|
|
|
|
|
2010-11-22 00:27:49 +08:00
|
|
|
static void alloc_init_pud(pgd_t *pgd, unsigned long addr, unsigned long end,
|
|
|
|
|
unsigned long phys, const struct mem_type *type)
|
|
|
|
|
{
|
|
|
|
|
pud_t *pud = pud_offset(pgd, addr);
|
|
|
|
|
unsigned long next;
|
|
|
|
|
|
|
|
|
|
do {
|
|
|
|
|
next = pud_addr_end(addr, end);
|
|
|
|
|
alloc_init_section(pud, addr, next, phys, type);
|
|
|
|
|
phys += next - addr;
|
|
|
|
|
} while (pud++, addr = next, addr != end);
|
|
|
|
|
}
|
|
|
|
|
|
2007-04-21 17:16:48 +08:00
|
|
|
static void __init create_36bit_mapping(struct map_desc *md,
|
|
|
|
|
const struct mem_type *type)
|
|
|
|
|
{
|
2010-11-16 08:16:01 +08:00
|
|
|
unsigned long addr, length, end;
|
|
|
|
|
phys_addr_t phys;
|
2007-04-21 17:16:48 +08:00
|
|
|
pgd_t *pgd;
|
|
|
|
|
|
|
|
|
|
addr = md->virtual;
|
2011-02-15 19:42:57 +08:00
|
|
|
phys = __pfn_to_phys(md->pfn);
|
2007-04-21 17:16:48 +08:00
|
|
|
length = PAGE_ALIGN(md->length);
|
|
|
|
|
|
|
|
|
|
if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) {
|
|
|
|
|
printk(KERN_ERR "MM: CPU does not support supersection "
|
|
|
|
|
"mapping for 0x%08llx at 0x%08lx\n",
|
2011-02-15 21:31:37 +08:00
|
|
|
(long long)__pfn_to_phys((u64)md->pfn), addr);
|
2007-04-21 17:16:48 +08:00
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* N.B. ARMv6 supersections are only defined to work with domain 0.
|
|
|
|
|
* Since domain assignments can in fact be arbitrary, the
|
|
|
|
|
* 'domain == 0' check below is required to insure that ARMv6
|
|
|
|
|
* supersections are only allocated for domain 0 regardless
|
|
|
|
|
* of the actual domain assignments in use.
|
|
|
|
|
*/
|
|
|
|
|
if (type->domain) {
|
|
|
|
|
printk(KERN_ERR "MM: invalid domain in supersection "
|
|
|
|
|
"mapping for 0x%08llx at 0x%08lx\n",
|
2011-02-15 21:31:37 +08:00
|
|
|
(long long)__pfn_to_phys((u64)md->pfn), addr);
|
2007-04-21 17:16:48 +08:00
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) {
|
2011-02-15 21:31:37 +08:00
|
|
|
printk(KERN_ERR "MM: cannot create mapping for 0x%08llx"
|
|
|
|
|
" at 0x%08lx invalid alignment\n",
|
|
|
|
|
(long long)__pfn_to_phys((u64)md->pfn), addr);
|
2007-04-21 17:16:48 +08:00
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Shift bits [35:32] of address into bits [23:20] of PMD
|
|
|
|
|
* (See ARMv6 spec).
|
|
|
|
|
*/
|
|
|
|
|
phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20);
|
|
|
|
|
|
|
|
|
|
pgd = pgd_offset_k(addr);
|
|
|
|
|
end = addr + length;
|
|
|
|
|
do {
|
2010-11-22 00:27:49 +08:00
|
|
|
pud_t *pud = pud_offset(pgd, addr);
|
|
|
|
|
pmd_t *pmd = pmd_offset(pud, addr);
|
2007-04-21 17:16:48 +08:00
|
|
|
int i;
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < 16; i++)
|
|
|
|
|
*pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER);
|
|
|
|
|
|
|
|
|
|
addr += SUPERSECTION_SIZE;
|
|
|
|
|
phys += SUPERSECTION_SIZE;
|
|
|
|
|
pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT;
|
|
|
|
|
} while (addr != end);
|
|
|
|
|
}
|
|
|
|
|
|
2006-09-27 22:38:34 +08:00
|
|
|
/*
|
|
|
|
|
* Create the page directory entries and any necessary
|
|
|
|
|
* page tables for the mapping specified by `md'. We
|
|
|
|
|
* are able to cope here with varying sizes and address
|
|
|
|
|
* offsets, and we take full advantage of sections and
|
|
|
|
|
* supersections.
|
|
|
|
|
*/
|
2010-03-26 02:56:05 +08:00
|
|
|
static void __init create_mapping(struct map_desc *md)
|
2006-09-27 22:38:34 +08:00
|
|
|
{
|
2011-02-15 19:42:57 +08:00
|
|
|
unsigned long addr, length, end;
|
|
|
|
|
phys_addr_t phys;
|
2007-04-21 17:05:32 +08:00
|
|
|
const struct mem_type *type;
|
2007-04-21 17:21:28 +08:00
|
|
|
pgd_t *pgd;
|
2006-09-27 22:38:34 +08:00
|
|
|
|
|
|
|
|
if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) {
|
2011-02-15 21:31:37 +08:00
|
|
|
printk(KERN_WARNING "BUG: not creating mapping for 0x%08llx"
|
|
|
|
|
" at 0x%08lx in user region\n",
|
|
|
|
|
(long long)__pfn_to_phys((u64)md->pfn), md->virtual);
|
2006-09-27 22:38:34 +08:00
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if ((md->type == MT_DEVICE || md->type == MT_ROM) &&
|
|
|
|
|
md->virtual >= PAGE_OFFSET && md->virtual < VMALLOC_END) {
|
2011-02-15 21:31:37 +08:00
|
|
|
printk(KERN_WARNING "BUG: mapping for 0x%08llx"
|
|
|
|
|
" at 0x%08lx overlaps vmalloc space\n",
|
|
|
|
|
(long long)__pfn_to_phys((u64)md->pfn), md->virtual);
|
2006-09-27 22:38:34 +08:00
|
|
|
}
|
|
|
|
|
|
2007-04-21 17:05:32 +08:00
|
|
|
type = &mem_types[md->type];
|
2006-09-27 22:38:34 +08:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Catch 36-bit addresses
|
|
|
|
|
*/
|
2007-04-21 17:16:48 +08:00
|
|
|
if (md->pfn >= 0x100000) {
|
|
|
|
|
create_36bit_mapping(md, type);
|
|
|
|
|
return;
|
2006-09-27 22:38:34 +08:00
|
|
|
}
|
|
|
|
|
|
2007-07-05 04:16:33 +08:00
|
|
|
addr = md->virtual & PAGE_MASK;
|
2011-02-15 19:42:57 +08:00
|
|
|
phys = __pfn_to_phys(md->pfn);
|
2007-07-05 04:16:33 +08:00
|
|
|
length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
|
2006-09-27 22:38:34 +08:00
|
|
|
|
2007-04-21 17:21:28 +08:00
|
|
|
if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) {
|
2011-02-15 21:31:37 +08:00
|
|
|
printk(KERN_WARNING "BUG: map for 0x%08llx at 0x%08lx can not "
|
2006-09-27 22:38:34 +08:00
|
|
|
"be mapped using pages, ignoring.\n",
|
2011-02-15 21:31:37 +08:00
|
|
|
(long long)__pfn_to_phys(md->pfn), addr);
|
2006-09-27 22:38:34 +08:00
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
2007-04-21 17:21:28 +08:00
|
|
|
pgd = pgd_offset_k(addr);
|
|
|
|
|
end = addr + length;
|
|
|
|
|
do {
|
|
|
|
|
unsigned long next = pgd_addr_end(addr, end);
|
2006-09-27 22:38:34 +08:00
|
|
|
|
2010-11-22 00:27:49 +08:00
|
|
|
alloc_init_pud(pgd, addr, next, phys, type);
|
2006-09-27 22:38:34 +08:00
|
|
|
|
2007-04-21 17:21:28 +08:00
|
|
|
phys += next - addr;
|
|
|
|
|
addr = next;
|
|
|
|
|
} while (pgd++, addr != end);
|
2006-09-27 22:38:34 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Create the architecture specific mappings
|
|
|
|
|
*/
|
|
|
|
|
void __init iotable_init(struct map_desc *io_desc, int nr)
|
|
|
|
|
{
|
|
|
|
|
int i;
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < nr; i++)
|
|
|
|
|
create_mapping(io_desc + i);
|
|
|
|
|
}
|
|
|
|
|
|
2010-05-22 23:20:14 +08:00
|
|
|
static void * __initdata vmalloc_min = (void *)(VMALLOC_END - SZ_128M);
|
2008-10-01 02:31:44 +08:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* vmalloc=size forces the vmalloc area to be exactly 'size'
|
|
|
|
|
* bytes. This can be used to increase (or decrease) the vmalloc
|
|
|
|
|
* area - the default is 128m.
|
|
|
|
|
*/
|
2010-01-12 06:17:34 +08:00
|
|
|
static int __init early_vmalloc(char *arg)
|
2008-10-01 02:31:44 +08:00
|
|
|
{
|
2010-05-22 23:20:14 +08:00
|
|
|
unsigned long vmalloc_reserve = memparse(arg, NULL);
|
2008-10-01 02:31:44 +08:00
|
|
|
|
|
|
|
|
if (vmalloc_reserve < SZ_16M) {
|
|
|
|
|
vmalloc_reserve = SZ_16M;
|
|
|
|
|
printk(KERN_WARNING
|
|
|
|
|
"vmalloc area too small, limiting to %luMB\n",
|
|
|
|
|
vmalloc_reserve >> 20);
|
|
|
|
|
}
|
2008-09-19 22:43:06 +08:00
|
|
|
|
|
|
|
|
if (vmalloc_reserve > VMALLOC_END - (PAGE_OFFSET + SZ_32M)) {
|
|
|
|
|
vmalloc_reserve = VMALLOC_END - (PAGE_OFFSET + SZ_32M);
|
|
|
|
|
printk(KERN_WARNING
|
|
|
|
|
"vmalloc area is too big, limiting to %luMB\n",
|
|
|
|
|
vmalloc_reserve >> 20);
|
|
|
|
|
}
|
2010-05-22 23:20:14 +08:00
|
|
|
|
|
|
|
|
vmalloc_min = (void *)(VMALLOC_END - vmalloc_reserve);
|
2010-01-12 06:17:34 +08:00
|
|
|
return 0;
|
2008-10-01 02:31:44 +08:00
|
|
|
}
|
2010-01-12 06:17:34 +08:00
|
|
|
early_param("vmalloc", early_vmalloc);
|
2008-10-01 02:31:44 +08:00
|
|
|
|
2010-10-28 02:57:38 +08:00
|
|
|
static phys_addr_t lowmem_limit __initdata = 0;
|
|
|
|
|
|
2008-10-07 01:24:40 +08:00
|
|
|
static void __init sanity_check_meminfo(void)
|
[ARM] prevent crashing when too much RAM installed
This patch will truncate and/or ignore memory banks if their kernel
direct mappings would (partially) overlap with the vmalloc area or
the mappings between the vmalloc area and the address space top, to
prevent crashing during early boot if there happens to be more RAM
installed than we are expecting.
Since the start of the vmalloc area is not at a fixed address (but
the vmalloc end address is, via the per-platform VMALLOC_END define),
a default area of 128M is reserved for vmalloc mappings, which can
be shrunk or enlarged by passing an appropriate vmalloc= command line
option as it is done on x86.
On a board with a 3:1 user:kernel split, VMALLOC_END at 0xfe000000,
two 512M RAM banks and vmalloc=128M (the default), this patch gives:
Truncating RAM at 20000000-3fffffff to -35ffffff (vmalloc region overlap).
Memory: 512MB 352MB = 864MB total
On a board with a 3:1 user:kernel split, VMALLOC_END at 0xfe800000,
two 256M RAM banks and vmalloc=768M, this patch gives:
Truncating RAM at 00000000-0fffffff to -0e7fffff (vmalloc region overlap).
Ignoring RAM at 10000000-1fffffff (vmalloc region overlap).
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Riku Voipio <riku.voipio@iki.fi>
2008-08-05 07:56:13 +08:00
|
|
|
{
|
ARM: Fix broken highmem support
Currently, highmem is selectable, and you can request an increased
vmalloc area. However, none of this has any effect on the memory
layout since a patch in the highmem series was accidentally dropped.
Moreover, even if you did want highmem, all memory would still be
registered as lowmem, possibly resulting in overflow of the available
virtual mapping space.
The highmem boundary is determined by the highest allowed beginning
of the vmalloc area, which depends on its configurable minimum size
(see commit 60296c71f6c5063e3c1f1d2619ca0b60940162e7 for details on
this).
We should create mappings and initialize bootmem only for low memory,
while the zone allocator must still be told about highmem.
Currently, memory nodes which are completely located in high memory
are not supported. This is not a huge limitation since systems
relying on highmem support are unlikely to have discontiguous memory
with large holes.
[ A similar patch was meant to be merged before commit 5f0fbf9ecaf3
and be available in Linux v2.6.30, however some git rebase screw-up
of mine dropped the first commit of the series, and that goofage
escaped testing somehow as well. -- Nico ]
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
2009-08-15 19:36:00 +08:00
|
|
|
int i, j, highmem = 0;
|
[ARM] prevent crashing when too much RAM installed
This patch will truncate and/or ignore memory banks if their kernel
direct mappings would (partially) overlap with the vmalloc area or
the mappings between the vmalloc area and the address space top, to
prevent crashing during early boot if there happens to be more RAM
installed than we are expecting.
Since the start of the vmalloc area is not at a fixed address (but
the vmalloc end address is, via the per-platform VMALLOC_END define),
a default area of 128M is reserved for vmalloc mappings, which can
be shrunk or enlarged by passing an appropriate vmalloc= command line
option as it is done on x86.
On a board with a 3:1 user:kernel split, VMALLOC_END at 0xfe000000,
two 512M RAM banks and vmalloc=128M (the default), this patch gives:
Truncating RAM at 20000000-3fffffff to -35ffffff (vmalloc region overlap).
Memory: 512MB 352MB = 864MB total
On a board with a 3:1 user:kernel split, VMALLOC_END at 0xfe800000,
two 256M RAM banks and vmalloc=768M, this patch gives:
Truncating RAM at 00000000-0fffffff to -0e7fffff (vmalloc region overlap).
Ignoring RAM at 10000000-1fffffff (vmalloc region overlap).
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Riku Voipio <riku.voipio@iki.fi>
2008-08-05 07:56:13 +08:00
|
|
|
|
2010-10-28 02:57:38 +08:00
|
|
|
lowmem_limit = __pa(vmalloc_min - 1) + 1;
|
|
|
|
|
memblock_set_current_limit(lowmem_limit);
|
2010-07-09 23:27:52 +08:00
|
|
|
|
2008-10-07 01:24:40 +08:00
|
|
|
for (i = 0, j = 0; i < meminfo.nr_banks; i++) {
|
2008-09-02 23:44:21 +08:00
|
|
|
struct membank *bank = &meminfo.bank[j];
|
|
|
|
|
*bank = meminfo.bank[i];
|
[ARM] prevent crashing when too much RAM installed
This patch will truncate and/or ignore memory banks if their kernel
direct mappings would (partially) overlap with the vmalloc area or
the mappings between the vmalloc area and the address space top, to
prevent crashing during early boot if there happens to be more RAM
installed than we are expecting.
Since the start of the vmalloc area is not at a fixed address (but
the vmalloc end address is, via the per-platform VMALLOC_END define),
a default area of 128M is reserved for vmalloc mappings, which can
be shrunk or enlarged by passing an appropriate vmalloc= command line
option as it is done on x86.
On a board with a 3:1 user:kernel split, VMALLOC_END at 0xfe000000,
two 512M RAM banks and vmalloc=128M (the default), this patch gives:
Truncating RAM at 20000000-3fffffff to -35ffffff (vmalloc region overlap).
Memory: 512MB 352MB = 864MB total
On a board with a 3:1 user:kernel split, VMALLOC_END at 0xfe800000,
two 256M RAM banks and vmalloc=768M, this patch gives:
Truncating RAM at 00000000-0fffffff to -0e7fffff (vmalloc region overlap).
Ignoring RAM at 10000000-1fffffff (vmalloc region overlap).
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Riku Voipio <riku.voipio@iki.fi>
2008-08-05 07:56:13 +08:00
|
|
|
|
2008-09-02 23:44:21 +08:00
|
|
|
#ifdef CONFIG_HIGHMEM
|
2010-05-22 23:20:14 +08:00
|
|
|
if (__va(bank->start) > vmalloc_min ||
|
ARM: Fix broken highmem support
Currently, highmem is selectable, and you can request an increased
vmalloc area. However, none of this has any effect on the memory
layout since a patch in the highmem series was accidentally dropped.
Moreover, even if you did want highmem, all memory would still be
registered as lowmem, possibly resulting in overflow of the available
virtual mapping space.
The highmem boundary is determined by the highest allowed beginning
of the vmalloc area, which depends on its configurable minimum size
(see commit 60296c71f6c5063e3c1f1d2619ca0b60940162e7 for details on
this).
We should create mappings and initialize bootmem only for low memory,
while the zone allocator must still be told about highmem.
Currently, memory nodes which are completely located in high memory
are not supported. This is not a huge limitation since systems
relying on highmem support are unlikely to have discontiguous memory
with large holes.
[ A similar patch was meant to be merged before commit 5f0fbf9ecaf3
and be available in Linux v2.6.30, however some git rebase screw-up
of mine dropped the first commit of the series, and that goofage
escaped testing somehow as well. -- Nico ]
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
2009-08-15 19:36:00 +08:00
|
|
|
__va(bank->start) < (void *)PAGE_OFFSET)
|
|
|
|
|
highmem = 1;
|
|
|
|
|
|
|
|
|
|
bank->highmem = highmem;
|
|
|
|
|
|
2008-09-02 23:44:21 +08:00
|
|
|
/*
|
|
|
|
|
* Split those memory banks which are partially overlapping
|
|
|
|
|
* the vmalloc area greatly simplifying things later.
|
|
|
|
|
*/
|
2010-05-22 23:20:14 +08:00
|
|
|
if (__va(bank->start) < vmalloc_min &&
|
|
|
|
|
bank->size > vmalloc_min - __va(bank->start)) {
|
2008-09-02 23:44:21 +08:00
|
|
|
if (meminfo.nr_banks >= NR_BANKS) {
|
|
|
|
|
printk(KERN_CRIT "NR_BANKS too low, "
|
|
|
|
|
"ignoring high memory\n");
|
|
|
|
|
} else {
|
|
|
|
|
memmove(bank + 1, bank,
|
|
|
|
|
(meminfo.nr_banks - i) * sizeof(*bank));
|
|
|
|
|
meminfo.nr_banks++;
|
|
|
|
|
i++;
|
2010-05-22 23:20:14 +08:00
|
|
|
bank[1].size -= vmalloc_min - __va(bank->start);
|
|
|
|
|
bank[1].start = __pa(vmalloc_min - 1) + 1;
|
ARM: Fix broken highmem support
Currently, highmem is selectable, and you can request an increased
vmalloc area. However, none of this has any effect on the memory
layout since a patch in the highmem series was accidentally dropped.
Moreover, even if you did want highmem, all memory would still be
registered as lowmem, possibly resulting in overflow of the available
virtual mapping space.
The highmem boundary is determined by the highest allowed beginning
of the vmalloc area, which depends on its configurable minimum size
(see commit 60296c71f6c5063e3c1f1d2619ca0b60940162e7 for details on
this).
We should create mappings and initialize bootmem only for low memory,
while the zone allocator must still be told about highmem.
Currently, memory nodes which are completely located in high memory
are not supported. This is not a huge limitation since systems
relying on highmem support are unlikely to have discontiguous memory
with large holes.
[ A similar patch was meant to be merged before commit 5f0fbf9ecaf3
and be available in Linux v2.6.30, however some git rebase screw-up
of mine dropped the first commit of the series, and that goofage
escaped testing somehow as well. -- Nico ]
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
2009-08-15 19:36:00 +08:00
|
|
|
bank[1].highmem = highmem = 1;
|
2008-09-02 23:44:21 +08:00
|
|
|
j++;
|
|
|
|
|
}
|
2010-05-22 23:20:14 +08:00
|
|
|
bank->size = vmalloc_min - __va(bank->start);
|
2008-09-02 23:44:21 +08:00
|
|
|
}
|
|
|
|
|
#else
|
2009-09-28 00:40:42 +08:00
|
|
|
bank->highmem = highmem;
|
|
|
|
|
|
2008-09-02 23:44:21 +08:00
|
|
|
/*
|
|
|
|
|
* Check whether this memory bank would entirely overlap
|
|
|
|
|
* the vmalloc area.
|
|
|
|
|
*/
|
2010-05-22 23:20:14 +08:00
|
|
|
if (__va(bank->start) >= vmalloc_min ||
|
2009-03-29 02:18:05 +08:00
|
|
|
__va(bank->start) < (void *)PAGE_OFFSET) {
|
2011-02-20 19:47:41 +08:00
|
|
|
printk(KERN_NOTICE "Ignoring RAM at %.8llx-%.8llx "
|
2008-09-02 23:44:21 +08:00
|
|
|
"(vmalloc region overlap).\n",
|
2011-02-20 19:47:41 +08:00
|
|
|
(unsigned long long)bank->start,
|
|
|
|
|
(unsigned long long)bank->start + bank->size - 1);
|
2008-09-02 23:44:21 +08:00
|
|
|
continue;
|
|
|
|
|
}
|
[ARM] prevent crashing when too much RAM installed
This patch will truncate and/or ignore memory banks if their kernel
direct mappings would (partially) overlap with the vmalloc area or
the mappings between the vmalloc area and the address space top, to
prevent crashing during early boot if there happens to be more RAM
installed than we are expecting.
Since the start of the vmalloc area is not at a fixed address (but
the vmalloc end address is, via the per-platform VMALLOC_END define),
a default area of 128M is reserved for vmalloc mappings, which can
be shrunk or enlarged by passing an appropriate vmalloc= command line
option as it is done on x86.
On a board with a 3:1 user:kernel split, VMALLOC_END at 0xfe000000,
two 512M RAM banks and vmalloc=128M (the default), this patch gives:
Truncating RAM at 20000000-3fffffff to -35ffffff (vmalloc region overlap).
Memory: 512MB 352MB = 864MB total
On a board with a 3:1 user:kernel split, VMALLOC_END at 0xfe800000,
two 256M RAM banks and vmalloc=768M, this patch gives:
Truncating RAM at 00000000-0fffffff to -0e7fffff (vmalloc region overlap).
Ignoring RAM at 10000000-1fffffff (vmalloc region overlap).
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Riku Voipio <riku.voipio@iki.fi>
2008-08-05 07:56:13 +08:00
|
|
|
|
2008-09-02 23:44:21 +08:00
|
|
|
/*
|
|
|
|
|
* Check whether this memory bank would partially overlap
|
|
|
|
|
* the vmalloc area.
|
|
|
|
|
*/
|
2010-05-22 23:20:14 +08:00
|
|
|
if (__va(bank->start + bank->size) > vmalloc_min ||
|
2008-09-02 23:44:21 +08:00
|
|
|
__va(bank->start + bank->size) < __va(bank->start)) {
|
2010-05-22 23:20:14 +08:00
|
|
|
unsigned long newsize = vmalloc_min - __va(bank->start);
|
2011-02-20 19:47:41 +08:00
|
|
|
printk(KERN_NOTICE "Truncating RAM at %.8llx-%.8llx "
|
|
|
|
|
"to -%.8llx (vmalloc region overlap).\n",
|
|
|
|
|
(unsigned long long)bank->start,
|
|
|
|
|
(unsigned long long)bank->start + bank->size - 1,
|
|
|
|
|
(unsigned long long)bank->start + newsize - 1);
|
2008-09-02 23:44:21 +08:00
|
|
|
bank->size = newsize;
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
j++;
|
[ARM] prevent crashing when too much RAM installed
This patch will truncate and/or ignore memory banks if their kernel
direct mappings would (partially) overlap with the vmalloc area or
the mappings between the vmalloc area and the address space top, to
prevent crashing during early boot if there happens to be more RAM
installed than we are expecting.
Since the start of the vmalloc area is not at a fixed address (but
the vmalloc end address is, via the per-platform VMALLOC_END define),
a default area of 128M is reserved for vmalloc mappings, which can
be shrunk or enlarged by passing an appropriate vmalloc= command line
option as it is done on x86.
On a board with a 3:1 user:kernel split, VMALLOC_END at 0xfe000000,
two 512M RAM banks and vmalloc=128M (the default), this patch gives:
Truncating RAM at 20000000-3fffffff to -35ffffff (vmalloc region overlap).
Memory: 512MB 352MB = 864MB total
On a board with a 3:1 user:kernel split, VMALLOC_END at 0xfe800000,
two 256M RAM banks and vmalloc=768M, this patch gives:
Truncating RAM at 00000000-0fffffff to -0e7fffff (vmalloc region overlap).
Ignoring RAM at 10000000-1fffffff (vmalloc region overlap).
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Riku Voipio <riku.voipio@iki.fi>
2008-08-05 07:56:13 +08:00
|
|
|
}
|
2009-09-28 03:55:43 +08:00
|
|
|
#ifdef CONFIG_HIGHMEM
|
|
|
|
|
if (highmem) {
|
|
|
|
|
const char *reason = NULL;
|
|
|
|
|
|
|
|
|
|
if (cache_is_vipt_aliasing()) {
|
|
|
|
|
/*
|
|
|
|
|
* Interactions between kmap and other mappings
|
|
|
|
|
* make highmem support with aliasing VIPT caches
|
|
|
|
|
* rather difficult.
|
|
|
|
|
*/
|
|
|
|
|
reason = "with VIPT aliasing cache";
|
|
|
|
|
}
|
|
|
|
|
if (reason) {
|
|
|
|
|
printk(KERN_CRIT "HIGHMEM is not supported %s, ignoring high memory\n",
|
|
|
|
|
reason);
|
|
|
|
|
while (j > 0 && meminfo.bank[j - 1].highmem)
|
|
|
|
|
j--;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
#endif
|
2008-10-07 01:24:40 +08:00
|
|
|
meminfo.nr_banks = j;
|
[ARM] prevent crashing when too much RAM installed
This patch will truncate and/or ignore memory banks if their kernel
direct mappings would (partially) overlap with the vmalloc area or
the mappings between the vmalloc area and the address space top, to
prevent crashing during early boot if there happens to be more RAM
installed than we are expecting.
Since the start of the vmalloc area is not at a fixed address (but
the vmalloc end address is, via the per-platform VMALLOC_END define),
a default area of 128M is reserved for vmalloc mappings, which can
be shrunk or enlarged by passing an appropriate vmalloc= command line
option as it is done on x86.
On a board with a 3:1 user:kernel split, VMALLOC_END at 0xfe000000,
two 512M RAM banks and vmalloc=128M (the default), this patch gives:
Truncating RAM at 20000000-3fffffff to -35ffffff (vmalloc region overlap).
Memory: 512MB 352MB = 864MB total
On a board with a 3:1 user:kernel split, VMALLOC_END at 0xfe800000,
two 256M RAM banks and vmalloc=768M, this patch gives:
Truncating RAM at 00000000-0fffffff to -0e7fffff (vmalloc region overlap).
Ignoring RAM at 10000000-1fffffff (vmalloc region overlap).
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Riku Voipio <riku.voipio@iki.fi>
2008-08-05 07:56:13 +08:00
|
|
|
}
|
|
|
|
|
|
2008-10-07 01:24:40 +08:00
|
|
|
static inline void prepare_page_table(void)
|
2006-09-27 22:27:33 +08:00
|
|
|
{
|
|
|
|
|
unsigned long addr;
|
2010-10-28 02:57:38 +08:00
|
|
|
phys_addr_t end;
|
2006-09-27 22:27:33 +08:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Clear out all the mappings below the kernel image.
|
|
|
|
|
*/
|
2008-11-07 01:11:07 +08:00
|
|
|
for (addr = 0; addr < MODULES_VADDR; addr += PGDIR_SIZE)
|
2006-09-27 22:27:33 +08:00
|
|
|
pmd_clear(pmd_off_k(addr));
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_XIP_KERNEL
|
|
|
|
|
/* The XIP kernel is mapped in the module area -- skip over it */
|
2008-12-01 19:53:07 +08:00
|
|
|
addr = ((unsigned long)_etext + PGDIR_SIZE - 1) & PGDIR_MASK;
|
2006-09-27 22:27:33 +08:00
|
|
|
#endif
|
|
|
|
|
for ( ; addr < PAGE_OFFSET; addr += PGDIR_SIZE)
|
|
|
|
|
pmd_clear(pmd_off_k(addr));
|
|
|
|
|
|
2010-10-28 02:57:38 +08:00
|
|
|
/*
|
|
|
|
|
* Find the end of the first block of lowmem.
|
|
|
|
|
*/
|
|
|
|
|
end = memblock.memory.regions[0].base + memblock.memory.regions[0].size;
|
|
|
|
|
if (end >= lowmem_limit)
|
|
|
|
|
end = lowmem_limit;
|
|
|
|
|
|
2006-09-27 22:27:33 +08:00
|
|
|
/*
|
|
|
|
|
* Clear out all the kernel space mappings, except for the first
|
|
|
|
|
* memory bank, up to the end of the vmalloc region.
|
|
|
|
|
*/
|
2010-10-28 02:57:38 +08:00
|
|
|
for (addr = __phys_to_virt(end);
|
2006-09-27 22:27:33 +08:00
|
|
|
addr < VMALLOC_END; addr += PGDIR_SIZE)
|
|
|
|
|
pmd_clear(pmd_off_k(addr));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
2010-07-09 23:27:52 +08:00
|
|
|
* Reserve the special regions of memory
|
2006-09-27 22:27:33 +08:00
|
|
|
*/
|
2010-07-09 23:27:52 +08:00
|
|
|
void __init arm_mm_memblock_reserve(void)
|
2006-09-27 22:27:33 +08:00
|
|
|
{
|
|
|
|
|
/*
|
|
|
|
|
* Reserve the page tables. These are already in use,
|
|
|
|
|
* and can only be in node 0.
|
|
|
|
|
*/
|
2010-07-09 23:27:52 +08:00
|
|
|
memblock_reserve(__pa(swapper_pg_dir), PTRS_PER_PGD * sizeof(pgd_t));
|
2006-09-27 22:27:33 +08:00
|
|
|
|
|
|
|
|
#ifdef CONFIG_SA1111
|
|
|
|
|
/*
|
|
|
|
|
* Because of the SA1111 DMA bug, we want to preserve our
|
|
|
|
|
* precious DMA-able memory...
|
|
|
|
|
*/
|
2010-07-09 23:27:52 +08:00
|
|
|
memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET);
|
2006-09-27 22:27:33 +08:00
|
|
|
#endif
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Set up device the mappings. Since we clear out the page tables for all
|
|
|
|
|
* mappings above VMALLOC_END, we will remove any debug device mappings.
|
|
|
|
|
* This means you have to be careful how you debug this function, or any
|
|
|
|
|
* called function. This means you can't use any function or debugging
|
|
|
|
|
* method which may touch any device, otherwise the kernel _will_ crash.
|
|
|
|
|
*/
|
|
|
|
|
static void __init devicemaps_init(struct machine_desc *mdesc)
|
|
|
|
|
{
|
|
|
|
|
struct map_desc map;
|
|
|
|
|
unsigned long addr;
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Allocate the vector page early.
|
|
|
|
|
*/
|
2010-09-13 23:03:21 +08:00
|
|
|
vectors_page = early_alloc(PAGE_SIZE);
|
2006-09-27 22:27:33 +08:00
|
|
|
|
|
|
|
|
for (addr = VMALLOC_END; addr; addr += PGDIR_SIZE)
|
|
|
|
|
pmd_clear(pmd_off_k(addr));
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Map the kernel if it is XIP.
|
|
|
|
|
* It is always first in the modulearea.
|
|
|
|
|
*/
|
|
|
|
|
#ifdef CONFIG_XIP_KERNEL
|
|
|
|
|
map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK);
|
2008-11-07 01:11:07 +08:00
|
|
|
map.virtual = MODULES_VADDR;
|
2008-12-01 19:53:07 +08:00
|
|
|
map.length = ((unsigned long)_etext - map.virtual + ~SECTION_MASK) & SECTION_MASK;
|
2006-09-27 22:27:33 +08:00
|
|
|
map.type = MT_ROM;
|
|
|
|
|
create_mapping(&map);
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Map the cache flushing regions.
|
|
|
|
|
*/
|
|
|
|
|
#ifdef FLUSH_BASE
|
|
|
|
|
map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS);
|
|
|
|
|
map.virtual = FLUSH_BASE;
|
|
|
|
|
map.length = SZ_1M;
|
|
|
|
|
map.type = MT_CACHECLEAN;
|
|
|
|
|
create_mapping(&map);
|
|
|
|
|
#endif
|
|
|
|
|
#ifdef FLUSH_BASE_MINICACHE
|
|
|
|
|
map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M);
|
|
|
|
|
map.virtual = FLUSH_BASE_MINICACHE;
|
|
|
|
|
map.length = SZ_1M;
|
|
|
|
|
map.type = MT_MINICLEAN;
|
|
|
|
|
create_mapping(&map);
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Create a mapping for the machine vectors at the high-vectors
|
|
|
|
|
* location (0xffff0000). If we aren't using high-vectors, also
|
|
|
|
|
* create a mapping at the low-vectors virtual address.
|
|
|
|
|
*/
|
2010-09-13 23:03:21 +08:00
|
|
|
map.pfn = __phys_to_pfn(virt_to_phys(vectors_page));
|
2006-09-27 22:27:33 +08:00
|
|
|
map.virtual = 0xffff0000;
|
|
|
|
|
map.length = PAGE_SIZE;
|
|
|
|
|
map.type = MT_HIGH_VECTORS;
|
|
|
|
|
create_mapping(&map);
|
|
|
|
|
|
|
|
|
|
if (!vectors_high()) {
|
|
|
|
|
map.virtual = 0;
|
|
|
|
|
map.type = MT_LOW_VECTORS;
|
|
|
|
|
create_mapping(&map);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Ask the machine support to map in the statically mapped devices.
|
|
|
|
|
*/
|
|
|
|
|
if (mdesc->map_io)
|
|
|
|
|
mdesc->map_io();
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Finally flush the caches and tlb to ensure that we're in a
|
|
|
|
|
* consistent state wrt the writebuffer. This also ensures that
|
|
|
|
|
* any write-allocated cache lines in the vector page are written
|
|
|
|
|
* back. After this point, we can start to touch devices again.
|
|
|
|
|
*/
|
|
|
|
|
local_flush_tlb_all();
|
|
|
|
|
flush_cache_all();
|
|
|
|
|
}
|
|
|
|
|
|
2008-09-16 04:44:55 +08:00
|
|
|
static void __init kmap_init(void)
|
|
|
|
|
{
|
|
|
|
|
#ifdef CONFIG_HIGHMEM
|
2010-07-02 01:33:29 +08:00
|
|
|
pkmap_page_table = early_pte_alloc(pmd_off_k(PKMAP_BASE),
|
|
|
|
|
PKMAP_BASE, _PAGE_KERNEL_TABLE);
|
2008-09-16 04:44:55 +08:00
|
|
|
#endif
|
|
|
|
|
}
|
|
|
|
|
|
2010-03-26 02:56:05 +08:00
|
|
|
static void __init map_lowmem(void)
|
|
|
|
|
{
|
2010-10-28 02:57:38 +08:00
|
|
|
struct memblock_region *reg;
|
2010-03-26 02:56:05 +08:00
|
|
|
|
|
|
|
|
/* Map all the lowmem memory banks. */
|
2010-10-28 02:57:38 +08:00
|
|
|
for_each_memblock(memory, reg) {
|
|
|
|
|
phys_addr_t start = reg->base;
|
|
|
|
|
phys_addr_t end = start + reg->size;
|
|
|
|
|
struct map_desc map;
|
|
|
|
|
|
|
|
|
|
if (end > lowmem_limit)
|
|
|
|
|
end = lowmem_limit;
|
|
|
|
|
if (start >= end)
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
map.pfn = __phys_to_pfn(start);
|
|
|
|
|
map.virtual = __phys_to_virt(start);
|
|
|
|
|
map.length = end - start;
|
|
|
|
|
map.type = MT_MEMORY;
|
2010-03-26 02:56:05 +08:00
|
|
|
|
2010-10-28 02:57:38 +08:00
|
|
|
create_mapping(&map);
|
2010-03-26 02:56:05 +08:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2006-09-27 22:27:33 +08:00
|
|
|
/*
|
|
|
|
|
* paging_init() sets up the page tables, initialises the zone memory
|
|
|
|
|
* maps, and sets up the zero page, bad page and bad page tables.
|
|
|
|
|
*/
|
2008-10-07 01:24:40 +08:00
|
|
|
void __init paging_init(struct machine_desc *mdesc)
|
2006-09-27 22:27:33 +08:00
|
|
|
{
|
|
|
|
|
void *zero_page;
|
|
|
|
|
|
|
|
|
|
build_mem_type_table();
|
2008-10-07 01:24:40 +08:00
|
|
|
sanity_check_meminfo();
|
|
|
|
|
prepare_page_table();
|
2010-03-26 02:56:05 +08:00
|
|
|
map_lowmem();
|
2006-09-27 22:27:33 +08:00
|
|
|
devicemaps_init(mdesc);
|
2008-09-16 04:44:55 +08:00
|
|
|
kmap_init();
|
2006-09-27 22:27:33 +08:00
|
|
|
|
|
|
|
|
top_pmd = pmd_off_k(0xffff0000);
|
|
|
|
|
|
2010-03-26 01:02:59 +08:00
|
|
|
/* allocate the zero page. */
|
|
|
|
|
zero_page = early_alloc(PAGE_SIZE);
|
2010-07-09 23:27:52 +08:00
|
|
|
|
2010-05-23 02:47:18 +08:00
|
|
|
bootmem_init();
|
2010-07-09 23:27:52 +08:00
|
|
|
|
2006-09-27 22:27:33 +08:00
|
|
|
empty_zero_page = virt_to_page(zero_page);
|
2009-10-25 18:23:04 +08:00
|
|
|
__flush_dcache_page(NULL, empty_zero_page);
|
2006-09-27 22:27:33 +08:00
|
|
|
}
|