2005-04-17 06:20:36 +08:00
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/* spinlock.h: 64-bit Sparc spinlock support.
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*
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* Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
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*/
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#ifndef __SPARC64_SPINLOCK_H
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#define __SPARC64_SPINLOCK_H
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#include <linux/config.h>
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#include <linux/threads.h> /* For NR_CPUS */
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#ifndef __ASSEMBLY__
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/* To get debugging spinlocks which detect and catch
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* deadlock situations, set CONFIG_DEBUG_SPINLOCK
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* and rebuild your kernel.
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*/
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/* All of these locking primitives are expected to work properly
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* even in an RMO memory model, which currently is what the kernel
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* runs in.
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*
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* There is another issue. Because we play games to save cycles
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* in the non-contention case, we need to be extra careful about
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* branch targets into the "spinning" code. They live in their
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* own section, but the newer V9 branches have a shorter range
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* than the traditional 32-bit sparc branch variants. The rule
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* is that the branches that go into and out of the spinner sections
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* must be pre-V9 branches.
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*/
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#ifndef CONFIG_DEBUG_SPINLOCK
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2005-04-21 08:12:41 +08:00
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typedef struct {
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volatile unsigned char lock;
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#ifdef CONFIG_PREEMPT
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unsigned int break_lock;
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#endif
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} spinlock_t;
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#define SPIN_LOCK_UNLOCKED (spinlock_t) {0,}
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2005-04-17 06:20:36 +08:00
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2005-04-21 08:12:41 +08:00
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#define spin_lock_init(lp) do { *(lp)= SPIN_LOCK_UNLOCKED; } while(0)
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#define spin_is_locked(lp) ((lp)->lock != 0)
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2005-04-17 06:20:36 +08:00
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2005-04-21 08:12:41 +08:00
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#define spin_unlock_wait(lp) \
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2005-08-30 03:46:22 +08:00
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do { rmb(); \
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2005-04-25 12:04:02 +08:00
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} while((lp)->lock)
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2005-04-17 06:20:36 +08:00
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static inline void _raw_spin_lock(spinlock_t *lock)
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{
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unsigned long tmp;
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__asm__ __volatile__(
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"1: ldstub [%1], %0\n"
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[SPARC64]: Avoid membar instructions in delay slots.
In particular, avoid membar instructions in the delay
slot of a jmpl instruction.
UltraSPARC-I, II, IIi, and IIe have a bug, documented in
the UltraSPARC-IIi User's Manual, Appendix K, Erratum 51
The long and short of it is that if the IMU unit misses
on a branch or jmpl, and there is a store buffer synchronizing
membar in the delay slot, the chip can stop fetching instructions.
If interrupts are enabled or some other trap is enabled, the
chip will unwedge itself, but performance will suffer.
We already had a workaround for this bug in a few spots, but
it's better to have the entire tree sanitized for this rule.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-06-28 06:42:04 +08:00
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" membar #StoreLoad | #StoreStore\n"
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2005-04-17 06:20:36 +08:00
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" brnz,pn %0, 2f\n"
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[SPARC64]: Avoid membar instructions in delay slots.
In particular, avoid membar instructions in the delay
slot of a jmpl instruction.
UltraSPARC-I, II, IIi, and IIe have a bug, documented in
the UltraSPARC-IIi User's Manual, Appendix K, Erratum 51
The long and short of it is that if the IMU unit misses
on a branch or jmpl, and there is a store buffer synchronizing
membar in the delay slot, the chip can stop fetching instructions.
If interrupts are enabled or some other trap is enabled, the
chip will unwedge itself, but performance will suffer.
We already had a workaround for this bug in a few spots, but
it's better to have the entire tree sanitized for this rule.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-06-28 06:42:04 +08:00
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" nop\n"
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2005-04-17 06:20:36 +08:00
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" .subsection 2\n"
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"2: ldub [%1], %0\n"
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[SPARC64]: Avoid membar instructions in delay slots.
In particular, avoid membar instructions in the delay
slot of a jmpl instruction.
UltraSPARC-I, II, IIi, and IIe have a bug, documented in
the UltraSPARC-IIi User's Manual, Appendix K, Erratum 51
The long and short of it is that if the IMU unit misses
on a branch or jmpl, and there is a store buffer synchronizing
membar in the delay slot, the chip can stop fetching instructions.
If interrupts are enabled or some other trap is enabled, the
chip will unwedge itself, but performance will suffer.
We already had a workaround for this bug in a few spots, but
it's better to have the entire tree sanitized for this rule.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-06-28 06:42:04 +08:00
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" membar #LoadLoad\n"
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2005-04-17 06:20:36 +08:00
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" brnz,pt %0, 2b\n"
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[SPARC64]: Avoid membar instructions in delay slots.
In particular, avoid membar instructions in the delay
slot of a jmpl instruction.
UltraSPARC-I, II, IIi, and IIe have a bug, documented in
the UltraSPARC-IIi User's Manual, Appendix K, Erratum 51
The long and short of it is that if the IMU unit misses
on a branch or jmpl, and there is a store buffer synchronizing
membar in the delay slot, the chip can stop fetching instructions.
If interrupts are enabled or some other trap is enabled, the
chip will unwedge itself, but performance will suffer.
We already had a workaround for this bug in a few spots, but
it's better to have the entire tree sanitized for this rule.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-06-28 06:42:04 +08:00
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" nop\n"
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2005-04-17 06:20:36 +08:00
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" ba,a,pt %%xcc, 1b\n"
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" .previous"
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: "=&r" (tmp)
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: "r" (lock)
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: "memory");
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}
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static inline int _raw_spin_trylock(spinlock_t *lock)
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{
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unsigned long result;
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__asm__ __volatile__(
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" ldstub [%1], %0\n"
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" membar #StoreLoad | #StoreStore"
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: "=r" (result)
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: "r" (lock)
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: "memory");
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return (result == 0UL);
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}
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static inline void _raw_spin_unlock(spinlock_t *lock)
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{
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__asm__ __volatile__(
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" membar #StoreStore | #LoadStore\n"
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" stb %%g0, [%0]"
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: /* No outputs */
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: "r" (lock)
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: "memory");
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}
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static inline void _raw_spin_lock_flags(spinlock_t *lock, unsigned long flags)
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{
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unsigned long tmp1, tmp2;
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__asm__ __volatile__(
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"1: ldstub [%2], %0\n"
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" membar #StoreLoad | #StoreStore\n"
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[SPARC64]: Avoid membar instructions in delay slots.
In particular, avoid membar instructions in the delay
slot of a jmpl instruction.
UltraSPARC-I, II, IIi, and IIe have a bug, documented in
the UltraSPARC-IIi User's Manual, Appendix K, Erratum 51
The long and short of it is that if the IMU unit misses
on a branch or jmpl, and there is a store buffer synchronizing
membar in the delay slot, the chip can stop fetching instructions.
If interrupts are enabled or some other trap is enabled, the
chip will unwedge itself, but performance will suffer.
We already had a workaround for this bug in a few spots, but
it's better to have the entire tree sanitized for this rule.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-06-28 06:42:04 +08:00
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" brnz,pn %0, 2f\n"
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" nop\n"
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2005-04-17 06:20:36 +08:00
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" .subsection 2\n"
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"2: rdpr %%pil, %1\n"
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" wrpr %3, %%pil\n"
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"3: ldub [%2], %0\n"
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" membar #LoadLoad\n"
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[SPARC64]: Avoid membar instructions in delay slots.
In particular, avoid membar instructions in the delay
slot of a jmpl instruction.
UltraSPARC-I, II, IIi, and IIe have a bug, documented in
the UltraSPARC-IIi User's Manual, Appendix K, Erratum 51
The long and short of it is that if the IMU unit misses
on a branch or jmpl, and there is a store buffer synchronizing
membar in the delay slot, the chip can stop fetching instructions.
If interrupts are enabled or some other trap is enabled, the
chip will unwedge itself, but performance will suffer.
We already had a workaround for this bug in a few spots, but
it's better to have the entire tree sanitized for this rule.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-06-28 06:42:04 +08:00
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" brnz,pt %0, 3b\n"
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" nop\n"
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2005-04-17 06:20:36 +08:00
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" ba,pt %%xcc, 1b\n"
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[SPARC64]: Avoid membar instructions in delay slots.
In particular, avoid membar instructions in the delay
slot of a jmpl instruction.
UltraSPARC-I, II, IIi, and IIe have a bug, documented in
the UltraSPARC-IIi User's Manual, Appendix K, Erratum 51
The long and short of it is that if the IMU unit misses
on a branch or jmpl, and there is a store buffer synchronizing
membar in the delay slot, the chip can stop fetching instructions.
If interrupts are enabled or some other trap is enabled, the
chip will unwedge itself, but performance will suffer.
We already had a workaround for this bug in a few spots, but
it's better to have the entire tree sanitized for this rule.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-06-28 06:42:04 +08:00
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" wrpr %1, %%pil\n"
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2005-04-17 06:20:36 +08:00
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" .previous"
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: "=&r" (tmp1), "=&r" (tmp2)
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: "r"(lock), "r"(flags)
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: "memory");
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}
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#else /* !(CONFIG_DEBUG_SPINLOCK) */
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typedef struct {
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2005-04-21 08:12:41 +08:00
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volatile unsigned char lock;
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2005-04-17 06:20:36 +08:00
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unsigned int owner_pc, owner_cpu;
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2005-04-21 08:12:41 +08:00
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#ifdef CONFIG_PREEMPT
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unsigned int break_lock;
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#endif
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2005-04-17 06:20:36 +08:00
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} spinlock_t;
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#define SPIN_LOCK_UNLOCKED (spinlock_t) { 0, 0, 0xff }
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2005-04-21 08:12:41 +08:00
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#define spin_lock_init(lp) do { *(lp)= SPIN_LOCK_UNLOCKED; } while(0)
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#define spin_is_locked(__lock) ((__lock)->lock != 0)
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2005-04-17 06:20:36 +08:00
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#define spin_unlock_wait(__lock) \
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do { \
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2005-08-30 03:46:22 +08:00
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rmb(); \
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2005-04-21 08:12:41 +08:00
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} while((__lock)->lock)
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2005-04-17 06:20:36 +08:00
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2005-08-30 03:46:07 +08:00
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extern void _do_spin_lock(spinlock_t *lock, char *str, unsigned long caller);
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extern void _do_spin_unlock(spinlock_t *lock);
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extern int _do_spin_trylock(spinlock_t *lock, unsigned long caller);
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#define _raw_spin_trylock(lp) \
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_do_spin_trylock(lp, (unsigned long) __builtin_return_address(0))
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#define _raw_spin_lock(lock) \
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_do_spin_lock(lock, "spin_lock", \
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(unsigned long) __builtin_return_address(0))
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2005-04-17 06:20:36 +08:00
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#define _raw_spin_unlock(lock) _do_spin_unlock(lock)
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#define _raw_spin_lock_flags(lock, flags) _raw_spin_lock(lock)
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#endif /* CONFIG_DEBUG_SPINLOCK */
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/* Multi-reader locks, these are much saner than the 32-bit Sparc ones... */
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#ifndef CONFIG_DEBUG_SPINLOCK
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2005-04-21 08:12:41 +08:00
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typedef struct {
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volatile unsigned int lock;
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#ifdef CONFIG_PREEMPT
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unsigned int break_lock;
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#endif
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} rwlock_t;
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2005-04-25 12:04:02 +08:00
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#define RW_LOCK_UNLOCKED (rwlock_t) {0,}
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2005-04-17 06:20:36 +08:00
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#define rwlock_init(lp) do { *(lp) = RW_LOCK_UNLOCKED; } while(0)
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static void inline __read_lock(rwlock_t *lock)
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{
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unsigned long tmp1, tmp2;
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__asm__ __volatile__ (
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"1: ldsw [%2], %0\n"
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" brlz,pn %0, 2f\n"
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"4: add %0, 1, %1\n"
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" cas [%2], %0, %1\n"
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" cmp %0, %1\n"
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[SPARC64]: Avoid membar instructions in delay slots.
In particular, avoid membar instructions in the delay
slot of a jmpl instruction.
UltraSPARC-I, II, IIi, and IIe have a bug, documented in
the UltraSPARC-IIi User's Manual, Appendix K, Erratum 51
The long and short of it is that if the IMU unit misses
on a branch or jmpl, and there is a store buffer synchronizing
membar in the delay slot, the chip can stop fetching instructions.
If interrupts are enabled or some other trap is enabled, the
chip will unwedge itself, but performance will suffer.
We already had a workaround for this bug in a few spots, but
it's better to have the entire tree sanitized for this rule.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-06-28 06:42:04 +08:00
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" membar #StoreLoad | #StoreStore\n"
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2005-04-17 06:20:36 +08:00
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" bne,pn %%icc, 1b\n"
|
[SPARC64]: Avoid membar instructions in delay slots.
In particular, avoid membar instructions in the delay
slot of a jmpl instruction.
UltraSPARC-I, II, IIi, and IIe have a bug, documented in
the UltraSPARC-IIi User's Manual, Appendix K, Erratum 51
The long and short of it is that if the IMU unit misses
on a branch or jmpl, and there is a store buffer synchronizing
membar in the delay slot, the chip can stop fetching instructions.
If interrupts are enabled or some other trap is enabled, the
chip will unwedge itself, but performance will suffer.
We already had a workaround for this bug in a few spots, but
it's better to have the entire tree sanitized for this rule.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-06-28 06:42:04 +08:00
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" nop\n"
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2005-04-17 06:20:36 +08:00
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" .subsection 2\n"
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"2: ldsw [%2], %0\n"
|
[SPARC64]: Avoid membar instructions in delay slots.
In particular, avoid membar instructions in the delay
slot of a jmpl instruction.
UltraSPARC-I, II, IIi, and IIe have a bug, documented in
the UltraSPARC-IIi User's Manual, Appendix K, Erratum 51
The long and short of it is that if the IMU unit misses
on a branch or jmpl, and there is a store buffer synchronizing
membar in the delay slot, the chip can stop fetching instructions.
If interrupts are enabled or some other trap is enabled, the
chip will unwedge itself, but performance will suffer.
We already had a workaround for this bug in a few spots, but
it's better to have the entire tree sanitized for this rule.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-06-28 06:42:04 +08:00
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" membar #LoadLoad\n"
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2005-04-17 06:20:36 +08:00
|
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" brlz,pt %0, 2b\n"
|
[SPARC64]: Avoid membar instructions in delay slots.
In particular, avoid membar instructions in the delay
slot of a jmpl instruction.
UltraSPARC-I, II, IIi, and IIe have a bug, documented in
the UltraSPARC-IIi User's Manual, Appendix K, Erratum 51
The long and short of it is that if the IMU unit misses
on a branch or jmpl, and there is a store buffer synchronizing
membar in the delay slot, the chip can stop fetching instructions.
If interrupts are enabled or some other trap is enabled, the
chip will unwedge itself, but performance will suffer.
We already had a workaround for this bug in a few spots, but
it's better to have the entire tree sanitized for this rule.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-06-28 06:42:04 +08:00
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" nop\n"
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2005-04-17 06:20:36 +08:00
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" ba,a,pt %%xcc, 4b\n"
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" .previous"
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: "=&r" (tmp1), "=&r" (tmp2)
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: "r" (lock)
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: "memory");
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}
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static void inline __read_unlock(rwlock_t *lock)
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{
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unsigned long tmp1, tmp2;
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__asm__ __volatile__(
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" membar #StoreLoad | #LoadLoad\n"
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"1: lduw [%2], %0\n"
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" sub %0, 1, %1\n"
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" cas [%2], %0, %1\n"
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" cmp %0, %1\n"
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" bne,pn %%xcc, 1b\n"
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" nop"
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: "=&r" (tmp1), "=&r" (tmp2)
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: "r" (lock)
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: "memory");
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}
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static void inline __write_lock(rwlock_t *lock)
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{
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unsigned long mask, tmp1, tmp2;
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mask = 0x80000000UL;
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|
|
|
|
__asm__ __volatile__(
|
|
|
|
|
"1: lduw [%2], %0\n"
|
|
|
|
|
" brnz,pn %0, 2f\n"
|
|
|
|
|
"4: or %0, %3, %1\n"
|
|
|
|
|
" cas [%2], %0, %1\n"
|
|
|
|
|
" cmp %0, %1\n"
|
[SPARC64]: Avoid membar instructions in delay slots.
In particular, avoid membar instructions in the delay
slot of a jmpl instruction.
UltraSPARC-I, II, IIi, and IIe have a bug, documented in
the UltraSPARC-IIi User's Manual, Appendix K, Erratum 51
The long and short of it is that if the IMU unit misses
on a branch or jmpl, and there is a store buffer synchronizing
membar in the delay slot, the chip can stop fetching instructions.
If interrupts are enabled or some other trap is enabled, the
chip will unwedge itself, but performance will suffer.
We already had a workaround for this bug in a few spots, but
it's better to have the entire tree sanitized for this rule.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-06-28 06:42:04 +08:00
|
|
|
" membar #StoreLoad | #StoreStore\n"
|
2005-04-17 06:20:36 +08:00
|
|
|
" bne,pn %%icc, 1b\n"
|
[SPARC64]: Avoid membar instructions in delay slots.
In particular, avoid membar instructions in the delay
slot of a jmpl instruction.
UltraSPARC-I, II, IIi, and IIe have a bug, documented in
the UltraSPARC-IIi User's Manual, Appendix K, Erratum 51
The long and short of it is that if the IMU unit misses
on a branch or jmpl, and there is a store buffer synchronizing
membar in the delay slot, the chip can stop fetching instructions.
If interrupts are enabled or some other trap is enabled, the
chip will unwedge itself, but performance will suffer.
We already had a workaround for this bug in a few spots, but
it's better to have the entire tree sanitized for this rule.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-06-28 06:42:04 +08:00
|
|
|
" nop\n"
|
2005-04-17 06:20:36 +08:00
|
|
|
" .subsection 2\n"
|
|
|
|
|
"2: lduw [%2], %0\n"
|
[SPARC64]: Avoid membar instructions in delay slots.
In particular, avoid membar instructions in the delay
slot of a jmpl instruction.
UltraSPARC-I, II, IIi, and IIe have a bug, documented in
the UltraSPARC-IIi User's Manual, Appendix K, Erratum 51
The long and short of it is that if the IMU unit misses
on a branch or jmpl, and there is a store buffer synchronizing
membar in the delay slot, the chip can stop fetching instructions.
If interrupts are enabled or some other trap is enabled, the
chip will unwedge itself, but performance will suffer.
We already had a workaround for this bug in a few spots, but
it's better to have the entire tree sanitized for this rule.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-06-28 06:42:04 +08:00
|
|
|
" membar #LoadLoad\n"
|
2005-04-17 06:20:36 +08:00
|
|
|
" brnz,pt %0, 2b\n"
|
[SPARC64]: Avoid membar instructions in delay slots.
In particular, avoid membar instructions in the delay
slot of a jmpl instruction.
UltraSPARC-I, II, IIi, and IIe have a bug, documented in
the UltraSPARC-IIi User's Manual, Appendix K, Erratum 51
The long and short of it is that if the IMU unit misses
on a branch or jmpl, and there is a store buffer synchronizing
membar in the delay slot, the chip can stop fetching instructions.
If interrupts are enabled or some other trap is enabled, the
chip will unwedge itself, but performance will suffer.
We already had a workaround for this bug in a few spots, but
it's better to have the entire tree sanitized for this rule.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-06-28 06:42:04 +08:00
|
|
|
" nop\n"
|
2005-04-17 06:20:36 +08:00
|
|
|
" ba,a,pt %%xcc, 4b\n"
|
|
|
|
|
" .previous"
|
|
|
|
|
: "=&r" (tmp1), "=&r" (tmp2)
|
|
|
|
|
: "r" (lock), "r" (mask)
|
|
|
|
|
: "memory");
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void inline __write_unlock(rwlock_t *lock)
|
|
|
|
|
{
|
|
|
|
|
__asm__ __volatile__(
|
|
|
|
|
" membar #LoadStore | #StoreStore\n"
|
|
|
|
|
" stw %%g0, [%0]"
|
|
|
|
|
: /* no outputs */
|
|
|
|
|
: "r" (lock)
|
|
|
|
|
: "memory");
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int inline __write_trylock(rwlock_t *lock)
|
|
|
|
|
{
|
|
|
|
|
unsigned long mask, tmp1, tmp2, result;
|
|
|
|
|
|
|
|
|
|
mask = 0x80000000UL;
|
|
|
|
|
|
|
|
|
|
__asm__ __volatile__(
|
|
|
|
|
" mov 0, %2\n"
|
|
|
|
|
"1: lduw [%3], %0\n"
|
|
|
|
|
" brnz,pn %0, 2f\n"
|
|
|
|
|
" or %0, %4, %1\n"
|
|
|
|
|
" cas [%3], %0, %1\n"
|
|
|
|
|
" cmp %0, %1\n"
|
[SPARC64]: Avoid membar instructions in delay slots.
In particular, avoid membar instructions in the delay
slot of a jmpl instruction.
UltraSPARC-I, II, IIi, and IIe have a bug, documented in
the UltraSPARC-IIi User's Manual, Appendix K, Erratum 51
The long and short of it is that if the IMU unit misses
on a branch or jmpl, and there is a store buffer synchronizing
membar in the delay slot, the chip can stop fetching instructions.
If interrupts are enabled or some other trap is enabled, the
chip will unwedge itself, but performance will suffer.
We already had a workaround for this bug in a few spots, but
it's better to have the entire tree sanitized for this rule.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-06-28 06:42:04 +08:00
|
|
|
" membar #StoreLoad | #StoreStore\n"
|
2005-04-17 06:20:36 +08:00
|
|
|
" bne,pn %%icc, 1b\n"
|
[SPARC64]: Avoid membar instructions in delay slots.
In particular, avoid membar instructions in the delay
slot of a jmpl instruction.
UltraSPARC-I, II, IIi, and IIe have a bug, documented in
the UltraSPARC-IIi User's Manual, Appendix K, Erratum 51
The long and short of it is that if the IMU unit misses
on a branch or jmpl, and there is a store buffer synchronizing
membar in the delay slot, the chip can stop fetching instructions.
If interrupts are enabled or some other trap is enabled, the
chip will unwedge itself, but performance will suffer.
We already had a workaround for this bug in a few spots, but
it's better to have the entire tree sanitized for this rule.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-06-28 06:42:04 +08:00
|
|
|
" nop\n"
|
2005-04-17 06:20:36 +08:00
|
|
|
" mov 1, %2\n"
|
|
|
|
|
"2:"
|
|
|
|
|
: "=&r" (tmp1), "=&r" (tmp2), "=&r" (result)
|
|
|
|
|
: "r" (lock), "r" (mask)
|
|
|
|
|
: "memory");
|
|
|
|
|
|
|
|
|
|
return result;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#define _raw_read_lock(p) __read_lock(p)
|
|
|
|
|
#define _raw_read_unlock(p) __read_unlock(p)
|
|
|
|
|
#define _raw_write_lock(p) __write_lock(p)
|
|
|
|
|
#define _raw_write_unlock(p) __write_unlock(p)
|
|
|
|
|
#define _raw_write_trylock(p) __write_trylock(p)
|
|
|
|
|
|
|
|
|
|
#else /* !(CONFIG_DEBUG_SPINLOCK) */
|
|
|
|
|
|
|
|
|
|
typedef struct {
|
2005-04-21 08:12:41 +08:00
|
|
|
volatile unsigned long lock;
|
2005-04-17 06:20:36 +08:00
|
|
|
unsigned int writer_pc, writer_cpu;
|
|
|
|
|
unsigned int reader_pc[NR_CPUS];
|
2005-04-21 08:12:41 +08:00
|
|
|
#ifdef CONFIG_PREEMPT
|
|
|
|
|
unsigned int break_lock;
|
|
|
|
|
#endif
|
2005-04-17 06:20:36 +08:00
|
|
|
} rwlock_t;
|
|
|
|
|
#define RW_LOCK_UNLOCKED (rwlock_t) { 0, 0, 0xff, { } }
|
|
|
|
|
#define rwlock_init(lp) do { *(lp) = RW_LOCK_UNLOCKED; } while(0)
|
|
|
|
|
|
2005-08-30 03:46:07 +08:00
|
|
|
extern void _do_read_lock(rwlock_t *rw, char *str, unsigned long caller);
|
|
|
|
|
extern void _do_read_unlock(rwlock_t *rw, char *str, unsigned long caller);
|
|
|
|
|
extern void _do_write_lock(rwlock_t *rw, char *str, unsigned long caller);
|
|
|
|
|
extern void _do_write_unlock(rwlock_t *rw, unsigned long caller);
|
|
|
|
|
extern int _do_write_trylock(rwlock_t *rw, char *str, unsigned long caller);
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
|
#define _raw_read_lock(lock) \
|
|
|
|
|
do { unsigned long flags; \
|
|
|
|
|
local_irq_save(flags); \
|
2005-08-30 03:46:07 +08:00
|
|
|
_do_read_lock(lock, "read_lock", \
|
|
|
|
|
(unsigned long) __builtin_return_address(0)); \
|
2005-04-17 06:20:36 +08:00
|
|
|
local_irq_restore(flags); \
|
|
|
|
|
} while(0)
|
|
|
|
|
|
|
|
|
|
#define _raw_read_unlock(lock) \
|
|
|
|
|
do { unsigned long flags; \
|
|
|
|
|
local_irq_save(flags); \
|
2005-08-30 03:46:07 +08:00
|
|
|
_do_read_unlock(lock, "read_unlock", \
|
|
|
|
|
(unsigned long) __builtin_return_address(0)); \
|
2005-04-17 06:20:36 +08:00
|
|
|
local_irq_restore(flags); \
|
|
|
|
|
} while(0)
|
|
|
|
|
|
|
|
|
|
#define _raw_write_lock(lock) \
|
|
|
|
|
do { unsigned long flags; \
|
|
|
|
|
local_irq_save(flags); \
|
2005-08-30 03:46:07 +08:00
|
|
|
_do_write_lock(lock, "write_lock", \
|
|
|
|
|
(unsigned long) __builtin_return_address(0)); \
|
2005-04-17 06:20:36 +08:00
|
|
|
local_irq_restore(flags); \
|
|
|
|
|
} while(0)
|
|
|
|
|
|
|
|
|
|
#define _raw_write_unlock(lock) \
|
|
|
|
|
do { unsigned long flags; \
|
|
|
|
|
local_irq_save(flags); \
|
2005-08-30 03:46:07 +08:00
|
|
|
_do_write_unlock(lock, \
|
|
|
|
|
(unsigned long) __builtin_return_address(0)); \
|
2005-04-17 06:20:36 +08:00
|
|
|
local_irq_restore(flags); \
|
|
|
|
|
} while(0)
|
|
|
|
|
|
|
|
|
|
#define _raw_write_trylock(lock) \
|
|
|
|
|
({ unsigned long flags; \
|
|
|
|
|
int val; \
|
|
|
|
|
local_irq_save(flags); \
|
2005-08-30 03:46:07 +08:00
|
|
|
val = _do_write_trylock(lock, "write_trylock", \
|
|
|
|
|
(unsigned long) __builtin_return_address(0)); \
|
2005-04-17 06:20:36 +08:00
|
|
|
local_irq_restore(flags); \
|
|
|
|
|
val; \
|
|
|
|
|
})
|
|
|
|
|
|
|
|
|
|
#endif /* CONFIG_DEBUG_SPINLOCK */
|
|
|
|
|
|
|
|
|
|
#define _raw_read_trylock(lock) generic_raw_read_trylock(lock)
|
2005-04-21 08:12:41 +08:00
|
|
|
#define read_can_lock(rw) (!((rw)->lock & 0x80000000UL))
|
|
|
|
|
#define write_can_lock(rw) (!(rw)->lock)
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
|
#endif /* !(__ASSEMBLY__) */
|
|
|
|
|
|
|
|
|
|
#endif /* !(__SPARC64_SPINLOCK_H) */
|
