2005-04-17 06:20:36 +08:00
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/************************************************************************/
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/* */
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/* Title : RIO Host Card Hardware Definitions */
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/* */
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/* Author : N.P.Vassallo */
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/* */
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/* Creation : 26th April 1999 */
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/* */
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/* Version : 1.0.0 */
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/* */
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/* Copyright : (c) Specialix International Ltd. 1999 *
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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* */
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/* Description : Prototypes, structures and definitions */
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/* describing the RIO board hardware */
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/* */
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/************************************************************************/
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/* History...
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1.0.0 26/04/99 NPV Creation.
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*/
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2006-01-12 04:17:49 +08:00
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#ifndef _rioboard_h /* If RIOBOARD.H not already defined */
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2005-04-17 06:20:36 +08:00
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#define _rioboard_h 1
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/*****************************************************************************
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*********************** ***********************
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*********************** Hardware Control Registers ***********************
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*********************** ***********************
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*****************************************************************************/
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/* Hardware Registers... */
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2006-01-12 04:17:49 +08:00
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#define RIO_REG_BASE 0x7C00 /* Base of control registers */
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2005-04-17 06:20:36 +08:00
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#define RIO_CONFIG RIO_REG_BASE + 0x0000 /* WRITE: Configuration Register */
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#define RIO_INTSET RIO_REG_BASE + 0x0080 /* WRITE: Interrupt Set */
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#define RIO_RESET RIO_REG_BASE + 0x0100 /* WRITE: Host Reset */
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#define RIO_INTRESET RIO_REG_BASE + 0x0180 /* WRITE: Interrupt Reset */
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#define RIO_VPD_ROM RIO_REG_BASE + 0x0000 /* READ: Vital Product Data ROM */
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#define RIO_INTSTAT RIO_REG_BASE + 0x0080 /* READ: Interrupt Status (Jet boards only) */
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#define RIO_RESETSTAT RIO_REG_BASE + 0x0100 /* READ: Reset Status (Jet boards only) */
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/* RIO_VPD_ROM definitions... */
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2006-01-12 04:17:49 +08:00
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#define VPD_SLX_ID1 0x00 /* READ: Specialix Identifier #1 */
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#define VPD_SLX_ID2 0x01 /* READ: Specialix Identifier #2 */
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#define VPD_HW_REV 0x02 /* READ: Hardware Revision */
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#define VPD_HW_ASSEM 0x03 /* READ: Hardware Assembly Level */
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#define VPD_UNIQUEID4 0x04 /* READ: Unique Identifier #4 */
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#define VPD_UNIQUEID3 0x05 /* READ: Unique Identifier #3 */
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#define VPD_UNIQUEID2 0x06 /* READ: Unique Identifier #2 */
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#define VPD_UNIQUEID1 0x07 /* READ: Unique Identifier #1 */
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#define VPD_MANU_YEAR 0x08 /* READ: Year Of Manufacture (0 = 1970) */
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#define VPD_MANU_WEEK 0x09 /* READ: Week Of Manufacture (0 = week 1 Jan) */
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#define VPD_HWFEATURE1 0x0A /* READ: Hardware Feature Byte 1 */
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#define VPD_HWFEATURE2 0x0B /* READ: Hardware Feature Byte 2 */
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#define VPD_HWFEATURE3 0x0C /* READ: Hardware Feature Byte 3 */
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#define VPD_HWFEATURE4 0x0D /* READ: Hardware Feature Byte 4 */
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#define VPD_HWFEATURE5 0x0E /* READ: Hardware Feature Byte 5 */
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#define VPD_OEMID 0x0F /* READ: OEM Identifier */
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#define VPD_IDENT 0x10 /* READ: Identifier string (16 bytes) */
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#define VPD_IDENT_LEN 0x10
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/* VPD ROM Definitions... */
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#define SLX_ID1 0x4D
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#define SLX_ID2 0x98
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2006-01-12 04:17:49 +08:00
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#define PRODUCT_ID(a) ((a>>4)&0xF) /* Use to obtain Product ID from VPD_UNIQUEID1 */
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2005-04-17 06:20:36 +08:00
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#define ID_SX_ISA 0x2
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#define ID_RIO_EISA 0x3
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#define ID_SX_PCI 0x5
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#define ID_SX_EISA 0x7
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#define ID_RIO_RTA16 0x9
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#define ID_RIO_ISA 0xA
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#define ID_RIO_MCA 0xB
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#define ID_RIO_SBUS 0xC
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#define ID_RIO_PCI 0xD
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#define ID_RIO_RTA8 0xE
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/* Transputer bootstrap definitions... */
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#define BOOTLOADADDR (0x8000 - 6)
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#define BOOTINDICATE (0x8000 - 2)
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/* Firmware load position... */
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2006-01-12 04:17:49 +08:00
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#define FIRMWARELOADADDR 0x7C00 /* Firmware is loaded _before_ this address */
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2005-04-17 06:20:36 +08:00
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/*****************************************************************************
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***************************** *****************************
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***************************** RIO (Rev1) ISA *****************************
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***************************** *****************************
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*****************************************************************************/
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/* Control Register Definitions... */
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#define RIO_ISA_IDENT "JBJGPGGHINSMJPJR"
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2006-01-12 04:17:49 +08:00
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#define RIO_ISA_CFG_BOOTRAM 0x01 /* Boot from RAM, else Link */
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#define RIO_ISA_CFG_BUSENABLE 0x02 /* Enable processor bus */
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#define RIO_ISA_CFG_IRQMASK 0x30 /* Interrupt mask */
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#define RIO_ISA_CFG_IRQ12 0x10 /* Interrupt Level 12 */
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#define RIO_ISA_CFG_IRQ11 0x20 /* Interrupt Level 11 */
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#define RIO_ISA_CFG_IRQ9 0x30 /* Interrupt Level 9 */
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#define RIO_ISA_CFG_LINK20 0x40 /* 20Mbps link, else 10Mbps */
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#define RIO_ISA_CFG_WAITSTATE0 0x80 /* 0 waitstates, else 1 */
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2005-04-17 06:20:36 +08:00
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/*****************************************************************************
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***************************** *****************************
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***************************** RIO (Rev2) ISA *****************************
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***************************** *****************************
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*****************************************************************************/
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/* Control Register Definitions... */
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#define RIO_ISA2_IDENT "JBJGPGGHINSMJPJR"
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2006-01-12 04:17:49 +08:00
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#define RIO_ISA2_CFG_BOOTRAM 0x01 /* Boot from RAM, else Link */
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#define RIO_ISA2_CFG_BUSENABLE 0x02 /* Enable processor bus */
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#define RIO_ISA2_CFG_INTENABLE 0x04 /* Interrupt enable, else disable */
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#define RIO_ISA2_CFG_16BIT 0x08 /* 16bit mode, else 8bit */
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#define RIO_ISA2_CFG_IRQMASK 0x30 /* Interrupt mask */
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#define RIO_ISA2_CFG_IRQ15 0x00 /* Interrupt Level 15 */
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#define RIO_ISA2_CFG_IRQ12 0x10 /* Interrupt Level 12 */
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#define RIO_ISA2_CFG_IRQ11 0x20 /* Interrupt Level 11 */
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#define RIO_ISA2_CFG_IRQ9 0x30 /* Interrupt Level 9 */
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#define RIO_ISA2_CFG_LINK20 0x40 /* 20Mbps link, else 10Mbps */
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#define RIO_ISA2_CFG_WAITSTATE0 0x80 /* 0 waitstates, else 1 */
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2005-04-17 06:20:36 +08:00
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/*****************************************************************************
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***************************** ******************************
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***************************** RIO (Jet) ISA ******************************
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***************************** ******************************
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*****************************************************************************/
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/* Control Register Definitions... */
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#define RIO_ISA3_IDENT "JET HOST BY KEV#"
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2006-01-12 04:17:49 +08:00
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#define RIO_ISA3_CFG_BUSENABLE 0x02 /* Enable processor bus */
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#define RIO_ISA3_CFG_INTENABLE 0x04 /* Interrupt enable, else disable */
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#define RIO_ISA32_CFG_IRQMASK 0xF30 /* Interrupt mask */
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#define RIO_ISA3_CFG_IRQ15 0xF0 /* Interrupt Level 15 */
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#define RIO_ISA3_CFG_IRQ12 0xC0 /* Interrupt Level 12 */
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#define RIO_ISA3_CFG_IRQ11 0xB0 /* Interrupt Level 11 */
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#define RIO_ISA3_CFG_IRQ10 0xA0 /* Interrupt Level 10 */
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#define RIO_ISA3_CFG_IRQ9 0x90 /* Interrupt Level 9 */
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2005-04-17 06:20:36 +08:00
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/*****************************************************************************
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********************************* ********************************
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********************************* RIO MCA ********************************
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********************************* ********************************
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*****************************************************************************/
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/* Control Register Definitions... */
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#define RIO_MCA_IDENT "JBJGPGGHINSMJPJR"
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2006-01-12 04:17:49 +08:00
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#define RIO_MCA_CFG_BOOTRAM 0x01 /* Boot from RAM, else Link */
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#define RIO_MCA_CFG_BUSENABLE 0x02 /* Enable processor bus */
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#define RIO_MCA_CFG_LINK20 0x40 /* 20Mbps link, else 10Mbps */
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2005-04-17 06:20:36 +08:00
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/*****************************************************************************
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******************************** ********************************
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******************************** RIO EISA ********************************
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******************************** ********************************
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*****************************************************************************/
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/* EISA Configuration Space Definitions... */
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#define EISA_PRODUCT_ID1 0xC80
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#define EISA_PRODUCT_ID2 0xC81
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#define EISA_PRODUCT_NUMBER 0xC82
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#define EISA_REVISION_NUMBER 0xC83
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#define EISA_CARD_ENABLE 0xC84
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2006-01-12 04:17:49 +08:00
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#define EISA_VPD_UNIQUEID4 0xC88 /* READ: Unique Identifier #4 */
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#define EISA_VPD_UNIQUEID3 0xC8A /* READ: Unique Identifier #3 */
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#define EISA_VPD_UNIQUEID2 0xC90 /* READ: Unique Identifier #2 */
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#define EISA_VPD_UNIQUEID1 0xC92 /* READ: Unique Identifier #1 */
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#define EISA_VPD_MANU_YEAR 0xC98 /* READ: Year Of Manufacture (0 = 1970) */
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#define EISA_VPD_MANU_WEEK 0xC9A /* READ: Week Of Manufacture (0 = week 1 Jan) */
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2005-04-17 06:20:36 +08:00
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#define EISA_MEM_ADDR_23_16 0xC00
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#define EISA_MEM_ADDR_31_24 0xC01
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2006-01-12 04:17:49 +08:00
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#define EISA_RIO_CONFIG 0xC02 /* WRITE: Configuration Register */
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#define EISA_RIO_INTSET 0xC03 /* WRITE: Interrupt Set */
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#define EISA_RIO_INTRESET 0xC03 /* READ: Interrupt Reset */
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2005-04-17 06:20:36 +08:00
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/* Control Register Definitions... */
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2006-01-12 04:17:49 +08:00
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#define RIO_EISA_CFG_BOOTRAM 0x01 /* Boot from RAM, else Link */
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#define RIO_EISA_CFG_LINK20 0x02 /* 20Mbps link, else 10Mbps */
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#define RIO_EISA_CFG_BUSENABLE 0x04 /* Enable processor bus */
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#define RIO_EISA_CFG_PROCRUN 0x08 /* Processor running, else reset */
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#define RIO_EISA_CFG_IRQMASK 0xF0 /* Interrupt mask */
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#define RIO_EISA_CFG_IRQ15 0xF0 /* Interrupt Level 15 */
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#define RIO_EISA_CFG_IRQ14 0xE0 /* Interrupt Level 14 */
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#define RIO_EISA_CFG_IRQ12 0xC0 /* Interrupt Level 12 */
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#define RIO_EISA_CFG_IRQ11 0xB0 /* Interrupt Level 11 */
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#define RIO_EISA_CFG_IRQ10 0xA0 /* Interrupt Level 10 */
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#define RIO_EISA_CFG_IRQ9 0x90 /* Interrupt Level 9 */
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#define RIO_EISA_CFG_IRQ7 0x70 /* Interrupt Level 7 */
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#define RIO_EISA_CFG_IRQ6 0x60 /* Interrupt Level 6 */
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#define RIO_EISA_CFG_IRQ5 0x50 /* Interrupt Level 5 */
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#define RIO_EISA_CFG_IRQ4 0x40 /* Interrupt Level 4 */
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#define RIO_EISA_CFG_IRQ3 0x30 /* Interrupt Level 3 */
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2005-04-17 06:20:36 +08:00
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/*****************************************************************************
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******************************** ********************************
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******************************** RIO SBus ********************************
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******************************** ********************************
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*****************************************************************************/
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/* Control Register Definitions... */
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#define RIO_SBUS_IDENT "JBPGK#\0\0\0\0\0\0\0\0\0\0"
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2006-01-12 04:17:49 +08:00
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#define RIO_SBUS_CFG_BOOTRAM 0x01 /* Boot from RAM, else Link */
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#define RIO_SBUS_CFG_BUSENABLE 0x02 /* Enable processor bus */
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#define RIO_SBUS_CFG_INTENABLE 0x04 /* Interrupt enable, else disable */
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#define RIO_SBUS_CFG_IRQMASK 0x38 /* Interrupt mask */
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#define RIO_SBUS_CFG_IRQNONE 0x00 /* No Interrupt */
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#define RIO_SBUS_CFG_IRQ7 0x38 /* Interrupt Level 7 */
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#define RIO_SBUS_CFG_IRQ6 0x30 /* Interrupt Level 6 */
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#define RIO_SBUS_CFG_IRQ5 0x28 /* Interrupt Level 5 */
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#define RIO_SBUS_CFG_IRQ4 0x20 /* Interrupt Level 4 */
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#define RIO_SBUS_CFG_IRQ3 0x18 /* Interrupt Level 3 */
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#define RIO_SBUS_CFG_IRQ2 0x10 /* Interrupt Level 2 */
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#define RIO_SBUS_CFG_IRQ1 0x08 /* Interrupt Level 1 */
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#define RIO_SBUS_CFG_LINK20 0x40 /* 20Mbps link, else 10Mbps */
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#define RIO_SBUS_CFG_PROC25 0x80 /* 25Mhz processor clock, else 20Mhz */
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2005-04-17 06:20:36 +08:00
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/*****************************************************************************
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********************************* ********************************
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********************************* RIO PCI ********************************
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********************************* ********************************
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*****************************************************************************/
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/* Control Register Definitions... */
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#define RIO_PCI_IDENT "ECDDPGJGJHJRGSK#"
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2006-01-12 04:17:49 +08:00
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#define RIO_PCI_CFG_BOOTRAM 0x01 /* Boot from RAM, else Link */
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#define RIO_PCI_CFG_BUSENABLE 0x02 /* Enable processor bus */
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#define RIO_PCI_CFG_INTENABLE 0x04 /* Interrupt enable, else disable */
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#define RIO_PCI_CFG_LINK20 0x40 /* 20Mbps link, else 10Mbps */
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#define RIO_PCI_CFG_PROC25 0x80 /* 25Mhz processor clock, else 20Mhz */
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2005-04-17 06:20:36 +08:00
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/* PCI Definitions... */
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2006-01-12 04:17:49 +08:00
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#define SPX_VENDOR_ID 0x11CB /* Assigned by the PCI SIG */
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#define SPX_DEVICE_ID 0x8000 /* RIO bridge boards */
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#define SPX_PLXDEVICE_ID 0x2000 /* PLX bridge boards */
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2005-04-17 06:20:36 +08:00
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#define SPX_SUB_VENDOR_ID SPX_VENDOR_ID /* Same as vendor id */
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2006-01-12 04:17:49 +08:00
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#define RIO_SUB_SYS_ID 0x0800 /* RIO PCI board */
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2005-04-17 06:20:36 +08:00
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/*****************************************************************************
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***************************** ******************************
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***************************** RIO (Jet) PCI ******************************
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***************************** ******************************
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*****************************************************************************/
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/* Control Register Definitions... */
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#define RIO_PCI2_IDENT "JET HOST BY KEV#"
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2006-01-12 04:17:49 +08:00
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#define RIO_PCI2_CFG_BUSENABLE 0x02 /* Enable processor bus */
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#define RIO_PCI2_CFG_INTENABLE 0x04 /* Interrupt enable, else disable */
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2005-04-17 06:20:36 +08:00
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/* PCI Definitions... */
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2006-01-12 04:17:49 +08:00
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#define RIO2_SUB_SYS_ID 0x0100 /* RIO (Jet) PCI board */
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2005-04-17 06:20:36 +08:00
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#endif /*_rioboard_h */
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/* End of RIOBOARD.H */
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