2013-09-26 11:24:47 +08:00
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/*
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* PCIe host controller driver for Freescale i.MX6 SoCs
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*
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* Copyright (C) 2013 Kosagi
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* http://www.kosagi.com
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*
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* Author: Sean Cross <xobs@kosagi.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/gpio.h>
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#include <linux/kernel.h>
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#include <linux/mfd/syscon.h>
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#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
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#include <linux/module.h>
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#include <linux/of_gpio.h>
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2016-05-03 03:08:21 +08:00
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#include <linux/of_device.h>
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2013-09-26 11:24:47 +08:00
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#include <linux/pci.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/resource.h>
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#include <linux/signal.h>
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#include <linux/types.h>
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2014-03-29 00:52:59 +08:00
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#include <linux/interrupt.h>
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2013-09-26 11:24:47 +08:00
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#include "pcie-designware.h"
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2017-02-15 21:18:14 +08:00
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#define to_imx6_pcie(x) dev_get_drvdata((x)->dev)
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2013-09-26 11:24:47 +08:00
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2016-05-03 03:08:21 +08:00
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enum imx6_pcie_variants {
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IMX6Q,
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2016-05-03 03:09:10 +08:00
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IMX6SX,
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IMX6QP,
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2016-05-03 03:08:21 +08:00
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};
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2013-09-26 11:24:47 +08:00
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struct imx6_pcie {
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2017-02-15 21:18:14 +08:00
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struct dw_pcie *pci;
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2016-03-29 05:45:36 +08:00
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int reset_gpio;
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PCI: imx6: Add reset-gpio-active-high boolean property to DT
Currently the reset-gpio DT property which controls the PCI bus device
reset signal defaults to active-low reset sequence (L=reset state,
H=operation state) plus the code in reset function isn't GPIO polarity
aware - it doesn't matter if the defined reset-gpio is active-low or
active-high, it will always result into active-low reset sequence.
I've tried to fix it properly and change the reset-gpio reset sequence to
be polarity-aware, but this patch has been accepted and then reverted as it
has introduced few backward incompatible issues:
1. Some DTBs, for example, imx6qdl-sabresd, don't define reset-gpio
polarity correctly:
reset-gpio = <&gpio7 12 0>;
which means that it's defined as active-high, but in reality it's
active-low; thus it wouldn't work without a DTS fix.
2. The logic in the reset function is inverted:
gpio_set_value_cansleep(imx6_pcie->reset_gpio, 0)
msleep(100);
gpio_set_value_cansleep(imx6_pcie->reset_gpio, 1);
so even if some of the i.MX6 boards had reset-gpio polarity defined
correctly in their DTSes, they would stop working.
As we can't break old DTBs, we can't fix them, so we need to introduce this
new DT reset-gpio-active-high boolean property so we can support boards
with active-high reset sequence.
This active-high reset sequence is for example needed on Apalis SoMs, where
GPIO1_IO28, used to PCIe reset is not connected directly to PERST# PCIe
signal, but it's ORed with RESETBMCU coming off the PMIC, and thus is
inverted, active-high.
Tested-by: Tim Harvey <tharvey@gateworks.com> # Gateworks Ventana boards (which have active-low PERST#)
Signed-off-by: Petr Štetiar <ynezz@true.cz>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Acked-by: Rob Herring <robh@kernel.org>
2016-04-20 08:42:07 +08:00
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bool gpio_active_high;
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2014-03-29 00:52:55 +08:00
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struct clk *pcie_bus;
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struct clk *pcie_phy;
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2016-04-06 05:53:27 +08:00
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struct clk *pcie_inbound_axi;
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2014-03-29 00:52:55 +08:00
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struct clk *pcie;
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2013-09-26 11:24:47 +08:00
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struct regmap *iomuxc_gpr;
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2016-05-03 03:08:21 +08:00
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enum imx6_pcie_variants variant;
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2016-01-15 23:24:35 +08:00
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u32 tx_deemph_gen1;
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u32 tx_deemph_gen2_3p5db;
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u32 tx_deemph_gen2_6db;
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u32 tx_swing_full;
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u32 tx_swing_low;
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2016-04-20 08:52:44 +08:00
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int link_gen;
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2013-09-26 11:24:47 +08:00
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};
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2013-12-13 05:50:02 +08:00
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/* PCIe Root Complex registers (memory-mapped) */
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#define PCIE_RC_LCR 0x7c
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#define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1 0x1
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#define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2 0x2
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#define PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK 0xf
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2015-06-13 06:27:43 +08:00
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#define PCIE_RC_LCSR 0x80
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2013-09-26 11:24:47 +08:00
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/* PCIe Port Logic registers (memory-mapped) */
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#define PL_OFFSET 0x700
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2014-08-01 02:16:05 +08:00
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#define PCIE_PL_PFLR (PL_OFFSET + 0x08)
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#define PCIE_PL_PFLR_LINK_STATE_MASK (0x3f << 16)
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#define PCIE_PL_PFLR_FORCE_LINK (1 << 15)
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2013-09-26 11:24:47 +08:00
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#define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28)
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#define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c)
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2013-12-13 05:49:59 +08:00
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#define PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING (1 << 29)
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#define PCIE_PHY_DEBUG_R1_XMLH_LINK_UP (1 << 4)
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2013-09-26 11:24:47 +08:00
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#define PCIE_PHY_CTRL (PL_OFFSET + 0x114)
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#define PCIE_PHY_CTRL_DATA_LOC 0
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#define PCIE_PHY_CTRL_CAP_ADR_LOC 16
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#define PCIE_PHY_CTRL_CAP_DAT_LOC 17
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#define PCIE_PHY_CTRL_WR_LOC 18
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#define PCIE_PHY_CTRL_RD_LOC 19
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#define PCIE_PHY_STAT (PL_OFFSET + 0x110)
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#define PCIE_PHY_STAT_ACK_LOC 16
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2013-12-13 05:50:02 +08:00
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#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
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#define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
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2013-09-26 11:24:47 +08:00
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/* PHY registers (not memory-mapped) */
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#define PCIE_PHY_RX_ASIC_OUT 0x100D
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2015-09-11 20:08:53 +08:00
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#define PCIE_PHY_RX_ASIC_OUT_VALID (1 << 0)
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2013-09-26 11:24:47 +08:00
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#define PHY_RX_OVRD_IN_LO 0x1005
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#define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5)
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#define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3)
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2016-10-12 11:09:32 +08:00
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static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, int exp_val)
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2013-09-26 11:24:47 +08:00
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{
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2017-02-15 21:18:14 +08:00
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struct dw_pcie *pci = imx6_pcie->pci;
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2013-09-26 11:24:47 +08:00
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u32 val;
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u32 max_iterations = 10;
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u32 wait_counter = 0;
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do {
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2017-02-15 21:18:14 +08:00
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val = dw_pcie_readl_dbi(pci, PCIE_PHY_STAT);
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2013-09-26 11:24:47 +08:00
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val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1;
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wait_counter++;
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if (val == exp_val)
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return 0;
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udelay(1);
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} while (wait_counter < max_iterations);
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return -ETIMEDOUT;
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}
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2016-10-12 11:09:32 +08:00
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static int pcie_phy_wait_ack(struct imx6_pcie *imx6_pcie, int addr)
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2013-09-26 11:24:47 +08:00
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{
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2017-02-15 21:18:14 +08:00
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struct dw_pcie *pci = imx6_pcie->pci;
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2013-09-26 11:24:47 +08:00
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u32 val;
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int ret;
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val = addr << PCIE_PHY_CTRL_DATA_LOC;
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2017-02-15 21:18:14 +08:00
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dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val);
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2013-09-26 11:24:47 +08:00
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val |= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC);
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2017-02-15 21:18:14 +08:00
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dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val);
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2013-09-26 11:24:47 +08:00
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2016-10-12 11:09:32 +08:00
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ret = pcie_phy_poll_ack(imx6_pcie, 1);
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2013-09-26 11:24:47 +08:00
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if (ret)
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return ret;
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val = addr << PCIE_PHY_CTRL_DATA_LOC;
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2017-02-15 21:18:14 +08:00
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dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val);
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2013-09-26 11:24:47 +08:00
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2016-10-12 11:09:32 +08:00
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return pcie_phy_poll_ack(imx6_pcie, 0);
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2013-09-26 11:24:47 +08:00
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}
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/* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */
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2016-10-12 11:09:32 +08:00
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static int pcie_phy_read(struct imx6_pcie *imx6_pcie, int addr, int *data)
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2013-09-26 11:24:47 +08:00
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{
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2017-02-15 21:18:14 +08:00
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struct dw_pcie *pci = imx6_pcie->pci;
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2013-09-26 11:24:47 +08:00
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u32 val, phy_ctl;
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int ret;
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2016-10-12 11:09:32 +08:00
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ret = pcie_phy_wait_ack(imx6_pcie, addr);
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2013-09-26 11:24:47 +08:00
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if (ret)
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return ret;
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/* assert Read signal */
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phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC;
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2017-02-15 21:18:14 +08:00
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dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, phy_ctl);
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2013-09-26 11:24:47 +08:00
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2016-10-12 11:09:32 +08:00
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ret = pcie_phy_poll_ack(imx6_pcie, 1);
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2013-09-26 11:24:47 +08:00
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if (ret)
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return ret;
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2017-02-15 21:18:14 +08:00
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val = dw_pcie_readl_dbi(pci, PCIE_PHY_STAT);
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2013-09-26 11:24:47 +08:00
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*data = val & 0xffff;
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/* deassert Read signal */
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2017-02-15 21:18:14 +08:00
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dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, 0x00);
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2013-09-26 11:24:47 +08:00
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2016-10-12 11:09:32 +08:00
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return pcie_phy_poll_ack(imx6_pcie, 0);
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2013-09-26 11:24:47 +08:00
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}
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2016-10-12 11:09:32 +08:00
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static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, int data)
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2013-09-26 11:24:47 +08:00
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{
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2017-02-15 21:18:14 +08:00
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struct dw_pcie *pci = imx6_pcie->pci;
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2013-09-26 11:24:47 +08:00
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u32 var;
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int ret;
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/* write addr */
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/* cap addr */
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2016-10-12 11:09:32 +08:00
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ret = pcie_phy_wait_ack(imx6_pcie, addr);
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2013-09-26 11:24:47 +08:00
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if (ret)
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return ret;
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var = data << PCIE_PHY_CTRL_DATA_LOC;
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2017-02-15 21:18:14 +08:00
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dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
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2013-09-26 11:24:47 +08:00
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/* capture data */
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var |= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC);
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2017-02-15 21:18:14 +08:00
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dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
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2013-09-26 11:24:47 +08:00
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2016-10-12 11:09:32 +08:00
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ret = pcie_phy_poll_ack(imx6_pcie, 1);
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2013-09-26 11:24:47 +08:00
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if (ret)
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return ret;
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/* deassert cap data */
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var = data << PCIE_PHY_CTRL_DATA_LOC;
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2017-02-15 21:18:14 +08:00
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dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
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2013-09-26 11:24:47 +08:00
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/* wait for ack de-assertion */
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2016-10-12 11:09:32 +08:00
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ret = pcie_phy_poll_ack(imx6_pcie, 0);
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2013-09-26 11:24:47 +08:00
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if (ret)
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return ret;
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/* assert wr signal */
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var = 0x1 << PCIE_PHY_CTRL_WR_LOC;
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2017-02-15 21:18:14 +08:00
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dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
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2013-09-26 11:24:47 +08:00
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/* wait for ack */
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2016-10-12 11:09:32 +08:00
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ret = pcie_phy_poll_ack(imx6_pcie, 1);
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2013-09-26 11:24:47 +08:00
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if (ret)
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return ret;
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/* deassert wr signal */
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var = data << PCIE_PHY_CTRL_DATA_LOC;
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2017-02-15 21:18:14 +08:00
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dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
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2013-09-26 11:24:47 +08:00
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/* wait for ack de-assertion */
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2016-10-12 11:09:32 +08:00
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ret = pcie_phy_poll_ack(imx6_pcie, 0);
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2013-09-26 11:24:47 +08:00
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if (ret)
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return ret;
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2017-02-15 21:18:14 +08:00
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dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, 0x0);
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2013-09-26 11:24:47 +08:00
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return 0;
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}
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2016-10-12 11:06:47 +08:00
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static void imx6_pcie_reset_phy(struct imx6_pcie *imx6_pcie)
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2016-01-16 02:56:47 +08:00
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{
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u32 tmp;
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2016-10-12 11:09:32 +08:00
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pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &tmp);
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2016-01-16 02:56:47 +08:00
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tmp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN |
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PHY_RX_OVRD_IN_LO_RX_PLL_EN);
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2016-10-12 11:09:32 +08:00
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pcie_phy_write(imx6_pcie, PHY_RX_OVRD_IN_LO, tmp);
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2016-01-16 02:56:47 +08:00
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usleep_range(2000, 3000);
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2016-10-12 11:09:32 +08:00
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pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &tmp);
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2016-01-16 02:56:47 +08:00
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tmp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN |
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PHY_RX_OVRD_IN_LO_RX_PLL_EN);
|
2016-10-12 11:09:32 +08:00
|
|
|
pcie_phy_write(imx6_pcie, PHY_RX_OVRD_IN_LO, tmp);
|
2016-01-16 02:56:47 +08:00
|
|
|
}
|
|
|
|
|
|
2013-09-26 11:24:47 +08:00
|
|
|
/* Added for PCI abort handling */
|
|
|
|
|
static int imx6q_pcie_abort_handler(unsigned long addr,
|
|
|
|
|
unsigned int fsr, struct pt_regs *regs)
|
|
|
|
|
{
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2016-10-07 02:35:17 +08:00
|
|
|
static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie)
|
2013-09-26 11:24:47 +08:00
|
|
|
{
|
2016-05-03 03:08:21 +08:00
|
|
|
switch (imx6_pcie->variant) {
|
|
|
|
|
case IMX6SX:
|
2016-04-06 05:53:27 +08:00
|
|
|
regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
|
|
|
|
|
IMX6SX_GPR12_PCIE_TEST_POWERDOWN,
|
|
|
|
|
IMX6SX_GPR12_PCIE_TEST_POWERDOWN);
|
|
|
|
|
/* Force PCIe PHY reset */
|
|
|
|
|
regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
|
|
|
|
|
IMX6SX_GPR5_PCIE_BTNRST_RESET,
|
|
|
|
|
IMX6SX_GPR5_PCIE_BTNRST_RESET);
|
2016-05-03 03:08:21 +08:00
|
|
|
break;
|
2016-05-03 03:09:10 +08:00
|
|
|
case IMX6QP:
|
|
|
|
|
regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
|
|
|
|
|
IMX6Q_GPR1_PCIE_SW_RST,
|
|
|
|
|
IMX6Q_GPR1_PCIE_SW_RST);
|
|
|
|
|
break;
|
2016-05-03 03:08:21 +08:00
|
|
|
case IMX6Q:
|
|
|
|
|
regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
|
|
|
|
|
IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18);
|
|
|
|
|
regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
|
|
|
|
|
IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16);
|
|
|
|
|
break;
|
2014-08-01 02:16:05 +08:00
|
|
|
}
|
2013-09-26 11:24:47 +08:00
|
|
|
}
|
|
|
|
|
|
2016-03-14 07:30:55 +08:00
|
|
|
static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
|
|
|
|
|
{
|
2017-02-15 21:18:14 +08:00
|
|
|
struct dw_pcie *pci = imx6_pcie->pci;
|
|
|
|
|
struct device *dev = pci->dev;
|
2016-05-03 03:08:21 +08:00
|
|
|
int ret = 0;
|
2016-04-06 05:53:27 +08:00
|
|
|
|
2016-05-03 03:08:21 +08:00
|
|
|
switch (imx6_pcie->variant) {
|
|
|
|
|
case IMX6SX:
|
2016-04-06 05:53:27 +08:00
|
|
|
ret = clk_prepare_enable(imx6_pcie->pcie_inbound_axi);
|
|
|
|
|
if (ret) {
|
2016-10-07 02:35:18 +08:00
|
|
|
dev_err(dev, "unable to enable pcie_axi clock\n");
|
2016-05-03 03:08:21 +08:00
|
|
|
break;
|
2016-04-06 05:53:27 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
|
|
|
|
|
IMX6SX_GPR12_PCIE_TEST_POWERDOWN, 0);
|
2016-05-03 03:08:21 +08:00
|
|
|
break;
|
2016-05-03 03:09:10 +08:00
|
|
|
case IMX6QP: /* FALLTHROUGH */
|
2016-05-03 03:08:21 +08:00
|
|
|
case IMX6Q:
|
|
|
|
|
/* power up core phy and enable ref clock */
|
|
|
|
|
regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
|
|
|
|
|
IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);
|
|
|
|
|
/*
|
|
|
|
|
* the async reset input need ref clock to sync internally,
|
|
|
|
|
* when the ref clock comes after reset, internal synced
|
|
|
|
|
* reset time is too short, cannot meet the requirement.
|
|
|
|
|
* add one ~10us delay here.
|
|
|
|
|
*/
|
|
|
|
|
udelay(10);
|
|
|
|
|
regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
|
|
|
|
|
IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
|
|
|
|
|
break;
|
2016-04-06 05:53:27 +08:00
|
|
|
}
|
|
|
|
|
|
2016-05-03 03:08:21 +08:00
|
|
|
return ret;
|
2016-03-14 07:30:55 +08:00
|
|
|
}
|
|
|
|
|
|
2016-10-07 02:35:17 +08:00
|
|
|
static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
|
2013-09-26 11:24:47 +08:00
|
|
|
{
|
2017-02-15 21:18:14 +08:00
|
|
|
struct dw_pcie *pci = imx6_pcie->pci;
|
|
|
|
|
struct device *dev = pci->dev;
|
2013-09-26 11:24:47 +08:00
|
|
|
int ret;
|
|
|
|
|
|
2014-03-29 00:52:55 +08:00
|
|
|
ret = clk_prepare_enable(imx6_pcie->pcie_phy);
|
2013-09-26 11:24:47 +08:00
|
|
|
if (ret) {
|
2016-10-07 02:35:18 +08:00
|
|
|
dev_err(dev, "unable to enable pcie_phy clock\n");
|
2016-10-07 02:35:17 +08:00
|
|
|
return;
|
2013-09-26 11:24:47 +08:00
|
|
|
}
|
|
|
|
|
|
2014-03-29 00:52:55 +08:00
|
|
|
ret = clk_prepare_enable(imx6_pcie->pcie_bus);
|
2013-09-26 11:24:47 +08:00
|
|
|
if (ret) {
|
2016-10-07 02:35:18 +08:00
|
|
|
dev_err(dev, "unable to enable pcie_bus clock\n");
|
2014-03-29 00:52:55 +08:00
|
|
|
goto err_pcie_bus;
|
2013-09-26 11:24:47 +08:00
|
|
|
}
|
|
|
|
|
|
2014-03-29 00:52:55 +08:00
|
|
|
ret = clk_prepare_enable(imx6_pcie->pcie);
|
2013-09-26 11:24:47 +08:00
|
|
|
if (ret) {
|
2016-10-07 02:35:18 +08:00
|
|
|
dev_err(dev, "unable to enable pcie clock\n");
|
2014-03-29 00:52:55 +08:00
|
|
|
goto err_pcie;
|
2013-09-26 11:24:47 +08:00
|
|
|
}
|
|
|
|
|
|
2016-03-14 07:30:55 +08:00
|
|
|
ret = imx6_pcie_enable_ref_clk(imx6_pcie);
|
|
|
|
|
if (ret) {
|
2016-10-07 02:35:18 +08:00
|
|
|
dev_err(dev, "unable to enable pcie ref clock\n");
|
2016-03-14 07:30:55 +08:00
|
|
|
goto err_ref_clk;
|
|
|
|
|
}
|
2014-08-08 14:36:40 +08:00
|
|
|
|
2014-10-27 13:17:32 +08:00
|
|
|
/* allow the clocks to stabilize */
|
|
|
|
|
usleep_range(200, 500);
|
|
|
|
|
|
2013-12-13 05:50:03 +08:00
|
|
|
/* Some boards don't have PCIe reset GPIO. */
|
2016-03-29 05:45:36 +08:00
|
|
|
if (gpio_is_valid(imx6_pcie->reset_gpio)) {
|
PCI: imx6: Add reset-gpio-active-high boolean property to DT
Currently the reset-gpio DT property which controls the PCI bus device
reset signal defaults to active-low reset sequence (L=reset state,
H=operation state) plus the code in reset function isn't GPIO polarity
aware - it doesn't matter if the defined reset-gpio is active-low or
active-high, it will always result into active-low reset sequence.
I've tried to fix it properly and change the reset-gpio reset sequence to
be polarity-aware, but this patch has been accepted and then reverted as it
has introduced few backward incompatible issues:
1. Some DTBs, for example, imx6qdl-sabresd, don't define reset-gpio
polarity correctly:
reset-gpio = <&gpio7 12 0>;
which means that it's defined as active-high, but in reality it's
active-low; thus it wouldn't work without a DTS fix.
2. The logic in the reset function is inverted:
gpio_set_value_cansleep(imx6_pcie->reset_gpio, 0)
msleep(100);
gpio_set_value_cansleep(imx6_pcie->reset_gpio, 1);
so even if some of the i.MX6 boards had reset-gpio polarity defined
correctly in their DTSes, they would stop working.
As we can't break old DTBs, we can't fix them, so we need to introduce this
new DT reset-gpio-active-high boolean property so we can support boards
with active-high reset sequence.
This active-high reset sequence is for example needed on Apalis SoMs, where
GPIO1_IO28, used to PCIe reset is not connected directly to PERST# PCIe
signal, but it's ORed with RESETBMCU coming off the PMIC, and thus is
inverted, active-high.
Tested-by: Tim Harvey <tharvey@gateworks.com> # Gateworks Ventana boards (which have active-low PERST#)
Signed-off-by: Petr Štetiar <ynezz@true.cz>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Acked-by: Rob Herring <robh@kernel.org>
2016-04-20 08:42:07 +08:00
|
|
|
gpio_set_value_cansleep(imx6_pcie->reset_gpio,
|
|
|
|
|
imx6_pcie->gpio_active_high);
|
2013-12-13 05:50:03 +08:00
|
|
|
msleep(100);
|
PCI: imx6: Add reset-gpio-active-high boolean property to DT
Currently the reset-gpio DT property which controls the PCI bus device
reset signal defaults to active-low reset sequence (L=reset state,
H=operation state) plus the code in reset function isn't GPIO polarity
aware - it doesn't matter if the defined reset-gpio is active-low or
active-high, it will always result into active-low reset sequence.
I've tried to fix it properly and change the reset-gpio reset sequence to
be polarity-aware, but this patch has been accepted and then reverted as it
has introduced few backward incompatible issues:
1. Some DTBs, for example, imx6qdl-sabresd, don't define reset-gpio
polarity correctly:
reset-gpio = <&gpio7 12 0>;
which means that it's defined as active-high, but in reality it's
active-low; thus it wouldn't work without a DTS fix.
2. The logic in the reset function is inverted:
gpio_set_value_cansleep(imx6_pcie->reset_gpio, 0)
msleep(100);
gpio_set_value_cansleep(imx6_pcie->reset_gpio, 1);
so even if some of the i.MX6 boards had reset-gpio polarity defined
correctly in their DTSes, they would stop working.
As we can't break old DTBs, we can't fix them, so we need to introduce this
new DT reset-gpio-active-high boolean property so we can support boards
with active-high reset sequence.
This active-high reset sequence is for example needed on Apalis SoMs, where
GPIO1_IO28, used to PCIe reset is not connected directly to PERST# PCIe
signal, but it's ORed with RESETBMCU coming off the PMIC, and thus is
inverted, active-high.
Tested-by: Tim Harvey <tharvey@gateworks.com> # Gateworks Ventana boards (which have active-low PERST#)
Signed-off-by: Petr Štetiar <ynezz@true.cz>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Acked-by: Rob Herring <robh@kernel.org>
2016-04-20 08:42:07 +08:00
|
|
|
gpio_set_value_cansleep(imx6_pcie->reset_gpio,
|
|
|
|
|
!imx6_pcie->gpio_active_high);
|
2013-12-13 05:50:03 +08:00
|
|
|
}
|
2016-04-06 05:53:27 +08:00
|
|
|
|
2016-05-03 03:09:10 +08:00
|
|
|
switch (imx6_pcie->variant) {
|
|
|
|
|
case IMX6SX:
|
2016-04-06 05:53:27 +08:00
|
|
|
regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
|
|
|
|
|
IMX6SX_GPR5_PCIE_BTNRST_RESET, 0);
|
2016-05-03 03:09:10 +08:00
|
|
|
break;
|
|
|
|
|
case IMX6QP:
|
|
|
|
|
regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
|
|
|
|
|
IMX6Q_GPR1_PCIE_SW_RST, 0);
|
|
|
|
|
|
|
|
|
|
usleep_range(200, 500);
|
|
|
|
|
break;
|
|
|
|
|
case IMX6Q: /* Nothing to do */
|
|
|
|
|
break;
|
|
|
|
|
}
|
2016-04-06 05:53:27 +08:00
|
|
|
|
2016-10-07 02:35:17 +08:00
|
|
|
return;
|
2013-09-26 11:24:47 +08:00
|
|
|
|
2016-03-14 07:30:55 +08:00
|
|
|
err_ref_clk:
|
|
|
|
|
clk_disable_unprepare(imx6_pcie->pcie);
|
2014-03-29 00:52:55 +08:00
|
|
|
err_pcie:
|
|
|
|
|
clk_disable_unprepare(imx6_pcie->pcie_bus);
|
|
|
|
|
err_pcie_bus:
|
|
|
|
|
clk_disable_unprepare(imx6_pcie->pcie_phy);
|
2013-09-26 11:24:47 +08:00
|
|
|
}
|
|
|
|
|
|
2016-10-12 11:06:47 +08:00
|
|
|
static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
|
2013-09-26 11:24:47 +08:00
|
|
|
{
|
2016-05-03 03:08:21 +08:00
|
|
|
if (imx6_pcie->variant == IMX6SX)
|
2016-04-06 05:53:27 +08:00
|
|
|
regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
|
|
|
|
|
IMX6SX_GPR12_PCIE_RX_EQ_MASK,
|
|
|
|
|
IMX6SX_GPR12_PCIE_RX_EQ_2);
|
|
|
|
|
|
2013-09-26 11:24:47 +08:00
|
|
|
regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
|
|
|
|
|
IMX6Q_GPR12_PCIE_CTL_2, 0 << 10);
|
|
|
|
|
|
|
|
|
|
/* configure constant input signal to the pcie ctrl and phy */
|
|
|
|
|
regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
|
|
|
|
|
IMX6Q_GPR12_DEVICE_TYPE, PCI_EXP_TYPE_ROOT_PORT << 12);
|
|
|
|
|
regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
|
|
|
|
|
IMX6Q_GPR12_LOS_LEVEL, 9 << 4);
|
|
|
|
|
|
|
|
|
|
regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
|
2016-01-15 23:24:35 +08:00
|
|
|
IMX6Q_GPR8_TX_DEEMPH_GEN1,
|
|
|
|
|
imx6_pcie->tx_deemph_gen1 << 0);
|
2013-09-26 11:24:47 +08:00
|
|
|
regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
|
2016-01-15 23:24:35 +08:00
|
|
|
IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB,
|
|
|
|
|
imx6_pcie->tx_deemph_gen2_3p5db << 6);
|
2013-09-26 11:24:47 +08:00
|
|
|
regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
|
2016-01-15 23:24:35 +08:00
|
|
|
IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB,
|
|
|
|
|
imx6_pcie->tx_deemph_gen2_6db << 12);
|
2013-09-26 11:24:47 +08:00
|
|
|
regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
|
2016-01-15 23:24:35 +08:00
|
|
|
IMX6Q_GPR8_TX_SWING_FULL,
|
|
|
|
|
imx6_pcie->tx_swing_full << 18);
|
2013-09-26 11:24:47 +08:00
|
|
|
regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
|
2016-01-15 23:24:35 +08:00
|
|
|
IMX6Q_GPR8_TX_SWING_LOW,
|
|
|
|
|
imx6_pcie->tx_swing_low << 25);
|
2013-09-26 11:24:47 +08:00
|
|
|
}
|
|
|
|
|
|
2016-10-12 11:06:47 +08:00
|
|
|
static int imx6_pcie_wait_for_link(struct imx6_pcie *imx6_pcie)
|
2013-12-13 05:50:01 +08:00
|
|
|
{
|
2017-02-15 21:18:14 +08:00
|
|
|
struct dw_pcie *pci = imx6_pcie->pci;
|
|
|
|
|
struct device *dev = pci->dev;
|
2016-10-07 02:35:18 +08:00
|
|
|
|
PCI: designware: Add generic dw_pcie_wait_for_link()
Several DesignWare-based drivers (dra7xx, exynos, imx6, keystone, qcom, and
spear13xx) had similar loops waiting for the link to come up.
Add a generic dw_pcie_wait_for_link() for use by all these drivers so the
waiting is done consistently, e.g., always using usleep_range() rather than
mdelay() and using similar timeouts and retry counts.
Note that this changes the Keystone link training/wait for link strategy,
so we initiate link training, then wait longer for the link to come up
before re-initiating link training.
[bhelgaas: changelog, split into its own patch, update pci-keystone.c, pcie-qcom.c]
Signed-off-by: Joao Pinto <jpinto@synopsys.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Pratyush Anand <pratyush.anand@gmail.com>
2016-03-11 04:44:35 +08:00
|
|
|
/* check if the link is up or not */
|
2017-02-15 21:18:14 +08:00
|
|
|
if (!dw_pcie_wait_for_link(pci))
|
PCI: designware: Add generic dw_pcie_wait_for_link()
Several DesignWare-based drivers (dra7xx, exynos, imx6, keystone, qcom, and
spear13xx) had similar loops waiting for the link to come up.
Add a generic dw_pcie_wait_for_link() for use by all these drivers so the
waiting is done consistently, e.g., always using usleep_range() rather than
mdelay() and using similar timeouts and retry counts.
Note that this changes the Keystone link training/wait for link strategy,
so we initiate link training, then wait longer for the link to come up
before re-initiating link training.
[bhelgaas: changelog, split into its own patch, update pci-keystone.c, pcie-qcom.c]
Signed-off-by: Joao Pinto <jpinto@synopsys.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Pratyush Anand <pratyush.anand@gmail.com>
2016-03-11 04:44:35 +08:00
|
|
|
return 0;
|
2013-12-13 05:50:01 +08:00
|
|
|
|
2016-10-07 02:35:18 +08:00
|
|
|
dev_dbg(dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
|
2017-02-15 21:18:14 +08:00
|
|
|
dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R0),
|
|
|
|
|
dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R1));
|
PCI: designware: Add generic dw_pcie_wait_for_link()
Several DesignWare-based drivers (dra7xx, exynos, imx6, keystone, qcom, and
spear13xx) had similar loops waiting for the link to come up.
Add a generic dw_pcie_wait_for_link() for use by all these drivers so the
waiting is done consistently, e.g., always using usleep_range() rather than
mdelay() and using similar timeouts and retry counts.
Note that this changes the Keystone link training/wait for link strategy,
so we initiate link training, then wait longer for the link to come up
before re-initiating link training.
[bhelgaas: changelog, split into its own patch, update pci-keystone.c, pcie-qcom.c]
Signed-off-by: Joao Pinto <jpinto@synopsys.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Pratyush Anand <pratyush.anand@gmail.com>
2016-03-11 04:44:35 +08:00
|
|
|
return -ETIMEDOUT;
|
2013-12-13 05:50:01 +08:00
|
|
|
}
|
|
|
|
|
|
2016-10-12 11:06:47 +08:00
|
|
|
static int imx6_pcie_wait_for_speed_change(struct imx6_pcie *imx6_pcie)
|
2015-06-13 03:30:16 +08:00
|
|
|
{
|
2017-02-15 21:18:14 +08:00
|
|
|
struct dw_pcie *pci = imx6_pcie->pci;
|
|
|
|
|
struct device *dev = pci->dev;
|
2015-06-13 04:02:49 +08:00
|
|
|
u32 tmp;
|
2015-06-13 03:30:16 +08:00
|
|
|
unsigned int retries;
|
|
|
|
|
|
|
|
|
|
for (retries = 0; retries < 200; retries++) {
|
2017-02-15 21:18:14 +08:00
|
|
|
tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
|
2015-06-13 03:30:16 +08:00
|
|
|
/* Test if the speed change finished. */
|
|
|
|
|
if (!(tmp & PORT_LOGIC_SPEED_CHANGE))
|
|
|
|
|
return 0;
|
|
|
|
|
usleep_range(100, 1000);
|
|
|
|
|
}
|
|
|
|
|
|
2016-10-07 02:35:18 +08:00
|
|
|
dev_err(dev, "Speed change timeout\n");
|
2015-06-13 03:30:16 +08:00
|
|
|
return -EINVAL;
|
2013-12-13 05:50:01 +08:00
|
|
|
}
|
|
|
|
|
|
2014-03-29 00:52:59 +08:00
|
|
|
static irqreturn_t imx6_pcie_msi_handler(int irq, void *arg)
|
|
|
|
|
{
|
2016-10-12 11:06:47 +08:00
|
|
|
struct imx6_pcie *imx6_pcie = arg;
|
2017-02-15 21:18:14 +08:00
|
|
|
struct dw_pcie *pci = imx6_pcie->pci;
|
|
|
|
|
struct pcie_port *pp = &pci->pp;
|
2014-03-29 00:52:59 +08:00
|
|
|
|
|
|
|
|
return dw_handle_msi_irq(pp);
|
|
|
|
|
}
|
|
|
|
|
|
2016-10-12 11:06:47 +08:00
|
|
|
static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie)
|
2013-09-26 11:24:47 +08:00
|
|
|
{
|
2017-02-15 21:18:14 +08:00
|
|
|
struct dw_pcie *pci = imx6_pcie->pci;
|
|
|
|
|
struct device *dev = pci->dev;
|
2015-06-13 04:02:49 +08:00
|
|
|
u32 tmp;
|
2015-06-13 03:30:16 +08:00
|
|
|
int ret;
|
2013-12-13 05:50:02 +08:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Force Gen1 operation when starting the link. In case the link is
|
|
|
|
|
* started in Gen2 mode, there is a possibility the devices on the
|
|
|
|
|
* bus will not be detected at all. This happens with PCIe switches.
|
|
|
|
|
*/
|
2017-02-15 21:18:14 +08:00
|
|
|
tmp = dw_pcie_readl_dbi(pci, PCIE_RC_LCR);
|
2013-12-13 05:50:02 +08:00
|
|
|
tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
|
|
|
|
|
tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1;
|
2017-02-15 21:18:14 +08:00
|
|
|
dw_pcie_writel_dbi(pci, PCIE_RC_LCR, tmp);
|
2013-12-13 05:50:02 +08:00
|
|
|
|
|
|
|
|
/* Start LTSSM. */
|
|
|
|
|
regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
|
|
|
|
|
IMX6Q_GPR12_PCIE_CTL_2, 1 << 10);
|
|
|
|
|
|
2016-10-12 11:06:47 +08:00
|
|
|
ret = imx6_pcie_wait_for_link(imx6_pcie);
|
2016-12-27 22:40:43 +08:00
|
|
|
if (ret)
|
2016-01-26 06:49:53 +08:00
|
|
|
goto err_reset_phy;
|
2013-12-13 05:50:02 +08:00
|
|
|
|
2016-04-20 08:52:44 +08:00
|
|
|
if (imx6_pcie->link_gen == 2) {
|
|
|
|
|
/* Allow Gen2 mode after the link is up. */
|
2017-02-15 21:18:14 +08:00
|
|
|
tmp = dw_pcie_readl_dbi(pci, PCIE_RC_LCR);
|
2016-04-20 08:52:44 +08:00
|
|
|
tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
|
|
|
|
|
tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2;
|
2017-02-15 21:18:14 +08:00
|
|
|
dw_pcie_writel_dbi(pci, PCIE_RC_LCR, tmp);
|
2016-04-20 08:52:44 +08:00
|
|
|
} else {
|
2016-10-07 02:35:18 +08:00
|
|
|
dev_info(dev, "Link: Gen2 disabled\n");
|
2016-04-20 08:52:44 +08:00
|
|
|
}
|
2013-12-13 05:50:02 +08:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Start Directed Speed Change so the best possible speed both link
|
|
|
|
|
* partners support can be negotiated.
|
|
|
|
|
*/
|
2017-02-15 21:18:14 +08:00
|
|
|
tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
|
2013-12-13 05:50:02 +08:00
|
|
|
tmp |= PORT_LOGIC_SPEED_CHANGE;
|
2017-02-15 21:18:14 +08:00
|
|
|
dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp);
|
2013-12-13 05:50:02 +08:00
|
|
|
|
2016-10-12 11:06:47 +08:00
|
|
|
ret = imx6_pcie_wait_for_speed_change(imx6_pcie);
|
2015-06-13 03:30:16 +08:00
|
|
|
if (ret) {
|
2016-10-07 02:35:18 +08:00
|
|
|
dev_err(dev, "Failed to bring link up!\n");
|
2016-01-26 06:49:53 +08:00
|
|
|
goto err_reset_phy;
|
2013-12-13 05:50:02 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Make sure link training is finished as well! */
|
2016-10-12 11:06:47 +08:00
|
|
|
ret = imx6_pcie_wait_for_link(imx6_pcie);
|
2013-12-13 05:50:02 +08:00
|
|
|
if (ret) {
|
2016-10-07 02:35:18 +08:00
|
|
|
dev_err(dev, "Failed to bring link up!\n");
|
2016-01-26 06:49:53 +08:00
|
|
|
goto err_reset_phy;
|
2013-12-13 05:50:02 +08:00
|
|
|
}
|
|
|
|
|
|
2017-02-15 21:18:14 +08:00
|
|
|
tmp = dw_pcie_readl_dbi(pci, PCIE_RC_LCSR);
|
2016-10-07 02:35:18 +08:00
|
|
|
dev_info(dev, "Link up, Gen%i\n", (tmp >> 16) & 0xf);
|
2015-06-13 03:30:16 +08:00
|
|
|
return 0;
|
2016-01-26 06:49:53 +08:00
|
|
|
|
|
|
|
|
err_reset_phy:
|
2016-10-07 02:35:18 +08:00
|
|
|
dev_dbg(dev, "PHY DEBUG_R0=0x%08x DEBUG_R1=0x%08x\n",
|
2017-02-15 21:18:14 +08:00
|
|
|
dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R0),
|
|
|
|
|
dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R1));
|
2016-10-12 11:18:26 +08:00
|
|
|
imx6_pcie_reset_phy(imx6_pcie);
|
2016-01-26 06:49:53 +08:00
|
|
|
return ret;
|
2013-12-13 05:50:02 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void imx6_pcie_host_init(struct pcie_port *pp)
|
|
|
|
|
{
|
2017-02-15 21:18:14 +08:00
|
|
|
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
|
|
|
|
|
struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci);
|
2013-09-26 11:24:47 +08:00
|
|
|
|
2016-10-12 11:06:47 +08:00
|
|
|
imx6_pcie_assert_core_reset(imx6_pcie);
|
|
|
|
|
imx6_pcie_init_phy(imx6_pcie);
|
|
|
|
|
imx6_pcie_deassert_core_reset(imx6_pcie);
|
2013-09-26 11:24:47 +08:00
|
|
|
dw_pcie_setup_rc(pp);
|
2016-10-12 11:06:47 +08:00
|
|
|
imx6_pcie_establish_link(imx6_pcie);
|
2014-03-29 00:52:59 +08:00
|
|
|
|
|
|
|
|
if (IS_ENABLED(CONFIG_PCI_MSI))
|
|
|
|
|
dw_pcie_msi_init(pp);
|
2013-09-26 11:24:47 +08:00
|
|
|
}
|
|
|
|
|
|
2017-02-15 21:18:14 +08:00
|
|
|
static int imx6_pcie_link_up(struct dw_pcie *pci)
|
2013-09-26 11:24:47 +08:00
|
|
|
{
|
2017-02-15 21:18:14 +08:00
|
|
|
return dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R1) &
|
2016-01-26 06:50:02 +08:00
|
|
|
PCIE_PHY_DEBUG_R1_XMLH_LINK_UP;
|
2013-09-26 11:24:47 +08:00
|
|
|
}
|
|
|
|
|
|
2017-02-15 21:18:14 +08:00
|
|
|
static struct dw_pcie_host_ops imx6_pcie_host_ops = {
|
2013-09-26 11:24:47 +08:00
|
|
|
.host_init = imx6_pcie_host_init,
|
|
|
|
|
};
|
|
|
|
|
|
2016-10-12 11:06:47 +08:00
|
|
|
static int __init imx6_add_pcie_port(struct imx6_pcie *imx6_pcie,
|
|
|
|
|
struct platform_device *pdev)
|
2013-09-26 11:24:47 +08:00
|
|
|
{
|
2017-02-15 21:18:14 +08:00
|
|
|
struct dw_pcie *pci = imx6_pcie->pci;
|
|
|
|
|
struct pcie_port *pp = &pci->pp;
|
|
|
|
|
struct device *dev = &pdev->dev;
|
2013-09-26 11:24:47 +08:00
|
|
|
int ret;
|
|
|
|
|
|
2014-03-29 00:52:59 +08:00
|
|
|
if (IS_ENABLED(CONFIG_PCI_MSI)) {
|
|
|
|
|
pp->msi_irq = platform_get_irq_byname(pdev, "msi");
|
|
|
|
|
if (pp->msi_irq <= 0) {
|
2016-10-07 02:35:18 +08:00
|
|
|
dev_err(dev, "failed to get MSI irq\n");
|
2014-03-29 00:52:59 +08:00
|
|
|
return -ENODEV;
|
|
|
|
|
}
|
|
|
|
|
|
2016-10-07 02:35:18 +08:00
|
|
|
ret = devm_request_irq(dev, pp->msi_irq,
|
2014-11-12 11:25:09 +08:00
|
|
|
imx6_pcie_msi_handler,
|
2015-12-11 03:18:20 +08:00
|
|
|
IRQF_SHARED | IRQF_NO_THREAD,
|
2016-10-12 11:06:47 +08:00
|
|
|
"mx6-pcie-msi", imx6_pcie);
|
2014-03-29 00:52:59 +08:00
|
|
|
if (ret) {
|
2016-10-07 02:35:18 +08:00
|
|
|
dev_err(dev, "failed to request MSI irq\n");
|
2015-09-11 20:08:52 +08:00
|
|
|
return ret;
|
2014-03-29 00:52:59 +08:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2013-09-26 11:24:47 +08:00
|
|
|
pp->root_bus_nr = -1;
|
|
|
|
|
pp->ops = &imx6_pcie_host_ops;
|
|
|
|
|
|
|
|
|
|
ret = dw_pcie_host_init(pp);
|
|
|
|
|
if (ret) {
|
2016-10-07 02:35:18 +08:00
|
|
|
dev_err(dev, "failed to initialize host\n");
|
2013-09-26 11:24:47 +08:00
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2017-02-15 21:18:14 +08:00
|
|
|
static const struct dw_pcie_ops dw_pcie_ops = {
|
|
|
|
|
.link_up = imx6_pcie_link_up,
|
|
|
|
|
};
|
|
|
|
|
|
2013-09-26 11:24:47 +08:00
|
|
|
static int __init imx6_pcie_probe(struct platform_device *pdev)
|
|
|
|
|
{
|
2016-10-07 02:35:18 +08:00
|
|
|
struct device *dev = &pdev->dev;
|
2017-02-15 21:18:14 +08:00
|
|
|
struct dw_pcie *pci;
|
2013-09-26 11:24:47 +08:00
|
|
|
struct imx6_pcie *imx6_pcie;
|
|
|
|
|
struct resource *dbi_base;
|
2016-10-07 02:35:18 +08:00
|
|
|
struct device_node *node = dev->of_node;
|
2013-09-26 11:24:47 +08:00
|
|
|
int ret;
|
|
|
|
|
|
2016-10-07 02:35:18 +08:00
|
|
|
imx6_pcie = devm_kzalloc(dev, sizeof(*imx6_pcie), GFP_KERNEL);
|
2013-09-26 11:24:47 +08:00
|
|
|
if (!imx6_pcie)
|
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
2017-02-15 21:18:14 +08:00
|
|
|
pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
|
|
|
|
|
if (!pci)
|
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
|
|
pci->dev = dev;
|
|
|
|
|
pci->ops = &dw_pcie_ops;
|
2013-09-26 11:24:47 +08:00
|
|
|
|
2016-05-03 03:08:21 +08:00
|
|
|
imx6_pcie->variant =
|
2016-10-07 02:35:18 +08:00
|
|
|
(enum imx6_pcie_variants)of_device_get_match_data(dev);
|
2016-04-06 05:53:27 +08:00
|
|
|
|
2013-09-26 11:24:47 +08:00
|
|
|
/* Added for PCI abort handling */
|
|
|
|
|
hook_fault_code(16 + 6, imx6q_pcie_abort_handler, SIGBUS, 0,
|
|
|
|
|
"imprecise external abort");
|
|
|
|
|
|
|
|
|
|
dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
2017-02-15 21:18:14 +08:00
|
|
|
pci->dbi_base = devm_ioremap_resource(dev, dbi_base);
|
|
|
|
|
if (IS_ERR(pci->dbi_base))
|
|
|
|
|
return PTR_ERR(pci->dbi_base);
|
2013-09-26 11:24:47 +08:00
|
|
|
|
|
|
|
|
/* Fetch GPIOs */
|
2016-10-07 02:35:18 +08:00
|
|
|
imx6_pcie->reset_gpio = of_get_named_gpio(node, "reset-gpio", 0);
|
|
|
|
|
imx6_pcie->gpio_active_high = of_property_read_bool(node,
|
PCI: imx6: Add reset-gpio-active-high boolean property to DT
Currently the reset-gpio DT property which controls the PCI bus device
reset signal defaults to active-low reset sequence (L=reset state,
H=operation state) plus the code in reset function isn't GPIO polarity
aware - it doesn't matter if the defined reset-gpio is active-low or
active-high, it will always result into active-low reset sequence.
I've tried to fix it properly and change the reset-gpio reset sequence to
be polarity-aware, but this patch has been accepted and then reverted as it
has introduced few backward incompatible issues:
1. Some DTBs, for example, imx6qdl-sabresd, don't define reset-gpio
polarity correctly:
reset-gpio = <&gpio7 12 0>;
which means that it's defined as active-high, but in reality it's
active-low; thus it wouldn't work without a DTS fix.
2. The logic in the reset function is inverted:
gpio_set_value_cansleep(imx6_pcie->reset_gpio, 0)
msleep(100);
gpio_set_value_cansleep(imx6_pcie->reset_gpio, 1);
so even if some of the i.MX6 boards had reset-gpio polarity defined
correctly in their DTSes, they would stop working.
As we can't break old DTBs, we can't fix them, so we need to introduce this
new DT reset-gpio-active-high boolean property so we can support boards
with active-high reset sequence.
This active-high reset sequence is for example needed on Apalis SoMs, where
GPIO1_IO28, used to PCIe reset is not connected directly to PERST# PCIe
signal, but it's ORed with RESETBMCU coming off the PMIC, and thus is
inverted, active-high.
Tested-by: Tim Harvey <tharvey@gateworks.com> # Gateworks Ventana boards (which have active-low PERST#)
Signed-off-by: Petr Štetiar <ynezz@true.cz>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Acked-by: Rob Herring <robh@kernel.org>
2016-04-20 08:42:07 +08:00
|
|
|
"reset-gpio-active-high");
|
2016-03-29 05:45:36 +08:00
|
|
|
if (gpio_is_valid(imx6_pcie->reset_gpio)) {
|
2016-10-07 02:35:18 +08:00
|
|
|
ret = devm_gpio_request_one(dev, imx6_pcie->reset_gpio,
|
PCI: imx6: Add reset-gpio-active-high boolean property to DT
Currently the reset-gpio DT property which controls the PCI bus device
reset signal defaults to active-low reset sequence (L=reset state,
H=operation state) plus the code in reset function isn't GPIO polarity
aware - it doesn't matter if the defined reset-gpio is active-low or
active-high, it will always result into active-low reset sequence.
I've tried to fix it properly and change the reset-gpio reset sequence to
be polarity-aware, but this patch has been accepted and then reverted as it
has introduced few backward incompatible issues:
1. Some DTBs, for example, imx6qdl-sabresd, don't define reset-gpio
polarity correctly:
reset-gpio = <&gpio7 12 0>;
which means that it's defined as active-high, but in reality it's
active-low; thus it wouldn't work without a DTS fix.
2. The logic in the reset function is inverted:
gpio_set_value_cansleep(imx6_pcie->reset_gpio, 0)
msleep(100);
gpio_set_value_cansleep(imx6_pcie->reset_gpio, 1);
so even if some of the i.MX6 boards had reset-gpio polarity defined
correctly in their DTSes, they would stop working.
As we can't break old DTBs, we can't fix them, so we need to introduce this
new DT reset-gpio-active-high boolean property so we can support boards
with active-high reset sequence.
This active-high reset sequence is for example needed on Apalis SoMs, where
GPIO1_IO28, used to PCIe reset is not connected directly to PERST# PCIe
signal, but it's ORed with RESETBMCU coming off the PMIC, and thus is
inverted, active-high.
Tested-by: Tim Harvey <tharvey@gateworks.com> # Gateworks Ventana boards (which have active-low PERST#)
Signed-off-by: Petr Štetiar <ynezz@true.cz>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Acked-by: Rob Herring <robh@kernel.org>
2016-04-20 08:42:07 +08:00
|
|
|
imx6_pcie->gpio_active_high ?
|
|
|
|
|
GPIOF_OUT_INIT_HIGH :
|
|
|
|
|
GPIOF_OUT_INIT_LOW,
|
|
|
|
|
"PCIe reset");
|
2016-03-29 05:45:36 +08:00
|
|
|
if (ret) {
|
2016-10-07 02:35:18 +08:00
|
|
|
dev_err(dev, "unable to get reset gpio\n");
|
2016-03-29 05:45:36 +08:00
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
}
|
2013-09-26 11:24:47 +08:00
|
|
|
|
|
|
|
|
/* Fetch clocks */
|
2016-10-07 02:35:18 +08:00
|
|
|
imx6_pcie->pcie_phy = devm_clk_get(dev, "pcie_phy");
|
2014-03-29 00:52:55 +08:00
|
|
|
if (IS_ERR(imx6_pcie->pcie_phy)) {
|
2016-10-07 02:35:18 +08:00
|
|
|
dev_err(dev, "pcie_phy clock source missing or invalid\n");
|
2014-03-29 00:52:55 +08:00
|
|
|
return PTR_ERR(imx6_pcie->pcie_phy);
|
2013-09-26 11:24:47 +08:00
|
|
|
}
|
|
|
|
|
|
2016-10-07 02:35:18 +08:00
|
|
|
imx6_pcie->pcie_bus = devm_clk_get(dev, "pcie_bus");
|
2014-03-29 00:52:55 +08:00
|
|
|
if (IS_ERR(imx6_pcie->pcie_bus)) {
|
2016-10-07 02:35:18 +08:00
|
|
|
dev_err(dev, "pcie_bus clock source missing or invalid\n");
|
2014-03-29 00:52:55 +08:00
|
|
|
return PTR_ERR(imx6_pcie->pcie_bus);
|
2013-09-26 11:24:47 +08:00
|
|
|
}
|
|
|
|
|
|
2016-10-07 02:35:18 +08:00
|
|
|
imx6_pcie->pcie = devm_clk_get(dev, "pcie");
|
2014-03-29 00:52:55 +08:00
|
|
|
if (IS_ERR(imx6_pcie->pcie)) {
|
2016-10-07 02:35:18 +08:00
|
|
|
dev_err(dev, "pcie clock source missing or invalid\n");
|
2014-03-29 00:52:55 +08:00
|
|
|
return PTR_ERR(imx6_pcie->pcie);
|
2013-09-26 11:24:47 +08:00
|
|
|
}
|
|
|
|
|
|
2016-05-03 03:08:21 +08:00
|
|
|
if (imx6_pcie->variant == IMX6SX) {
|
2016-10-07 02:35:18 +08:00
|
|
|
imx6_pcie->pcie_inbound_axi = devm_clk_get(dev,
|
2016-04-06 05:53:27 +08:00
|
|
|
"pcie_inbound_axi");
|
|
|
|
|
if (IS_ERR(imx6_pcie->pcie_inbound_axi)) {
|
2017-02-07 23:50:25 +08:00
|
|
|
dev_err(dev, "pcie_inbound_axi clock missing or invalid\n");
|
2016-04-06 05:53:27 +08:00
|
|
|
return PTR_ERR(imx6_pcie->pcie_inbound_axi);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2013-09-26 11:24:47 +08:00
|
|
|
/* Grab GPR config register range */
|
|
|
|
|
imx6_pcie->iomuxc_gpr =
|
|
|
|
|
syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
|
|
|
|
|
if (IS_ERR(imx6_pcie->iomuxc_gpr)) {
|
2016-10-07 02:35:18 +08:00
|
|
|
dev_err(dev, "unable to find iomuxc registers\n");
|
2013-12-02 11:39:35 +08:00
|
|
|
return PTR_ERR(imx6_pcie->iomuxc_gpr);
|
2013-09-26 11:24:47 +08:00
|
|
|
}
|
2016-01-15 23:24:35 +08:00
|
|
|
|
|
|
|
|
/* Grab PCIe PHY Tx Settings */
|
|
|
|
|
if (of_property_read_u32(node, "fsl,tx-deemph-gen1",
|
|
|
|
|
&imx6_pcie->tx_deemph_gen1))
|
|
|
|
|
imx6_pcie->tx_deemph_gen1 = 0;
|
|
|
|
|
|
|
|
|
|
if (of_property_read_u32(node, "fsl,tx-deemph-gen2-3p5db",
|
|
|
|
|
&imx6_pcie->tx_deemph_gen2_3p5db))
|
|
|
|
|
imx6_pcie->tx_deemph_gen2_3p5db = 0;
|
|
|
|
|
|
|
|
|
|
if (of_property_read_u32(node, "fsl,tx-deemph-gen2-6db",
|
|
|
|
|
&imx6_pcie->tx_deemph_gen2_6db))
|
|
|
|
|
imx6_pcie->tx_deemph_gen2_6db = 20;
|
|
|
|
|
|
|
|
|
|
if (of_property_read_u32(node, "fsl,tx-swing-full",
|
|
|
|
|
&imx6_pcie->tx_swing_full))
|
|
|
|
|
imx6_pcie->tx_swing_full = 127;
|
|
|
|
|
|
|
|
|
|
if (of_property_read_u32(node, "fsl,tx-swing-low",
|
|
|
|
|
&imx6_pcie->tx_swing_low))
|
|
|
|
|
imx6_pcie->tx_swing_low = 127;
|
2013-09-26 11:24:47 +08:00
|
|
|
|
2016-04-20 08:52:44 +08:00
|
|
|
/* Limit link speed */
|
2016-10-07 02:35:18 +08:00
|
|
|
ret = of_property_read_u32(node, "fsl,max-link-speed",
|
2016-04-20 08:52:44 +08:00
|
|
|
&imx6_pcie->link_gen);
|
|
|
|
|
if (ret)
|
|
|
|
|
imx6_pcie->link_gen = 1;
|
|
|
|
|
|
2017-02-15 21:18:11 +08:00
|
|
|
platform_set_drvdata(pdev, imx6_pcie);
|
|
|
|
|
|
2016-10-12 11:06:47 +08:00
|
|
|
ret = imx6_add_pcie_port(imx6_pcie, pdev);
|
2013-09-26 11:24:47 +08:00
|
|
|
if (ret < 0)
|
2013-12-02 11:39:35 +08:00
|
|
|
return ret;
|
2013-09-26 11:24:47 +08:00
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2014-08-01 02:16:05 +08:00
|
|
|
static void imx6_pcie_shutdown(struct platform_device *pdev)
|
|
|
|
|
{
|
|
|
|
|
struct imx6_pcie *imx6_pcie = platform_get_drvdata(pdev);
|
|
|
|
|
|
|
|
|
|
/* bring down link, so bootloader gets clean state in case of reboot */
|
2016-10-12 11:06:47 +08:00
|
|
|
imx6_pcie_assert_core_reset(imx6_pcie);
|
2014-08-01 02:16:05 +08:00
|
|
|
}
|
|
|
|
|
|
2013-09-26 11:24:47 +08:00
|
|
|
static const struct of_device_id imx6_pcie_of_match[] = {
|
2016-05-03 03:08:21 +08:00
|
|
|
{ .compatible = "fsl,imx6q-pcie", .data = (void *)IMX6Q, },
|
|
|
|
|
{ .compatible = "fsl,imx6sx-pcie", .data = (void *)IMX6SX, },
|
2016-05-03 03:09:10 +08:00
|
|
|
{ .compatible = "fsl,imx6qp-pcie", .data = (void *)IMX6QP, },
|
2013-09-26 11:24:47 +08:00
|
|
|
{},
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static struct platform_driver imx6_pcie_driver = {
|
|
|
|
|
.driver = {
|
|
|
|
|
.name = "imx6q-pcie",
|
2013-10-21 17:06:41 +08:00
|
|
|
.of_match_table = imx6_pcie_of_match,
|
2013-09-26 11:24:47 +08:00
|
|
|
},
|
2014-08-01 02:16:05 +08:00
|
|
|
.shutdown = imx6_pcie_shutdown,
|
2013-09-26 11:24:47 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static int __init imx6_pcie_init(void)
|
|
|
|
|
{
|
|
|
|
|
return platform_driver_probe(&imx6_pcie_driver, imx6_pcie_probe);
|
|
|
|
|
}
|
2016-08-23 05:59:43 +08:00
|
|
|
device_initcall(imx6_pcie_init);
|