53 lines
2.1 KiB
Plaintext
53 lines
2.1 KiB
Plaintext
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ARM Cache Coherent Network
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==========================
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CCN-504 is a ring-bus interconnect consisting of 11 crosspoints
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(XPs), with each crosspoint supporting up to two device ports,
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so nodes (devices) 0 and 1 are connected to crosspoint 0,
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nodes 2 and 3 to crosspoint 1 etc.
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PMU (perf) driver
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-----------------
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The CCN driver registers a perf PMU driver, which provides
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description of available events and configuration options
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in sysfs, see /sys/bus/event_source/devices/ccn*.
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The "format" directory describes format of the config, config1
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and config2 fields of the perf_event_attr structure. The "events"
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directory provides configuration templates for all documented
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events, that can be used with perf tool. For example "xp_valid_flit"
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is an equivalent of "type=0x8,event=0x4". Other parameters must be
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explicitly specified. For events originating from device, "node"
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defines its index. All crosspoint events require "xp" (index),
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"port" (device port number) and "vc" (virtual channel ID) and
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"dir" (direction). Watchpoints (special "event" value 0xfe) also
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require comparator values ("cmp_l" and "cmp_h") and "mask", being
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index of the comparator mask.
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Masks are defined separately from the event description
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(due to limited number of the config values) in the "cmp_mask"
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directory, with first 8 configurable by user and additional
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4 hardcoded for the most frequent use cases.
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Cycle counter is described by a "type" value 0xff and does
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not require any other settings.
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Example of perf tool use:
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/ # perf list | grep ccn
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ccn/cycles/ [Kernel PMU event]
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<...>
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ccn/xp_valid_flit/ [Kernel PMU event]
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<...>
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/ # perf stat -C 0 -e ccn/cycles/,ccn/xp_valid_flit,xp=1,port=0,vc=1,dir=1/ \
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sleep 1
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The driver does not support sampling, therefore "perf record" will
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not work. Also notice that only single cpu is being selected
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("-C 0") - this is because perf framework does not support
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"non-CPU related" counters (yet?) so system-wide session ("-a")
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would try (and in most cases fail) to set up the same event
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per each CPU.
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