388 lines
9.6 KiB
C
388 lines
9.6 KiB
C
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/*
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* Au12x0/Au1550 PSC ALSA ASoC audio support.
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*
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* (c) 2007-2008 MSC Vertriebsges.m.b.H.,
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* Manuel Lauss <mano@roarinelk.homelinux.net>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Au1xxx-PSC AC97 glue.
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*
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* NOTE: all of these drivers can only work with a SINGLE instance
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* of a PSC. Multiple independent audio devices are impossible
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* with ASoC v1.
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/device.h>
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#include <linux/delay.h>
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#include <linux/suspend.h>
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#include <sound/core.h>
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#include <sound/pcm.h>
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#include <sound/initval.h>
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#include <sound/soc.h>
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#include <asm/mach-au1x00/au1000.h>
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#include <asm/mach-au1x00/au1xxx_psc.h>
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#include "psc.h"
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#define AC97_DIR \
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(SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE)
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#define AC97_RATES \
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SNDRV_PCM_RATE_8000_48000
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#define AC97_FMTS \
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(SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3BE)
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#define AC97PCR_START(stype) \
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((stype) == PCM_TX ? PSC_AC97PCR_TS : PSC_AC97PCR_RS)
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#define AC97PCR_STOP(stype) \
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((stype) == PCM_TX ? PSC_AC97PCR_TP : PSC_AC97PCR_RP)
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#define AC97PCR_CLRFIFO(stype) \
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((stype) == PCM_TX ? PSC_AC97PCR_TC : PSC_AC97PCR_RC)
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/* instance data. There can be only one, MacLeod!!!! */
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static struct au1xpsc_audio_data *au1xpsc_ac97_workdata;
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/* AC97 controller reads codec register */
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static unsigned short au1xpsc_ac97_read(struct snd_ac97 *ac97,
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unsigned short reg)
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{
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/* FIXME */
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struct au1xpsc_audio_data *pscdata = au1xpsc_ac97_workdata;
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unsigned short data, tmo;
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au_writel(PSC_AC97CDC_RD | PSC_AC97CDC_INDX(reg), AC97_CDC(pscdata));
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au_sync();
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tmo = 1000;
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while ((!(au_readl(AC97_EVNT(pscdata)) & PSC_AC97EVNT_CD)) && --tmo)
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udelay(2);
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if (!tmo)
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data = 0xffff;
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else
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data = au_readl(AC97_CDC(pscdata)) & 0xffff;
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au_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata));
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au_sync();
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return data;
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}
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/* AC97 controller writes to codec register */
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static void au1xpsc_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
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unsigned short val)
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{
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/* FIXME */
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struct au1xpsc_audio_data *pscdata = au1xpsc_ac97_workdata;
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unsigned int tmo;
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au_writel(PSC_AC97CDC_INDX(reg) | (val & 0xffff), AC97_CDC(pscdata));
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au_sync();
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tmo = 1000;
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while ((!(au_readl(AC97_EVNT(pscdata)) & PSC_AC97EVNT_CD)) && --tmo)
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au_sync();
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au_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata));
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au_sync();
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}
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/* AC97 controller asserts a warm reset */
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static void au1xpsc_ac97_warm_reset(struct snd_ac97 *ac97)
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{
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/* FIXME */
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struct au1xpsc_audio_data *pscdata = au1xpsc_ac97_workdata;
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au_writel(PSC_AC97RST_SNC, AC97_RST(pscdata));
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au_sync();
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msleep(10);
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au_writel(0, AC97_RST(pscdata));
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au_sync();
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}
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static void au1xpsc_ac97_cold_reset(struct snd_ac97 *ac97)
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{
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/* FIXME */
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struct au1xpsc_audio_data *pscdata = au1xpsc_ac97_workdata;
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int i;
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/* disable PSC during cold reset */
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au_writel(0, AC97_CFG(au1xpsc_ac97_workdata));
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au_sync();
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au_writel(PSC_CTRL_DISABLE, PSC_CTRL(pscdata));
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au_sync();
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/* issue cold reset */
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au_writel(PSC_AC97RST_RST, AC97_RST(pscdata));
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au_sync();
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msleep(500);
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au_writel(0, AC97_RST(pscdata));
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au_sync();
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/* enable PSC */
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au_writel(PSC_CTRL_ENABLE, PSC_CTRL(pscdata));
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au_sync();
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/* wait for PSC to indicate it's ready */
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i = 100000;
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while (!((au_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_SR)) && (--i))
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au_sync();
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if (i == 0) {
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printk(KERN_ERR "au1xpsc-ac97: PSC not ready!\n");
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return;
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}
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/* enable the ac97 function */
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au_writel(pscdata->cfg | PSC_AC97CFG_DE_ENABLE, AC97_CFG(pscdata));
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au_sync();
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/* wait for AC97 core to become ready */
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i = 100000;
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while (!((au_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_DR)) && (--i))
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au_sync();
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if (i == 0)
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printk(KERN_ERR "au1xpsc-ac97: AC97 ctrl not ready\n");
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}
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/* AC97 controller operations */
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struct snd_ac97_bus_ops soc_ac97_ops = {
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.read = au1xpsc_ac97_read,
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.write = au1xpsc_ac97_write,
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.reset = au1xpsc_ac97_cold_reset,
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.warm_reset = au1xpsc_ac97_warm_reset,
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};
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EXPORT_SYMBOL_GPL(soc_ac97_ops);
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static int au1xpsc_ac97_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params)
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{
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/* FIXME */
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struct au1xpsc_audio_data *pscdata = au1xpsc_ac97_workdata;
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unsigned long r, stat;
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int chans, stype = SUBSTREAM_TYPE(substream);
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chans = params_channels(params);
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r = au_readl(AC97_CFG(pscdata));
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stat = au_readl(AC97_STAT(pscdata));
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/* already active? */
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if (stat & (PSC_AC97STAT_TB | PSC_AC97STAT_RB)) {
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/* reject parameters not currently set up */
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if ((PSC_AC97CFG_GET_LEN(r) != params->msbits) ||
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(pscdata->rate != params_rate(params)))
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return -EINVAL;
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} else {
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/* disable AC97 device controller first */
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au_writel(r & ~PSC_AC97CFG_DE_ENABLE, AC97_CFG(pscdata));
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au_sync();
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/* set sample bitdepth: REG[24:21]=(BITS-2)/2 */
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r &= ~PSC_AC97CFG_LEN_MASK;
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r |= PSC_AC97CFG_SET_LEN(params->msbits);
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/* channels: enable slots for front L/R channel */
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if (stype == PCM_TX) {
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r &= ~PSC_AC97CFG_TXSLOT_MASK;
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r |= PSC_AC97CFG_TXSLOT_ENA(3);
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r |= PSC_AC97CFG_TXSLOT_ENA(4);
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} else {
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r &= ~PSC_AC97CFG_RXSLOT_MASK;
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r |= PSC_AC97CFG_RXSLOT_ENA(3);
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r |= PSC_AC97CFG_RXSLOT_ENA(4);
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}
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/* finally enable the AC97 controller again */
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au_writel(r | PSC_AC97CFG_DE_ENABLE, AC97_CFG(pscdata));
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au_sync();
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pscdata->cfg = r;
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pscdata->rate = params_rate(params);
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}
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return 0;
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}
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static int au1xpsc_ac97_trigger(struct snd_pcm_substream *substream,
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int cmd)
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{
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/* FIXME */
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struct au1xpsc_audio_data *pscdata = au1xpsc_ac97_workdata;
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int ret, stype = SUBSTREAM_TYPE(substream);
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ret = 0;
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switch (cmd) {
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case SNDRV_PCM_TRIGGER_START:
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case SNDRV_PCM_TRIGGER_RESUME:
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au_writel(AC97PCR_START(stype), AC97_PCR(pscdata));
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au_sync();
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break;
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case SNDRV_PCM_TRIGGER_STOP:
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case SNDRV_PCM_TRIGGER_SUSPEND:
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au_writel(AC97PCR_STOP(stype), AC97_PCR(pscdata));
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au_sync();
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break;
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default:
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ret = -EINVAL;
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}
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return ret;
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}
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static int au1xpsc_ac97_probe(struct platform_device *pdev,
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struct snd_soc_dai *dai)
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{
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int ret;
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struct resource *r;
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unsigned long sel;
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if (au1xpsc_ac97_workdata)
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return -EBUSY;
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au1xpsc_ac97_workdata =
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kzalloc(sizeof(struct au1xpsc_audio_data), GFP_KERNEL);
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if (!au1xpsc_ac97_workdata)
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return -ENOMEM;
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r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!r) {
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ret = -ENODEV;
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goto out0;
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}
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ret = -EBUSY;
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au1xpsc_ac97_workdata->ioarea =
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request_mem_region(r->start, r->end - r->start + 1,
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"au1xpsc_ac97");
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if (!au1xpsc_ac97_workdata->ioarea)
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goto out0;
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au1xpsc_ac97_workdata->mmio = ioremap(r->start, 0xffff);
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if (!au1xpsc_ac97_workdata->mmio)
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goto out1;
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/* configuration: max dma trigger threshold, enable ac97 */
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au1xpsc_ac97_workdata->cfg = PSC_AC97CFG_RT_FIFO8 |
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PSC_AC97CFG_TT_FIFO8 |
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PSC_AC97CFG_DE_ENABLE;
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/* preserve PSC clock source set up by platform (dev.platform_data
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* is already occupied by soc layer)
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*/
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sel = au_readl(PSC_SEL(au1xpsc_ac97_workdata)) & PSC_SEL_CLK_MASK;
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au_writel(PSC_CTRL_DISABLE, PSC_CTRL(au1xpsc_ac97_workdata));
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au_sync();
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au_writel(0, PSC_SEL(au1xpsc_ac97_workdata));
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au_sync();
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au_writel(PSC_SEL_PS_AC97MODE | sel, PSC_SEL(au1xpsc_ac97_workdata));
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au_sync();
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/* next up: cold reset. Dont check for PSC-ready now since
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* there may not be any codec clock yet.
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*/
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return 0;
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out1:
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release_resource(au1xpsc_ac97_workdata->ioarea);
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kfree(au1xpsc_ac97_workdata->ioarea);
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out0:
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kfree(au1xpsc_ac97_workdata);
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au1xpsc_ac97_workdata = NULL;
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return ret;
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}
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static void au1xpsc_ac97_remove(struct platform_device *pdev,
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struct snd_soc_dai *dai)
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{
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/* disable PSC completely */
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au_writel(0, AC97_CFG(au1xpsc_ac97_workdata));
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au_sync();
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au_writel(PSC_CTRL_DISABLE, PSC_CTRL(au1xpsc_ac97_workdata));
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au_sync();
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iounmap(au1xpsc_ac97_workdata->mmio);
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release_resource(au1xpsc_ac97_workdata->ioarea);
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kfree(au1xpsc_ac97_workdata->ioarea);
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kfree(au1xpsc_ac97_workdata);
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au1xpsc_ac97_workdata = NULL;
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}
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static int au1xpsc_ac97_suspend(struct platform_device *pdev,
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struct snd_soc_dai *dai)
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{
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/* save interesting registers and disable PSC */
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au1xpsc_ac97_workdata->pm[0] =
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au_readl(PSC_SEL(au1xpsc_ac97_workdata));
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au_writel(0, AC97_CFG(au1xpsc_ac97_workdata));
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au_sync();
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au_writel(PSC_CTRL_DISABLE, PSC_CTRL(au1xpsc_ac97_workdata));
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au_sync();
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return 0;
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}
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static int au1xpsc_ac97_resume(struct platform_device *pdev,
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struct snd_soc_dai *dai)
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{
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/* restore PSC clock config */
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au_writel(au1xpsc_ac97_workdata->pm[0] | PSC_SEL_PS_AC97MODE,
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PSC_SEL(au1xpsc_ac97_workdata));
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au_sync();
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/* after this point the ac97 core will cold-reset the codec.
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* During cold-reset the PSC is reinitialized and the last
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* configuration set up in hw_params() is restored.
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*/
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return 0;
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}
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struct snd_soc_dai au1xpsc_ac97_dai = {
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.name = "au1xpsc_ac97",
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.type = SND_SOC_DAI_AC97,
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.probe = au1xpsc_ac97_probe,
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.remove = au1xpsc_ac97_remove,
|
||
|
|
.suspend = au1xpsc_ac97_suspend,
|
||
|
|
.resume = au1xpsc_ac97_resume,
|
||
|
|
.playback = {
|
||
|
|
.rates = AC97_RATES,
|
||
|
|
.formats = AC97_FMTS,
|
||
|
|
.channels_min = 2,
|
||
|
|
.channels_max = 2,
|
||
|
|
},
|
||
|
|
.capture = {
|
||
|
|
.rates = AC97_RATES,
|
||
|
|
.formats = AC97_FMTS,
|
||
|
|
.channels_min = 2,
|
||
|
|
.channels_max = 2,
|
||
|
|
},
|
||
|
|
.ops = {
|
||
|
|
.trigger = au1xpsc_ac97_trigger,
|
||
|
|
.hw_params = au1xpsc_ac97_hw_params,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
EXPORT_SYMBOL_GPL(au1xpsc_ac97_dai);
|
||
|
|
|
||
|
|
static int __init au1xpsc_ac97_init(void)
|
||
|
|
{
|
||
|
|
au1xpsc_ac97_workdata = NULL;
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void __exit au1xpsc_ac97_exit(void)
|
||
|
|
{
|
||
|
|
}
|
||
|
|
|
||
|
|
module_init(au1xpsc_ac97_init);
|
||
|
|
module_exit(au1xpsc_ac97_exit);
|
||
|
|
|
||
|
|
MODULE_LICENSE("GPL");
|
||
|
|
MODULE_DESCRIPTION("Au12x0/Au1550 PSC AC97 ALSA ASoC audio driver");
|
||
|
|
MODULE_AUTHOR("Manuel Lauss <mano@roarinelk.homelinux.net>");
|