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linux_old1/include/linux/spi/sh_msiof.h

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spi: SuperH MSIOF SPI Master driver V2 This patch is V2 of SPI Master support for the SuperH MSIOF. Full duplex, spi mode 0-3, active high cs, 3-wire and lsb first should all be supported, but the driver has so far only been tested with "mmc_spi". The MSIOF hardware comes with 32-bit FIFOs for receive and transmit, and this driver simply breaks the SPI messages into FIFO-sized chunks. The MSIOF hardware manages the pins for clock, receive and transmit (sck/miso/mosi), but the chip select pin is managed by software and must be configured as a regular GPIO pin by the board code. Performance wise there is still room for improvement, but on a Ecovec board with the built-in sh7724 MSIOF0 this driver gets Mini-sd read speeds of about half a megabyte per second. Future work include better clock setup and merging of 8-bit transfers into 32-bit words to reduce interrupt load and improve throughput. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2009-11-26 19:10:05 +08:00
#ifndef __SPI_SH_MSIOF_H__
#define __SPI_SH_MSIOF_H__
struct sh_msiof_spi_info {
int tx_fifo_override;
int rx_fifo_override;
u16 num_chipselect;
spi: sh-msiof: Add DMA support Add DMA support to the MSIOF driver using platform data. As MSIOF DMA is limited to 32-bit words (requiring byte/wordswapping for smaller wordsizes), and the group length is limited to 256 words, DMA is performed on two fixed pages, allocated and mapped at driver initialization time. Performance figures (in Mbps) on r8a7791/koelsch at different SPI clock frequencies for 1024-byte and 4096-byte transfers: 1024 bytes 4096 bytes - 3.25 MHz: PIO 2.1, DMA 2.6 | PIO 2.8, DMA 3.1 - 6.5 MHz: PIO 3.2, DMA 4.4 | PIO 5.0, DMA 5.9 - 13 MHz: PIO 4.2, DMA 6.6 | PIO 8.2, DMA 10.7 - 26 MHz: PIO 5.9, DMA 10.4 | PIO 12.4, DMA 18.4 Note that DMA is only faster than PIO for transfers that exceed the FIFO size (typically 64 words / 256 bytes). Also note that large transfers (larger than the group length for DMA, or larger than the FIFO size for PIO), should use cs-gpio (with the appropriate pinmux setup), as the hardware chipselect will be deasserted in between chunks. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Mark Brown <broonie@linaro.org>
2014-06-30 18:10:24 +08:00
unsigned int dma_tx_id;
unsigned int dma_rx_id;
spi: sh-msiof: Configure MSIOF sync signal timing in device tree The MSIOF controller has DTDL and SYNCDL in SITMDR1 register. So, this patch adds new properties like the following commit: d0fb47a5237d8b9576113568bacfd27892308b62 (spi: fsl-espi: Configure FSL eSPI CSBEF and CSAFT) Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2014-12-19 16:15:53 +08:00
u32 dtdl;
u32 syncdl;
spi: SuperH MSIOF SPI Master driver V2 This patch is V2 of SPI Master support for the SuperH MSIOF. Full duplex, spi mode 0-3, active high cs, 3-wire and lsb first should all be supported, but the driver has so far only been tested with "mmc_spi". The MSIOF hardware comes with 32-bit FIFOs for receive and transmit, and this driver simply breaks the SPI messages into FIFO-sized chunks. The MSIOF hardware manages the pins for clock, receive and transmit (sck/miso/mosi), but the chip select pin is managed by software and must be configured as a regular GPIO pin by the board code. Performance wise there is still room for improvement, but on a Ecovec board with the built-in sh7724 MSIOF0 this driver gets Mini-sd read speeds of about half a megabyte per second. Future work include better clock setup and merging of 8-bit transfers into 32-bit words to reduce interrupt load and improve throughput. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2009-11-26 19:10:05 +08:00
};
#endif /* __SPI_SH_MSIOF_H__ */