18 lines
529 B
C
18 lines
529 B
C
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/*
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* include/asm-sparc64/cache.h
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*/
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#ifndef __ARCH_SPARC64_CACHE_H
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#define __ARCH_SPARC64_CACHE_H
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/* bytes per L1 cache line */
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#define L1_CACHE_SHIFT 5
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#define L1_CACHE_BYTES 32 /* Two 16-byte sub-blocks per line. */
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#define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1))
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#define L1_CACHE_SHIFT_MAX 5 /* largest L1 which this arch supports */
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#define SMP_CACHE_BYTES_SHIFT 6
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#define SMP_CACHE_BYTES (1 << SMP_CACHE_BYTES_SHIFT) /* L2 cache line size. */
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#endif
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