2009-09-07 11:26:23 +08:00
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/*
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* Renesas SuperH DMA Engine support
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*
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* base is drivers/dma/flsdma.c
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*
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2012-05-09 23:09:21 +08:00
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* Copyright (C) 2011-2012 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
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2009-09-07 11:26:23 +08:00
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* Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
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* Copyright (C) 2009 Renesas Solutions, Inc. All rights reserved.
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* Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
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*
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* This is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* - DMA of SuperH does not have Hardware DMA chain mode.
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* - MAX DMA size is 16MB.
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*
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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2013-08-02 22:50:36 +08:00
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#include <linux/of.h>
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#include <linux/of_device.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 16:04:11 +08:00
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#include <linux/slab.h>
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2009-09-07 11:26:23 +08:00
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#include <linux/interrupt.h>
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#include <linux/dmaengine.h>
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#include <linux/delay.h>
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#include <linux/platform_device.h>
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2010-02-12 00:50:18 +08:00
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#include <linux/pm_runtime.h>
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2010-03-19 12:47:10 +08:00
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#include <linux/sh_dma.h>
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2010-12-17 18:16:10 +08:00
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#include <linux/notifier.h>
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#include <linux/kdebug.h>
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#include <linux/spinlock.h>
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#include <linux/rculist.h>
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2012-03-07 06:34:26 +08:00
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2012-07-03 04:30:53 +08:00
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#include "../dmaengine.h"
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2009-09-07 11:26:23 +08:00
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#include "shdma.h"
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2013-08-02 22:50:37 +08:00
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/* DMA register */
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#define SAR 0x00
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#define DAR 0x04
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#define TCR 0x08
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#define CHCR 0x0C
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#define DMAOR 0x40
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#define TEND 0x18 /* USB-DMAC */
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2012-05-09 23:09:21 +08:00
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#define SH_DMAE_DRV_NAME "sh-dma-engine"
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2009-09-07 11:26:23 +08:00
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2010-02-12 00:50:14 +08:00
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/* Default MEMCPY transfer size = 2^2 = 4 bytes */
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#define LOG2_DEFAULT_XFER_SIZE 2
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2012-05-09 23:09:21 +08:00
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#define SH_DMA_SLAVE_NUMBER 256
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#define SH_DMA_TCR_MAX (16 * 1024 * 1024 - 1)
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2009-09-07 11:26:23 +08:00
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2010-12-17 18:16:10 +08:00
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/*
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* Used for write-side mutual exclusion for the global device list,
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2011-04-30 01:09:21 +08:00
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* read-side synchronization by way of RCU, and per-controller data.
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2010-12-17 18:16:10 +08:00
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*/
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static DEFINE_SPINLOCK(sh_dmae_lock);
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static LIST_HEAD(sh_dmae_devices);
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2013-07-10 18:09:47 +08:00
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/*
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* Different DMAC implementations provide different ways to clear DMA channels:
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* (1) none - no CHCLR registers are available
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* (2) one CHCLR register per channel - 0 has to be written to it to clear
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* channel buffers
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* (3) one CHCLR per several channels - 1 has to be written to the bit,
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* corresponding to the specific channel to reset it
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*/
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2013-07-02 23:37:58 +08:00
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static void channel_clear(struct sh_dmae_chan *sh_dc)
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2012-01-04 22:34:17 +08:00
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{
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struct sh_dmae_device *shdev = to_sh_dev(sh_dc);
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2013-07-10 18:09:47 +08:00
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const struct sh_dmae_channel *chan_pdata = shdev->pdata->channel +
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sh_dc->shdma_chan.id;
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u32 val = shdev->pdata->chclr_bitwise ? 1 << chan_pdata->chclr_bit : 0;
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2012-01-04 22:34:17 +08:00
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2013-07-10 18:09:47 +08:00
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__raw_writel(val, shdev->chan_reg + chan_pdata->chclr_offset);
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2012-01-04 22:34:17 +08:00
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}
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2009-12-18 00:41:39 +08:00
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2009-09-07 11:26:23 +08:00
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static void sh_dmae_writel(struct sh_dmae_chan *sh_dc, u32 data, u32 reg)
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{
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2013-07-02 23:46:01 +08:00
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__raw_writel(data, sh_dc->base + reg);
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2009-09-07 11:26:23 +08:00
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}
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static u32 sh_dmae_readl(struct sh_dmae_chan *sh_dc, u32 reg)
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{
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2013-07-02 23:46:01 +08:00
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return __raw_readl(sh_dc->base + reg);
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2010-02-12 00:50:10 +08:00
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}
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static u16 dmaor_read(struct sh_dmae_device *shdev)
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{
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2013-07-02 23:46:01 +08:00
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void __iomem *addr = shdev->chan_reg + DMAOR;
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2011-06-17 16:20:56 +08:00
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if (shdev->pdata->dmaor_is_32bit)
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return __raw_readl(addr);
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else
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return __raw_readw(addr);
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2010-02-12 00:50:10 +08:00
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}
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static void dmaor_write(struct sh_dmae_device *shdev, u16 data)
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{
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2013-07-02 23:46:01 +08:00
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void __iomem *addr = shdev->chan_reg + DMAOR;
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2011-06-17 16:20:56 +08:00
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if (shdev->pdata->dmaor_is_32bit)
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__raw_writel(data, addr);
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else
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__raw_writew(data, addr);
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2009-09-07 11:26:23 +08:00
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}
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2011-06-17 16:20:40 +08:00
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static void chcr_write(struct sh_dmae_chan *sh_dc, u32 data)
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{
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struct sh_dmae_device *shdev = to_sh_dev(sh_dc);
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2013-07-02 23:46:01 +08:00
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__raw_writel(data, sh_dc->base + shdev->chcr_offset);
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2011-06-17 16:20:40 +08:00
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}
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static u32 chcr_read(struct sh_dmae_chan *sh_dc)
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{
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struct sh_dmae_device *shdev = to_sh_dev(sh_dc);
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2013-07-02 23:46:01 +08:00
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return __raw_readl(sh_dc->base + shdev->chcr_offset);
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2009-09-07 11:26:23 +08:00
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}
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/*
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* Reset DMA controller
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*
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* SH7780 has two DMAOR register
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*/
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2010-02-12 00:50:10 +08:00
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static void sh_dmae_ctl_stop(struct sh_dmae_device *shdev)
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2009-09-07 11:26:23 +08:00
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{
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2011-04-30 01:09:21 +08:00
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unsigned short dmaor;
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unsigned long flags;
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spin_lock_irqsave(&sh_dmae_lock, flags);
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2009-09-07 11:26:23 +08:00
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2011-04-30 01:09:21 +08:00
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dmaor = dmaor_read(shdev);
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2010-02-12 00:50:10 +08:00
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dmaor_write(shdev, dmaor & ~(DMAOR_NMIF | DMAOR_AE | DMAOR_DME));
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2011-04-30 01:09:21 +08:00
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spin_unlock_irqrestore(&sh_dmae_lock, flags);
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2009-09-07 11:26:23 +08:00
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}
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2010-02-12 00:50:10 +08:00
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static int sh_dmae_rst(struct sh_dmae_device *shdev)
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2009-09-07 11:26:23 +08:00
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{
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unsigned short dmaor;
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2011-04-30 01:09:21 +08:00
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unsigned long flags;
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2009-09-07 11:26:23 +08:00
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2011-04-30 01:09:21 +08:00
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spin_lock_irqsave(&sh_dmae_lock, flags);
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2009-09-07 11:26:23 +08:00
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2011-04-30 01:09:21 +08:00
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dmaor = dmaor_read(shdev) & ~(DMAOR_NMIF | DMAOR_AE | DMAOR_DME);
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2012-01-04 22:34:17 +08:00
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if (shdev->pdata->chclr_present) {
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int i;
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for (i = 0; i < shdev->pdata->channel_num; i++) {
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struct sh_dmae_chan *sh_chan = shdev->chan[i];
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if (sh_chan)
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2013-07-02 23:37:58 +08:00
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channel_clear(sh_chan);
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2012-01-04 22:34:17 +08:00
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}
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}
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2011-04-30 01:09:21 +08:00
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dmaor_write(shdev, dmaor | shdev->pdata->dmaor_init);
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dmaor = dmaor_read(shdev);
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spin_unlock_irqrestore(&sh_dmae_lock, flags);
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if (dmaor & (DMAOR_AE | DMAOR_NMIF)) {
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2012-05-09 23:09:21 +08:00
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dev_warn(shdev->shdma_dev.dma_dev.dev, "Can't initialize DMAOR.\n");
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2011-04-30 01:09:21 +08:00
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return -EIO;
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2009-09-07 11:26:23 +08:00
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}
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2012-01-04 22:34:17 +08:00
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if (shdev->pdata->dmaor_init & ~dmaor)
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2012-05-09 23:09:21 +08:00
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dev_warn(shdev->shdma_dev.dma_dev.dev,
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2012-01-04 22:34:17 +08:00
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"DMAOR=0x%x hasn't latched the initial value 0x%x.\n",
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dmaor, shdev->pdata->dmaor_init);
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2009-09-07 11:26:23 +08:00
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return 0;
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}
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2010-01-19 15:24:55 +08:00
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static bool dmae_is_busy(struct sh_dmae_chan *sh_chan)
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2009-09-07 11:26:23 +08:00
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{
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2011-06-17 16:20:40 +08:00
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u32 chcr = chcr_read(sh_chan);
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2010-01-19 15:24:55 +08:00
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if ((chcr & (CHCR_DE | CHCR_TE)) == CHCR_DE)
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return true; /* working */
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return false; /* waiting */
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2009-09-07 11:26:23 +08:00
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}
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2010-02-12 00:50:14 +08:00
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static unsigned int calc_xmit_shift(struct sh_dmae_chan *sh_chan, u32 chcr)
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2009-09-07 11:26:23 +08:00
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{
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2011-06-16 13:08:09 +08:00
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struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
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2013-08-02 22:18:09 +08:00
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const struct sh_dmae_pdata *pdata = shdev->pdata;
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2010-02-12 00:50:14 +08:00
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int cnt = ((chcr & pdata->ts_low_mask) >> pdata->ts_low_shift) |
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((chcr & pdata->ts_high_mask) >> pdata->ts_high_shift);
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if (cnt >= pdata->ts_shift_num)
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cnt = 0;
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2010-02-03 22:44:12 +08:00
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2010-02-12 00:50:14 +08:00
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return pdata->ts_shift[cnt];
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}
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static u32 log2size_to_chcr(struct sh_dmae_chan *sh_chan, int l2size)
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{
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2011-06-16 13:08:09 +08:00
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struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
|
2013-08-02 22:18:09 +08:00
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const struct sh_dmae_pdata *pdata = shdev->pdata;
|
2010-02-12 00:50:14 +08:00
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int i;
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for (i = 0; i < pdata->ts_shift_num; i++)
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if (pdata->ts_shift[i] == l2size)
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break;
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if (i == pdata->ts_shift_num)
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i = 0;
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return ((i << pdata->ts_low_shift) & pdata->ts_low_mask) |
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((i << pdata->ts_high_shift) & pdata->ts_high_mask);
|
2009-09-07 11:26:23 +08:00
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}
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|
2009-12-18 00:41:39 +08:00
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static void dmae_set_reg(struct sh_dmae_chan *sh_chan, struct sh_dmae_regs *hw)
|
2009-09-07 11:26:23 +08:00
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{
|
2009-12-18 00:41:39 +08:00
|
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sh_dmae_writel(sh_chan, hw->sar, SAR);
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sh_dmae_writel(sh_chan, hw->dar, DAR);
|
2010-02-03 22:46:41 +08:00
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sh_dmae_writel(sh_chan, hw->tcr >> sh_chan->xmit_shift, TCR);
|
2009-09-07 11:26:23 +08:00
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}
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static void dmae_start(struct sh_dmae_chan *sh_chan)
|
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|
|
{
|
2011-06-17 16:20:51 +08:00
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|
struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
|
2011-06-17 16:20:40 +08:00
|
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|
u32 chcr = chcr_read(sh_chan);
|
2009-09-07 11:26:23 +08:00
|
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|
2011-06-17 16:21:05 +08:00
|
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if (shdev->pdata->needs_tend_set)
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|
|
sh_dmae_writel(sh_chan, 0xFFFFFFFF, TEND);
|
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|
2011-06-17 16:20:51 +08:00
|
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|
chcr |= CHCR_DE | shdev->chcr_ie_bit;
|
2011-06-17 16:20:40 +08:00
|
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|
chcr_write(sh_chan, chcr & ~CHCR_TE);
|
2009-09-07 11:26:23 +08:00
|
|
|
}
|
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|
|
2010-02-03 22:46:41 +08:00
|
|
|
static void dmae_init(struct sh_dmae_chan *sh_chan)
|
|
|
|
{
|
2010-02-12 00:50:14 +08:00
|
|
|
/*
|
|
|
|
* Default configuration for dual address memory-memory transfer.
|
|
|
|
* 0x400 represents auto-request.
|
|
|
|
*/
|
|
|
|
u32 chcr = DM_INC | SM_INC | 0x400 | log2size_to_chcr(sh_chan,
|
|
|
|
LOG2_DEFAULT_XFER_SIZE);
|
|
|
|
sh_chan->xmit_shift = calc_xmit_shift(sh_chan, chcr);
|
2011-06-17 16:20:40 +08:00
|
|
|
chcr_write(sh_chan, chcr);
|
2010-02-03 22:46:41 +08:00
|
|
|
}
|
|
|
|
|
2009-09-07 11:26:23 +08:00
|
|
|
static int dmae_set_chcr(struct sh_dmae_chan *sh_chan, u32 val)
|
|
|
|
{
|
2011-04-30 01:09:21 +08:00
|
|
|
/* If DMA is active, cannot set CHCR. TODO: remove this superfluous check */
|
2010-01-19 15:24:55 +08:00
|
|
|
if (dmae_is_busy(sh_chan))
|
|
|
|
return -EBUSY;
|
2009-09-07 11:26:23 +08:00
|
|
|
|
2010-02-12 00:50:14 +08:00
|
|
|
sh_chan->xmit_shift = calc_xmit_shift(sh_chan, val);
|
2011-06-17 16:20:40 +08:00
|
|
|
chcr_write(sh_chan, val);
|
2010-02-03 22:46:41 +08:00
|
|
|
|
2009-09-07 11:26:23 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int dmae_set_dmars(struct sh_dmae_chan *sh_chan, u16 val)
|
|
|
|
{
|
2011-06-16 13:08:09 +08:00
|
|
|
struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
|
2013-08-02 22:18:09 +08:00
|
|
|
const struct sh_dmae_pdata *pdata = shdev->pdata;
|
2012-05-09 23:09:21 +08:00
|
|
|
const struct sh_dmae_channel *chan_pdata = &pdata->channel[sh_chan->shdma_chan.id];
|
2013-07-02 23:46:01 +08:00
|
|
|
void __iomem *addr = shdev->dmars;
|
2011-06-16 13:08:28 +08:00
|
|
|
unsigned int shift = chan_pdata->dmars_bit;
|
2010-01-19 15:24:55 +08:00
|
|
|
|
|
|
|
if (dmae_is_busy(sh_chan))
|
|
|
|
return -EBUSY;
|
2009-09-07 11:26:23 +08:00
|
|
|
|
2011-06-17 16:21:05 +08:00
|
|
|
if (pdata->no_dmars)
|
|
|
|
return 0;
|
|
|
|
|
2011-05-24 18:31:12 +08:00
|
|
|
/* in the case of a missing DMARS resource use first memory window */
|
|
|
|
if (!addr)
|
2013-07-02 23:46:01 +08:00
|
|
|
addr = shdev->chan_reg;
|
|
|
|
addr += chan_pdata->dmars;
|
2011-05-24 18:31:12 +08:00
|
|
|
|
2010-02-12 00:50:10 +08:00
|
|
|
__raw_writew((__raw_readw(addr) & (0xff00 >> shift)) | (val << shift),
|
|
|
|
addr);
|
2009-09-07 11:26:23 +08:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-05-09 23:09:21 +08:00
|
|
|
static void sh_dmae_start_xfer(struct shdma_chan *schan,
|
|
|
|
struct shdma_desc *sdesc)
|
2009-09-07 11:26:23 +08:00
|
|
|
{
|
2012-05-09 23:09:21 +08:00
|
|
|
struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan,
|
|
|
|
shdma_chan);
|
|
|
|
struct sh_dmae_desc *sh_desc = container_of(sdesc,
|
|
|
|
struct sh_dmae_desc, shdma_desc);
|
|
|
|
dev_dbg(sh_chan->shdma_chan.dev, "Queue #%d to %d: %u@%x -> %x\n",
|
|
|
|
sdesc->async_tx.cookie, sh_chan->shdma_chan.id,
|
|
|
|
sh_desc->hw.tcr, sh_desc->hw.sar, sh_desc->hw.dar);
|
|
|
|
/* Get the ld start address from ld_queue */
|
|
|
|
dmae_set_reg(sh_chan, &sh_desc->hw);
|
|
|
|
dmae_start(sh_chan);
|
2009-09-07 11:26:23 +08:00
|
|
|
}
|
|
|
|
|
2012-05-09 23:09:21 +08:00
|
|
|
static bool sh_dmae_channel_busy(struct shdma_chan *schan)
|
2009-09-07 11:26:23 +08:00
|
|
|
{
|
2012-05-09 23:09:21 +08:00
|
|
|
struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan,
|
|
|
|
shdma_chan);
|
|
|
|
return dmae_is_busy(sh_chan);
|
2009-09-07 11:26:23 +08:00
|
|
|
}
|
|
|
|
|
2012-05-09 23:09:21 +08:00
|
|
|
static void sh_dmae_setup_xfer(struct shdma_chan *schan,
|
2012-07-05 18:29:41 +08:00
|
|
|
int slave_id)
|
2010-02-03 22:46:41 +08:00
|
|
|
{
|
2012-05-09 23:09:21 +08:00
|
|
|
struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan,
|
|
|
|
shdma_chan);
|
2010-02-03 22:46:41 +08:00
|
|
|
|
2012-07-05 18:29:41 +08:00
|
|
|
if (slave_id >= 0) {
|
2012-05-09 23:09:21 +08:00
|
|
|
const struct sh_dmae_slave_config *cfg =
|
2012-07-05 18:29:40 +08:00
|
|
|
sh_chan->config;
|
2010-02-03 22:46:41 +08:00
|
|
|
|
2012-05-09 23:09:21 +08:00
|
|
|
dmae_set_dmars(sh_chan, cfg->mid_rid);
|
|
|
|
dmae_set_chcr(sh_chan, cfg->chcr);
|
2010-01-19 15:24:55 +08:00
|
|
|
} else {
|
2012-05-09 23:09:21 +08:00
|
|
|
dmae_init(sh_chan);
|
2010-01-19 15:24:55 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-06-19 00:16:57 +08:00
|
|
|
/*
|
|
|
|
* Find a slave channel configuration from the contoller list by either a slave
|
|
|
|
* ID in the non-DT case, or by a MID/RID value in the DT case
|
|
|
|
*/
|
2012-05-09 23:09:21 +08:00
|
|
|
static const struct sh_dmae_slave_config *dmae_find_slave(
|
2013-06-19 00:16:57 +08:00
|
|
|
struct sh_dmae_chan *sh_chan, int match)
|
2010-01-19 15:24:55 +08:00
|
|
|
{
|
2012-05-09 23:09:21 +08:00
|
|
|
struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
|
2013-08-02 22:18:09 +08:00
|
|
|
const struct sh_dmae_pdata *pdata = shdev->pdata;
|
2012-05-09 23:09:21 +08:00
|
|
|
const struct sh_dmae_slave_config *cfg;
|
2010-01-19 15:24:55 +08:00
|
|
|
int i;
|
|
|
|
|
2013-06-19 00:16:57 +08:00
|
|
|
if (!sh_chan->shdma_chan.dev->of_node) {
|
|
|
|
if (match >= SH_DMA_SLAVE_NUMBER)
|
|
|
|
return NULL;
|
2010-01-19 15:24:55 +08:00
|
|
|
|
2013-06-19 00:16:57 +08:00
|
|
|
for (i = 0, cfg = pdata->slave; i < pdata->slave_num; i++, cfg++)
|
|
|
|
if (cfg->slave_id == match)
|
|
|
|
return cfg;
|
|
|
|
} else {
|
|
|
|
for (i = 0, cfg = pdata->slave; i < pdata->slave_num; i++, cfg++)
|
|
|
|
if (cfg->mid_rid == match) {
|
2013-08-02 22:50:36 +08:00
|
|
|
sh_chan->shdma_chan.slave_id = i;
|
2013-06-19 00:16:57 +08:00
|
|
|
return cfg;
|
|
|
|
}
|
|
|
|
}
|
2010-01-19 15:24:55 +08:00
|
|
|
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
2012-05-09 23:09:21 +08:00
|
|
|
static int sh_dmae_set_slave(struct shdma_chan *schan,
|
2013-08-02 22:50:36 +08:00
|
|
|
int slave_id, dma_addr_t slave_addr, bool try)
|
2010-01-19 15:24:55 +08:00
|
|
|
{
|
2012-05-09 23:09:21 +08:00
|
|
|
struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan,
|
|
|
|
shdma_chan);
|
2012-07-05 18:29:41 +08:00
|
|
|
const struct sh_dmae_slave_config *cfg = dmae_find_slave(sh_chan, slave_id);
|
2012-05-09 23:09:21 +08:00
|
|
|
if (!cfg)
|
2012-11-28 14:49:47 +08:00
|
|
|
return -ENXIO;
|
2010-02-19 00:30:02 +08:00
|
|
|
|
2013-08-02 22:50:36 +08:00
|
|
|
if (!try) {
|
2012-07-05 18:29:42 +08:00
|
|
|
sh_chan->config = cfg;
|
2013-08-02 22:50:36 +08:00
|
|
|
sh_chan->slave_addr = slave_addr ? : cfg->addr;
|
|
|
|
}
|
2010-03-27 07:44:01 +08:00
|
|
|
|
|
|
|
return 0;
|
2010-02-03 22:46:41 +08:00
|
|
|
}
|
|
|
|
|
2012-05-09 23:09:21 +08:00
|
|
|
static void dmae_halt(struct sh_dmae_chan *sh_chan)
|
2009-09-07 11:26:23 +08:00
|
|
|
{
|
2012-05-09 23:09:21 +08:00
|
|
|
struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
|
|
|
|
u32 chcr = chcr_read(sh_chan);
|
2009-12-18 00:41:39 +08:00
|
|
|
|
2012-05-09 23:09:21 +08:00
|
|
|
chcr &= ~(CHCR_DE | CHCR_TE | shdev->chcr_ie_bit);
|
|
|
|
chcr_write(sh_chan, chcr);
|
2009-12-18 00:41:39 +08:00
|
|
|
}
|
|
|
|
|
2012-05-09 23:09:21 +08:00
|
|
|
static int sh_dmae_desc_setup(struct shdma_chan *schan,
|
|
|
|
struct shdma_desc *sdesc,
|
|
|
|
dma_addr_t src, dma_addr_t dst, size_t *len)
|
2009-12-18 00:41:39 +08:00
|
|
|
{
|
2012-05-09 23:09:21 +08:00
|
|
|
struct sh_dmae_desc *sh_desc = container_of(sdesc,
|
|
|
|
struct sh_dmae_desc, shdma_desc);
|
2009-09-07 11:26:23 +08:00
|
|
|
|
2012-05-09 23:09:21 +08:00
|
|
|
if (*len > schan->max_xfer_len)
|
|
|
|
*len = schan->max_xfer_len;
|
2009-09-07 11:26:23 +08:00
|
|
|
|
2012-05-09 23:09:21 +08:00
|
|
|
sh_desc->hw.sar = src;
|
|
|
|
sh_desc->hw.dar = dst;
|
|
|
|
sh_desc->hw.tcr = *len;
|
2009-09-07 11:26:23 +08:00
|
|
|
|
2012-05-09 23:09:21 +08:00
|
|
|
return 0;
|
2009-09-07 11:26:23 +08:00
|
|
|
}
|
|
|
|
|
2012-05-09 23:09:21 +08:00
|
|
|
static void sh_dmae_halt(struct shdma_chan *schan)
|
2009-09-07 11:26:23 +08:00
|
|
|
{
|
2012-05-09 23:09:21 +08:00
|
|
|
struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan,
|
|
|
|
shdma_chan);
|
|
|
|
dmae_halt(sh_chan);
|
2009-09-07 11:26:23 +08:00
|
|
|
}
|
|
|
|
|
2012-05-09 23:09:21 +08:00
|
|
|
static bool sh_dmae_chan_irq(struct shdma_chan *schan, int irq)
|
2009-09-07 11:26:23 +08:00
|
|
|
{
|
2012-05-09 23:09:21 +08:00
|
|
|
struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan,
|
|
|
|
shdma_chan);
|
2009-09-07 11:26:23 +08:00
|
|
|
|
2012-05-09 23:09:21 +08:00
|
|
|
if (!(chcr_read(sh_chan) & CHCR_TE))
|
|
|
|
return false;
|
2009-09-07 11:26:23 +08:00
|
|
|
|
2012-05-09 23:09:21 +08:00
|
|
|
/* DMA stop */
|
|
|
|
dmae_halt(sh_chan);
|
2011-04-30 01:09:21 +08:00
|
|
|
|
2012-05-09 23:09:21 +08:00
|
|
|
return true;
|
2009-09-07 11:26:23 +08:00
|
|
|
}
|
|
|
|
|
2012-07-31 03:28:27 +08:00
|
|
|
static size_t sh_dmae_get_partial(struct shdma_chan *schan,
|
|
|
|
struct shdma_desc *sdesc)
|
|
|
|
{
|
|
|
|
struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan,
|
|
|
|
shdma_chan);
|
|
|
|
struct sh_dmae_desc *sh_desc = container_of(sdesc,
|
|
|
|
struct sh_dmae_desc, shdma_desc);
|
2013-07-24 14:12:41 +08:00
|
|
|
return sh_desc->hw.tcr -
|
|
|
|
(sh_dmae_readl(sh_chan, TCR) << sh_chan->xmit_shift);
|
2012-07-31 03:28:27 +08:00
|
|
|
}
|
|
|
|
|
2011-04-30 01:09:21 +08:00
|
|
|
/* Called from error IRQ or NMI */
|
|
|
|
static bool sh_dmae_reset(struct sh_dmae_device *shdev)
|
2009-09-07 11:26:23 +08:00
|
|
|
{
|
2012-05-09 23:09:21 +08:00
|
|
|
bool ret;
|
2009-09-07 11:26:23 +08:00
|
|
|
|
2010-02-12 00:50:05 +08:00
|
|
|
/* halt the dma controller */
|
2010-02-12 00:50:10 +08:00
|
|
|
sh_dmae_ctl_stop(shdev);
|
2010-02-12 00:50:05 +08:00
|
|
|
|
|
|
|
/* We cannot detect, which channel caused the error, have to reset all */
|
2012-05-09 23:09:21 +08:00
|
|
|
ret = shdma_reset(&shdev->shdma_dev);
|
2010-12-17 18:16:10 +08:00
|
|
|
|
2010-02-12 00:50:10 +08:00
|
|
|
sh_dmae_rst(shdev);
|
2010-02-12 00:50:05 +08:00
|
|
|
|
2012-05-09 23:09:21 +08:00
|
|
|
return ret;
|
2010-12-17 18:16:10 +08:00
|
|
|
}
|
|
|
|
|
2013-12-11 20:43:05 +08:00
|
|
|
#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARM)
|
2010-12-17 18:16:10 +08:00
|
|
|
static irqreturn_t sh_dmae_err(int irq, void *data)
|
|
|
|
{
|
2011-02-09 15:46:47 +08:00
|
|
|
struct sh_dmae_device *shdev = data;
|
|
|
|
|
2011-04-30 01:09:21 +08:00
|
|
|
if (!(dmaor_read(shdev) & DMAOR_AE))
|
2011-02-09 15:46:47 +08:00
|
|
|
return IRQ_NONE;
|
2011-04-30 01:09:21 +08:00
|
|
|
|
2012-05-09 23:09:21 +08:00
|
|
|
sh_dmae_reset(shdev);
|
2011-04-30 01:09:21 +08:00
|
|
|
return IRQ_HANDLED;
|
2009-09-07 11:26:23 +08:00
|
|
|
}
|
2013-12-11 20:43:05 +08:00
|
|
|
#endif
|
2009-09-07 11:26:23 +08:00
|
|
|
|
2012-05-09 23:09:21 +08:00
|
|
|
static bool sh_dmae_desc_completed(struct shdma_chan *schan,
|
|
|
|
struct shdma_desc *sdesc)
|
2009-09-07 11:26:23 +08:00
|
|
|
{
|
2012-05-09 23:09:21 +08:00
|
|
|
struct sh_dmae_chan *sh_chan = container_of(schan,
|
|
|
|
struct sh_dmae_chan, shdma_chan);
|
|
|
|
struct sh_dmae_desc *sh_desc = container_of(sdesc,
|
|
|
|
struct sh_dmae_desc, shdma_desc);
|
2009-09-07 11:26:23 +08:00
|
|
|
u32 sar_buf = sh_dmae_readl(sh_chan, SAR);
|
2010-02-03 22:46:41 +08:00
|
|
|
u32 dar_buf = sh_dmae_readl(sh_chan, DAR);
|
2009-12-11 01:35:07 +08:00
|
|
|
|
2012-05-09 23:09:21 +08:00
|
|
|
return (sdesc->direction == DMA_DEV_TO_MEM &&
|
|
|
|
(sh_desc->hw.dar + sh_desc->hw.tcr) == dar_buf) ||
|
|
|
|
(sdesc->direction != DMA_DEV_TO_MEM &&
|
|
|
|
(sh_desc->hw.sar + sh_desc->hw.tcr) == sar_buf);
|
2009-09-07 11:26:23 +08:00
|
|
|
}
|
|
|
|
|
2010-12-17 18:16:10 +08:00
|
|
|
static bool sh_dmae_nmi_notify(struct sh_dmae_device *shdev)
|
|
|
|
{
|
|
|
|
/* Fast path out if NMIF is not asserted for this controller */
|
|
|
|
if ((dmaor_read(shdev) & DMAOR_NMIF) == 0)
|
|
|
|
return false;
|
|
|
|
|
2011-04-30 01:09:21 +08:00
|
|
|
return sh_dmae_reset(shdev);
|
2010-12-17 18:16:10 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static int sh_dmae_nmi_handler(struct notifier_block *self,
|
|
|
|
unsigned long cmd, void *data)
|
|
|
|
{
|
|
|
|
struct sh_dmae_device *shdev;
|
|
|
|
int ret = NOTIFY_DONE;
|
|
|
|
bool triggered;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Only concern ourselves with NMI events.
|
|
|
|
*
|
|
|
|
* Normally we would check the die chain value, but as this needs
|
|
|
|
* to be architecture independent, check for NMI context instead.
|
|
|
|
*/
|
|
|
|
if (!in_nmi())
|
|
|
|
return NOTIFY_DONE;
|
|
|
|
|
|
|
|
rcu_read_lock();
|
|
|
|
list_for_each_entry_rcu(shdev, &sh_dmae_devices, node) {
|
|
|
|
/*
|
|
|
|
* Only stop if one of the controllers has NMIF asserted,
|
|
|
|
* we do not want to interfere with regular address error
|
|
|
|
* handling or NMI events that don't concern the DMACs.
|
|
|
|
*/
|
|
|
|
triggered = sh_dmae_nmi_notify(shdev);
|
|
|
|
if (triggered == true)
|
|
|
|
ret = NOTIFY_OK;
|
|
|
|
}
|
|
|
|
rcu_read_unlock();
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct notifier_block sh_dmae_nmi_notifier __read_mostly = {
|
|
|
|
.notifier_call = sh_dmae_nmi_handler,
|
|
|
|
|
|
|
|
/* Run before NMI debug handler and KGDB */
|
|
|
|
.priority = 1,
|
|
|
|
};
|
|
|
|
|
2012-11-20 02:22:55 +08:00
|
|
|
static int sh_dmae_chan_probe(struct sh_dmae_device *shdev, int id,
|
2010-02-12 00:50:10 +08:00
|
|
|
int irq, unsigned long flags)
|
2009-09-07 11:26:23 +08:00
|
|
|
{
|
2010-04-21 23:36:49 +08:00
|
|
|
const struct sh_dmae_channel *chan_pdata = &shdev->pdata->channel[id];
|
2012-05-09 23:09:21 +08:00
|
|
|
struct shdma_dev *sdev = &shdev->shdma_dev;
|
|
|
|
struct platform_device *pdev = to_platform_device(sdev->dma_dev.dev);
|
|
|
|
struct sh_dmae_chan *sh_chan;
|
|
|
|
struct shdma_chan *schan;
|
|
|
|
int err;
|
2009-09-07 11:26:23 +08:00
|
|
|
|
2013-07-02 23:45:55 +08:00
|
|
|
sh_chan = devm_kzalloc(sdev->dma_dev.dev, sizeof(struct sh_dmae_chan),
|
|
|
|
GFP_KERNEL);
|
2012-05-09 23:09:21 +08:00
|
|
|
if (!sh_chan) {
|
|
|
|
dev_err(sdev->dma_dev.dev,
|
2009-12-11 01:35:07 +08:00
|
|
|
"No free memory for allocating dma channels!\n");
|
2009-09-07 11:26:23 +08:00
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
2012-05-09 23:09:21 +08:00
|
|
|
schan = &sh_chan->shdma_chan;
|
|
|
|
schan->max_xfer_len = SH_DMA_TCR_MAX + 1;
|
2010-02-12 00:50:14 +08:00
|
|
|
|
2012-05-09 23:09:21 +08:00
|
|
|
shdma_chan_probe(sdev, schan, id);
|
2009-09-07 11:26:23 +08:00
|
|
|
|
2013-07-02 23:46:01 +08:00
|
|
|
sh_chan->base = shdev->chan_reg + chan_pdata->offset;
|
2009-09-07 11:26:23 +08:00
|
|
|
|
2012-05-09 23:09:21 +08:00
|
|
|
/* set up channel irq */
|
2010-02-12 00:50:10 +08:00
|
|
|
if (pdev->id >= 0)
|
2012-05-09 23:09:21 +08:00
|
|
|
snprintf(sh_chan->dev_id, sizeof(sh_chan->dev_id),
|
|
|
|
"sh-dmae%d.%d", pdev->id, id);
|
2010-02-12 00:50:10 +08:00
|
|
|
else
|
2012-05-09 23:09:21 +08:00
|
|
|
snprintf(sh_chan->dev_id, sizeof(sh_chan->dev_id),
|
|
|
|
"sh-dma%d", id);
|
2009-09-07 11:26:23 +08:00
|
|
|
|
2012-05-09 23:09:21 +08:00
|
|
|
err = shdma_request_irq(schan, irq, flags, sh_chan->dev_id);
|
2009-09-07 11:26:23 +08:00
|
|
|
if (err) {
|
2012-05-09 23:09:21 +08:00
|
|
|
dev_err(sdev->dma_dev.dev,
|
|
|
|
"DMA channel %d request_irq error %d\n",
|
|
|
|
id, err);
|
2009-09-07 11:26:23 +08:00
|
|
|
goto err_no_irq;
|
|
|
|
}
|
|
|
|
|
2012-05-09 23:09:21 +08:00
|
|
|
shdev->chan[id] = sh_chan;
|
2009-09-07 11:26:23 +08:00
|
|
|
return 0;
|
|
|
|
|
|
|
|
err_no_irq:
|
|
|
|
/* remove from dmaengine device node */
|
2012-05-09 23:09:21 +08:00
|
|
|
shdma_chan_remove(schan);
|
2009-09-07 11:26:23 +08:00
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void sh_dmae_chan_remove(struct sh_dmae_device *shdev)
|
|
|
|
{
|
2012-05-09 23:09:21 +08:00
|
|
|
struct dma_device *dma_dev = &shdev->shdma_dev.dma_dev;
|
|
|
|
struct shdma_chan *schan;
|
2009-09-07 11:26:23 +08:00
|
|
|
int i;
|
|
|
|
|
2012-05-09 23:09:21 +08:00
|
|
|
shdma_for_each_chan(schan, &shdev->shdma_dev, i) {
|
|
|
|
BUG_ON(!schan);
|
2010-02-12 00:50:10 +08:00
|
|
|
|
2012-05-09 23:09:21 +08:00
|
|
|
shdma_chan_remove(schan);
|
|
|
|
}
|
|
|
|
dma_dev->chancnt = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void sh_dmae_shutdown(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct sh_dmae_device *shdev = platform_get_drvdata(pdev);
|
|
|
|
sh_dmae_ctl_stop(shdev);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int sh_dmae_runtime_suspend(struct device *dev)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int sh_dmae_runtime_resume(struct device *dev)
|
|
|
|
{
|
|
|
|
struct sh_dmae_device *shdev = dev_get_drvdata(dev);
|
|
|
|
|
|
|
|
return sh_dmae_rst(shdev);
|
|
|
|
}
|
|
|
|
|
|
|
|
#ifdef CONFIG_PM
|
|
|
|
static int sh_dmae_suspend(struct device *dev)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int sh_dmae_resume(struct device *dev)
|
|
|
|
{
|
|
|
|
struct sh_dmae_device *shdev = dev_get_drvdata(dev);
|
|
|
|
int i, ret;
|
|
|
|
|
|
|
|
ret = sh_dmae_rst(shdev);
|
|
|
|
if (ret < 0)
|
|
|
|
dev_err(dev, "Failed to reset!\n");
|
|
|
|
|
|
|
|
for (i = 0; i < shdev->pdata->channel_num; i++) {
|
|
|
|
struct sh_dmae_chan *sh_chan = shdev->chan[i];
|
|
|
|
|
|
|
|
if (!sh_chan->shdma_chan.desc_num)
|
|
|
|
continue;
|
|
|
|
|
2012-07-05 18:29:41 +08:00
|
|
|
if (sh_chan->shdma_chan.slave_id >= 0) {
|
2012-07-05 18:29:40 +08:00
|
|
|
const struct sh_dmae_slave_config *cfg = sh_chan->config;
|
2012-05-09 23:09:21 +08:00
|
|
|
dmae_set_dmars(sh_chan, cfg->mid_rid);
|
|
|
|
dmae_set_chcr(sh_chan, cfg->chcr);
|
|
|
|
} else {
|
|
|
|
dmae_init(sh_chan);
|
2009-09-07 11:26:23 +08:00
|
|
|
}
|
|
|
|
}
|
2012-05-09 23:09:21 +08:00
|
|
|
|
|
|
|
return 0;
|
2009-09-07 11:26:23 +08:00
|
|
|
}
|
2012-05-09 23:09:21 +08:00
|
|
|
#else
|
|
|
|
#define sh_dmae_suspend NULL
|
|
|
|
#define sh_dmae_resume NULL
|
|
|
|
#endif
|
2009-09-07 11:26:23 +08:00
|
|
|
|
2013-12-11 20:43:06 +08:00
|
|
|
static const struct dev_pm_ops sh_dmae_pm = {
|
2012-05-09 23:09:21 +08:00
|
|
|
.suspend = sh_dmae_suspend,
|
|
|
|
.resume = sh_dmae_resume,
|
|
|
|
.runtime_suspend = sh_dmae_runtime_suspend,
|
|
|
|
.runtime_resume = sh_dmae_runtime_resume,
|
|
|
|
};
|
|
|
|
|
|
|
|
static dma_addr_t sh_dmae_slave_addr(struct shdma_chan *schan)
|
|
|
|
{
|
2012-07-05 18:29:40 +08:00
|
|
|
struct sh_dmae_chan *sh_chan = container_of(schan,
|
|
|
|
struct sh_dmae_chan, shdma_chan);
|
2012-05-09 23:09:21 +08:00
|
|
|
|
|
|
|
/*
|
2012-07-05 18:29:40 +08:00
|
|
|
* Implicit BUG_ON(!sh_chan->config)
|
|
|
|
* This is an exclusive slave DMA operation, may only be called after a
|
|
|
|
* successful slave configuration.
|
2012-05-09 23:09:21 +08:00
|
|
|
*/
|
2013-08-02 22:50:36 +08:00
|
|
|
return sh_chan->slave_addr;
|
2012-05-09 23:09:21 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static struct shdma_desc *sh_dmae_embedded_desc(void *buf, int i)
|
|
|
|
{
|
|
|
|
return &((struct sh_dmae_desc *)buf)[i].shdma_desc;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct shdma_ops sh_dmae_shdma_ops = {
|
|
|
|
.desc_completed = sh_dmae_desc_completed,
|
|
|
|
.halt_channel = sh_dmae_halt,
|
|
|
|
.channel_busy = sh_dmae_channel_busy,
|
|
|
|
.slave_addr = sh_dmae_slave_addr,
|
|
|
|
.desc_setup = sh_dmae_desc_setup,
|
|
|
|
.set_slave = sh_dmae_set_slave,
|
|
|
|
.setup_xfer = sh_dmae_setup_xfer,
|
|
|
|
.start_xfer = sh_dmae_start_xfer,
|
|
|
|
.embedded_desc = sh_dmae_embedded_desc,
|
|
|
|
.chan_irq = sh_dmae_chan_irq,
|
2012-07-31 03:28:27 +08:00
|
|
|
.get_partial = sh_dmae_get_partial,
|
2012-05-09 23:09:21 +08:00
|
|
|
};
|
|
|
|
|
2013-08-02 22:50:36 +08:00
|
|
|
static const struct of_device_id sh_dmae_of_match[] = {
|
2013-08-02 22:50:39 +08:00
|
|
|
{.compatible = "renesas,shdma-r8a73a4", .data = r8a73a4_shdma_devid,},
|
2013-08-02 22:50:36 +08:00
|
|
|
{}
|
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, sh_dmae_of_match);
|
|
|
|
|
2012-11-20 02:22:55 +08:00
|
|
|
static int sh_dmae_probe(struct platform_device *pdev)
|
2009-09-07 11:26:23 +08:00
|
|
|
{
|
2013-08-02 22:50:36 +08:00
|
|
|
const struct sh_dmae_pdata *pdata;
|
2013-12-11 20:43:05 +08:00
|
|
|
unsigned long chan_flag[SH_DMAE_MAX_CHANNELS] = {};
|
|
|
|
int chan_irq[SH_DMAE_MAX_CHANNELS];
|
|
|
|
#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARM)
|
|
|
|
unsigned long irqflags = 0;
|
|
|
|
int errirq;
|
|
|
|
#endif
|
2011-05-24 18:31:20 +08:00
|
|
|
int err, i, irq_cnt = 0, irqres = 0, irq_cap = 0;
|
2009-09-07 11:26:23 +08:00
|
|
|
struct sh_dmae_device *shdev;
|
2012-05-09 23:09:21 +08:00
|
|
|
struct dma_device *dma_dev;
|
2010-02-12 00:50:10 +08:00
|
|
|
struct resource *chan, *dmars, *errirq_res, *chanirq_res;
|
2009-09-07 11:26:23 +08:00
|
|
|
|
2013-08-02 22:50:36 +08:00
|
|
|
if (pdev->dev.of_node)
|
|
|
|
pdata = of_match_device(sh_dmae_of_match, &pdev->dev)->data;
|
|
|
|
else
|
2013-09-02 20:12:35 +08:00
|
|
|
pdata = dev_get_platdata(&pdev->dev);
|
2013-08-02 22:50:36 +08:00
|
|
|
|
2009-11-23 03:10:10 +08:00
|
|
|
/* get platform data */
|
2010-02-12 00:50:10 +08:00
|
|
|
if (!pdata || !pdata->channel_num)
|
2009-11-23 03:10:10 +08:00
|
|
|
return -ENODEV;
|
|
|
|
|
2010-02-12 00:50:10 +08:00
|
|
|
chan = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
2011-05-24 18:31:12 +08:00
|
|
|
/* DMARS area is optional */
|
2010-02-12 00:50:10 +08:00
|
|
|
dmars = platform_get_resource(pdev, IORESOURCE_MEM, 1);
|
|
|
|
/*
|
|
|
|
* IRQ resources:
|
|
|
|
* 1. there always must be at least one IRQ IO-resource. On SH4 it is
|
|
|
|
* the error IRQ, in which case it is the only IRQ in this resource:
|
|
|
|
* start == end. If it is the only IRQ resource, all channels also
|
|
|
|
* use the same IRQ.
|
|
|
|
* 2. DMA channel IRQ resources can be specified one per resource or in
|
|
|
|
* ranges (start != end)
|
|
|
|
* 3. iff all events (channels and, optionally, error) on this
|
|
|
|
* controller use the same IRQ, only one IRQ resource can be
|
|
|
|
* specified, otherwise there must be one IRQ per channel, even if
|
|
|
|
* some of them are equal
|
|
|
|
* 4. if all IRQs on this controller are equal or if some specific IRQs
|
|
|
|
* specify IORESOURCE_IRQ_SHAREABLE in their resources, they will be
|
|
|
|
* requested with the IRQF_SHARED flag
|
|
|
|
*/
|
|
|
|
errirq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
|
|
|
|
if (!chan || !errirq_res)
|
|
|
|
return -ENODEV;
|
|
|
|
|
2013-07-02 23:45:55 +08:00
|
|
|
shdev = devm_kzalloc(&pdev->dev, sizeof(struct sh_dmae_device),
|
|
|
|
GFP_KERNEL);
|
2009-09-07 11:26:23 +08:00
|
|
|
if (!shdev) {
|
2010-02-12 00:50:10 +08:00
|
|
|
dev_err(&pdev->dev, "Not enough memory\n");
|
2013-07-02 23:45:55 +08:00
|
|
|
return -ENOMEM;
|
2010-02-12 00:50:10 +08:00
|
|
|
}
|
|
|
|
|
2012-05-09 23:09:21 +08:00
|
|
|
dma_dev = &shdev->shdma_dev.dma_dev;
|
|
|
|
|
2013-07-02 23:45:55 +08:00
|
|
|
shdev->chan_reg = devm_ioremap_resource(&pdev->dev, chan);
|
|
|
|
if (IS_ERR(shdev->chan_reg))
|
|
|
|
return PTR_ERR(shdev->chan_reg);
|
2010-02-12 00:50:10 +08:00
|
|
|
if (dmars) {
|
2013-07-02 23:45:55 +08:00
|
|
|
shdev->dmars = devm_ioremap_resource(&pdev->dev, dmars);
|
|
|
|
if (IS_ERR(shdev->dmars))
|
|
|
|
return PTR_ERR(shdev->dmars);
|
2009-09-07 11:26:23 +08:00
|
|
|
}
|
|
|
|
|
2012-05-09 23:09:21 +08:00
|
|
|
if (!pdata->slave_only)
|
|
|
|
dma_cap_set(DMA_MEMCPY, dma_dev->cap_mask);
|
|
|
|
if (pdata->slave && pdata->slave_num)
|
|
|
|
dma_cap_set(DMA_SLAVE, dma_dev->cap_mask);
|
|
|
|
|
|
|
|
/* Default transfer size of 32 bytes requires 32-byte alignment */
|
|
|
|
dma_dev->copy_align = LOG2_DEFAULT_XFER_SIZE;
|
|
|
|
|
|
|
|
shdev->shdma_dev.ops = &sh_dmae_shdma_ops;
|
|
|
|
shdev->shdma_dev.desc_size = sizeof(struct sh_dmae_desc);
|
|
|
|
err = shdma_init(&pdev->dev, &shdev->shdma_dev,
|
|
|
|
pdata->channel_num);
|
|
|
|
if (err < 0)
|
|
|
|
goto eshdma;
|
|
|
|
|
2009-09-07 11:26:23 +08:00
|
|
|
/* platform data */
|
2013-06-06 23:37:13 +08:00
|
|
|
shdev->pdata = pdata;
|
2009-09-07 11:26:23 +08:00
|
|
|
|
2011-06-17 16:20:40 +08:00
|
|
|
if (pdata->chcr_offset)
|
|
|
|
shdev->chcr_offset = pdata->chcr_offset;
|
|
|
|
else
|
|
|
|
shdev->chcr_offset = CHCR;
|
|
|
|
|
2011-06-17 16:20:51 +08:00
|
|
|
if (pdata->chcr_ie_bit)
|
|
|
|
shdev->chcr_ie_bit = pdata->chcr_ie_bit;
|
|
|
|
else
|
|
|
|
shdev->chcr_ie_bit = CHCR_IE;
|
|
|
|
|
2011-05-31 14:53:03 +08:00
|
|
|
platform_set_drvdata(pdev, shdev);
|
|
|
|
|
2010-02-12 00:50:18 +08:00
|
|
|
pm_runtime_enable(&pdev->dev);
|
2012-05-09 23:09:21 +08:00
|
|
|
err = pm_runtime_get_sync(&pdev->dev);
|
|
|
|
if (err < 0)
|
|
|
|
dev_err(&pdev->dev, "%s(): GET = %d\n", __func__, err);
|
2010-02-12 00:50:18 +08:00
|
|
|
|
2011-05-02 15:59:02 +08:00
|
|
|
spin_lock_irq(&sh_dmae_lock);
|
2010-12-17 18:16:10 +08:00
|
|
|
list_add_tail_rcu(&shdev->node, &sh_dmae_devices);
|
2011-05-02 15:59:02 +08:00
|
|
|
spin_unlock_irq(&sh_dmae_lock);
|
2010-12-17 18:16:10 +08:00
|
|
|
|
2011-04-30 01:09:21 +08:00
|
|
|
/* reset dma controller - only needed as a test */
|
2010-02-12 00:50:10 +08:00
|
|
|
err = sh_dmae_rst(shdev);
|
2009-09-07 11:26:23 +08:00
|
|
|
if (err)
|
|
|
|
goto rst_err;
|
|
|
|
|
2010-03-19 12:47:19 +08:00
|
|
|
#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
|
2010-02-12 00:50:10 +08:00
|
|
|
chanirq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
|
|
|
|
|
|
|
|
if (!chanirq_res)
|
|
|
|
chanirq_res = errirq_res;
|
|
|
|
else
|
|
|
|
irqres++;
|
|
|
|
|
|
|
|
if (chanirq_res == errirq_res ||
|
|
|
|
(errirq_res->flags & IORESOURCE_BITS) == IORESOURCE_IRQ_SHAREABLE)
|
2009-09-07 11:26:23 +08:00
|
|
|
irqflags = IRQF_SHARED;
|
2010-02-12 00:50:10 +08:00
|
|
|
|
|
|
|
errirq = errirq_res->start;
|
|
|
|
|
2013-07-02 23:45:55 +08:00
|
|
|
err = devm_request_irq(&pdev->dev, errirq, sh_dmae_err, irqflags,
|
|
|
|
"DMAC Address Error", shdev);
|
2010-02-12 00:50:10 +08:00
|
|
|
if (err) {
|
|
|
|
dev_err(&pdev->dev,
|
|
|
|
"DMA failed requesting irq #%d, error %d\n",
|
|
|
|
errirq, err);
|
|
|
|
goto eirq_err;
|
2009-09-07 11:26:23 +08:00
|
|
|
}
|
|
|
|
|
2010-02-12 00:50:10 +08:00
|
|
|
#else
|
|
|
|
chanirq_res = errirq_res;
|
2010-03-19 12:47:19 +08:00
|
|
|
#endif /* CONFIG_CPU_SH4 || CONFIG_ARCH_SHMOBILE */
|
2010-02-12 00:50:10 +08:00
|
|
|
|
|
|
|
if (chanirq_res->start == chanirq_res->end &&
|
|
|
|
!platform_get_resource(pdev, IORESOURCE_IRQ, 1)) {
|
|
|
|
/* Special case - all multiplexed */
|
|
|
|
for (; irq_cnt < pdata->channel_num; irq_cnt++) {
|
2012-05-09 23:09:21 +08:00
|
|
|
if (irq_cnt < SH_DMAE_MAX_CHANNELS) {
|
2011-05-24 18:31:20 +08:00
|
|
|
chan_irq[irq_cnt] = chanirq_res->start;
|
|
|
|
chan_flag[irq_cnt] = IRQF_SHARED;
|
|
|
|
} else {
|
|
|
|
irq_cap = 1;
|
|
|
|
break;
|
|
|
|
}
|
2009-09-07 11:26:23 +08:00
|
|
|
}
|
2010-02-12 00:50:10 +08:00
|
|
|
} else {
|
|
|
|
do {
|
|
|
|
for (i = chanirq_res->start; i <= chanirq_res->end; i++) {
|
2012-05-09 23:09:21 +08:00
|
|
|
if (irq_cnt >= SH_DMAE_MAX_CHANNELS) {
|
2011-06-09 14:35:08 +08:00
|
|
|
irq_cap = 1;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2010-02-12 00:50:10 +08:00
|
|
|
if ((errirq_res->flags & IORESOURCE_BITS) ==
|
|
|
|
IORESOURCE_IRQ_SHAREABLE)
|
|
|
|
chan_flag[irq_cnt] = IRQF_SHARED;
|
|
|
|
else
|
2013-10-13 13:10:51 +08:00
|
|
|
chan_flag[irq_cnt] = 0;
|
2010-02-12 00:50:10 +08:00
|
|
|
dev_dbg(&pdev->dev,
|
|
|
|
"Found IRQ %d for channel %d\n",
|
|
|
|
i, irq_cnt);
|
|
|
|
chan_irq[irq_cnt++] = i;
|
2011-05-24 18:31:20 +08:00
|
|
|
}
|
|
|
|
|
2012-05-09 23:09:21 +08:00
|
|
|
if (irq_cnt >= SH_DMAE_MAX_CHANNELS)
|
2011-05-24 18:31:20 +08:00
|
|
|
break;
|
2011-06-09 14:35:08 +08:00
|
|
|
|
2010-02-12 00:50:10 +08:00
|
|
|
chanirq_res = platform_get_resource(pdev,
|
|
|
|
IORESOURCE_IRQ, ++irqres);
|
|
|
|
} while (irq_cnt < pdata->channel_num && chanirq_res);
|
2009-09-07 11:26:23 +08:00
|
|
|
}
|
2010-02-12 00:50:10 +08:00
|
|
|
|
2009-09-07 11:26:23 +08:00
|
|
|
/* Create DMA Channel */
|
2011-05-24 18:31:20 +08:00
|
|
|
for (i = 0; i < irq_cnt; i++) {
|
2010-02-12 00:50:10 +08:00
|
|
|
err = sh_dmae_chan_probe(shdev, i, chan_irq[i], chan_flag[i]);
|
2009-09-07 11:26:23 +08:00
|
|
|
if (err)
|
|
|
|
goto chan_probe_err;
|
|
|
|
}
|
|
|
|
|
2011-05-24 18:31:20 +08:00
|
|
|
if (irq_cap)
|
|
|
|
dev_notice(&pdev->dev, "Attempting to register %d DMA "
|
|
|
|
"channels when a maximum of %d are supported.\n",
|
2012-05-09 23:09:21 +08:00
|
|
|
pdata->channel_num, SH_DMAE_MAX_CHANNELS);
|
2011-05-24 18:31:20 +08:00
|
|
|
|
2010-02-12 00:50:18 +08:00
|
|
|
pm_runtime_put(&pdev->dev);
|
|
|
|
|
2012-05-09 23:09:21 +08:00
|
|
|
err = dma_async_device_register(&shdev->shdma_dev.dma_dev);
|
|
|
|
if (err < 0)
|
|
|
|
goto edmadevreg;
|
2009-09-07 11:26:23 +08:00
|
|
|
|
|
|
|
return err;
|
|
|
|
|
2012-05-09 23:09:21 +08:00
|
|
|
edmadevreg:
|
|
|
|
pm_runtime_get(&pdev->dev);
|
|
|
|
|
2009-09-07 11:26:23 +08:00
|
|
|
chan_probe_err:
|
|
|
|
sh_dmae_chan_remove(shdev);
|
2011-05-24 18:31:20 +08:00
|
|
|
|
2010-03-19 12:47:19 +08:00
|
|
|
#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
|
2009-09-07 11:26:23 +08:00
|
|
|
eirq_err:
|
2010-02-12 00:50:10 +08:00
|
|
|
#endif
|
2009-09-07 11:26:23 +08:00
|
|
|
rst_err:
|
2011-05-02 15:59:02 +08:00
|
|
|
spin_lock_irq(&sh_dmae_lock);
|
2010-12-17 18:16:10 +08:00
|
|
|
list_del_rcu(&shdev->node);
|
2011-05-02 15:59:02 +08:00
|
|
|
spin_unlock_irq(&sh_dmae_lock);
|
2010-12-17 18:16:10 +08:00
|
|
|
|
2010-02-12 00:50:18 +08:00
|
|
|
pm_runtime_put(&pdev->dev);
|
2011-04-30 01:09:25 +08:00
|
|
|
pm_runtime_disable(&pdev->dev);
|
|
|
|
|
2012-05-09 23:09:21 +08:00
|
|
|
shdma_cleanup(&shdev->shdma_dev);
|
|
|
|
eshdma:
|
2011-05-02 15:59:02 +08:00
|
|
|
synchronize_rcu();
|
2009-09-07 11:26:23 +08:00
|
|
|
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
2012-12-22 07:09:59 +08:00
|
|
|
static int sh_dmae_remove(struct platform_device *pdev)
|
2009-09-07 11:26:23 +08:00
|
|
|
{
|
|
|
|
struct sh_dmae_device *shdev = platform_get_drvdata(pdev);
|
2012-05-09 23:09:21 +08:00
|
|
|
struct dma_device *dma_dev = &shdev->shdma_dev.dma_dev;
|
2009-09-07 11:26:23 +08:00
|
|
|
|
2012-05-09 23:09:21 +08:00
|
|
|
dma_async_device_unregister(dma_dev);
|
2009-09-07 11:26:23 +08:00
|
|
|
|
2011-05-02 15:59:02 +08:00
|
|
|
spin_lock_irq(&sh_dmae_lock);
|
2010-12-17 18:16:10 +08:00
|
|
|
list_del_rcu(&shdev->node);
|
2011-05-02 15:59:02 +08:00
|
|
|
spin_unlock_irq(&sh_dmae_lock);
|
2010-12-17 18:16:10 +08:00
|
|
|
|
2010-02-12 00:50:18 +08:00
|
|
|
pm_runtime_disable(&pdev->dev);
|
|
|
|
|
2012-05-09 23:09:21 +08:00
|
|
|
sh_dmae_chan_remove(shdev);
|
|
|
|
shdma_cleanup(&shdev->shdma_dev);
|
|
|
|
|
2011-05-02 15:59:02 +08:00
|
|
|
synchronize_rcu();
|
2010-02-12 00:50:10 +08:00
|
|
|
|
2009-09-07 11:26:23 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct platform_driver sh_dmae_driver = {
|
2012-05-09 23:09:21 +08:00
|
|
|
.driver = {
|
2010-05-21 23:28:51 +08:00
|
|
|
.owner = THIS_MODULE,
|
2011-04-30 01:09:25 +08:00
|
|
|
.pm = &sh_dmae_pm,
|
2012-05-09 23:09:21 +08:00
|
|
|
.name = SH_DMAE_DRV_NAME,
|
2013-06-19 00:16:57 +08:00
|
|
|
.of_match_table = sh_dmae_of_match,
|
2009-09-07 11:26:23 +08:00
|
|
|
},
|
2012-11-20 02:20:04 +08:00
|
|
|
.remove = sh_dmae_remove,
|
2012-05-09 23:09:21 +08:00
|
|
|
.shutdown = sh_dmae_shutdown,
|
2009-09-07 11:26:23 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
static int __init sh_dmae_init(void)
|
|
|
|
{
|
2011-01-07 01:04:50 +08:00
|
|
|
/* Wire up NMI handling */
|
|
|
|
int err = register_die_notifier(&sh_dmae_nmi_notifier);
|
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
|
2009-09-07 11:26:23 +08:00
|
|
|
return platform_driver_probe(&sh_dmae_driver, sh_dmae_probe);
|
|
|
|
}
|
|
|
|
module_init(sh_dmae_init);
|
|
|
|
|
|
|
|
static void __exit sh_dmae_exit(void)
|
|
|
|
{
|
|
|
|
platform_driver_unregister(&sh_dmae_driver);
|
2011-01-07 01:04:50 +08:00
|
|
|
|
|
|
|
unregister_die_notifier(&sh_dmae_nmi_notifier);
|
2009-09-07 11:26:23 +08:00
|
|
|
}
|
|
|
|
module_exit(sh_dmae_exit);
|
|
|
|
|
|
|
|
MODULE_AUTHOR("Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>");
|
|
|
|
MODULE_DESCRIPTION("Renesas SH DMA Engine driver");
|
|
|
|
MODULE_LICENSE("GPL");
|
2012-05-09 23:09:21 +08:00
|
|
|
MODULE_ALIAS("platform:" SH_DMAE_DRV_NAME);
|