blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-07 05:50:22 +08:00
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#ifndef __BFIN_SPINLOCK_H
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#define __BFIN_SPINLOCK_H
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2009-06-13 23:21:51 +08:00
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#ifndef CONFIG_SMP
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# include <asm-generic/spinlock.h>
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#else
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2009-01-07 23:14:39 +08:00
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#include <asm/atomic.h>
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blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-07 05:50:22 +08:00
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2009-01-07 23:14:39 +08:00
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asmlinkage int __raw_spin_is_locked_asm(volatile int *ptr);
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asmlinkage void __raw_spin_lock_asm(volatile int *ptr);
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asmlinkage int __raw_spin_trylock_asm(volatile int *ptr);
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asmlinkage void __raw_spin_unlock_asm(volatile int *ptr);
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asmlinkage void __raw_read_lock_asm(volatile int *ptr);
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asmlinkage int __raw_read_trylock_asm(volatile int *ptr);
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asmlinkage void __raw_read_unlock_asm(volatile int *ptr);
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asmlinkage void __raw_write_lock_asm(volatile int *ptr);
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asmlinkage int __raw_write_trylock_asm(volatile int *ptr);
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asmlinkage void __raw_write_unlock_asm(volatile int *ptr);
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static inline int __raw_spin_is_locked(raw_spinlock_t *lock)
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{
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return __raw_spin_is_locked_asm(&lock->lock);
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}
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static inline void __raw_spin_lock(raw_spinlock_t *lock)
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{
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__raw_spin_lock_asm(&lock->lock);
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}
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#define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock)
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static inline int __raw_spin_trylock(raw_spinlock_t *lock)
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{
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return __raw_spin_trylock_asm(&lock->lock);
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}
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static inline void __raw_spin_unlock(raw_spinlock_t *lock)
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{
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__raw_spin_unlock_asm(&lock->lock);
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}
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static inline void __raw_spin_unlock_wait(raw_spinlock_t *lock)
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{
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while (__raw_spin_is_locked(lock))
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cpu_relax();
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}
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static inline int __raw_read_can_lock(raw_rwlock_t *rw)
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{
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return __raw_uncached_fetch_asm(&rw->lock) > 0;
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}
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static inline int __raw_write_can_lock(raw_rwlock_t *rw)
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{
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return __raw_uncached_fetch_asm(&rw->lock) == RW_LOCK_BIAS;
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}
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static inline void __raw_read_lock(raw_rwlock_t *rw)
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{
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__raw_read_lock_asm(&rw->lock);
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}
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static inline int __raw_read_trylock(raw_rwlock_t *rw)
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{
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return __raw_read_trylock_asm(&rw->lock);
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}
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static inline void __raw_read_unlock(raw_rwlock_t *rw)
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{
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__raw_read_unlock_asm(&rw->lock);
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}
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static inline void __raw_write_lock(raw_rwlock_t *rw)
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{
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__raw_write_lock_asm(&rw->lock);
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}
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static inline int __raw_write_trylock(raw_rwlock_t *rw)
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{
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return __raw_write_trylock_asm(&rw->lock);
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}
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static inline void __raw_write_unlock(raw_rwlock_t *rw)
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{
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__raw_write_unlock_asm(&rw->lock);
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}
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#define _raw_spin_relax(lock) cpu_relax()
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#define _raw_read_relax(lock) cpu_relax()
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#define _raw_write_relax(lock) cpu_relax()
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2009-06-13 23:21:51 +08:00
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#endif
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2009-01-07 23:14:39 +08:00
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#endif /* !__BFIN_SPINLOCK_H */
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