2015-04-23 16:35:43 +08:00
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Mediatek infracfg controller
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============================
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The Mediatek infracfg controller provides various clocks and reset
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outputs to the system.
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Required Properties:
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2016-08-19 13:34:50 +08:00
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- compatible: Should be one of:
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- "mediatek,mt2701-infracfg", "syscon"
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dt-bindings: ARM: Mediatek: Document bindings for MT2712
This patch adds the binding documentation for apmixedsys, bdpsys,
imgsys, imgsys, infracfg, mcucfg, mfgcfg, mmsys, pericfg, topckgen,
vdecsys and vencsys for Mediatek MT2712.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-10-23 12:10:32 +08:00
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- "mediatek,mt2712-infracfg", "syscon"
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2017-04-08 09:20:28 +08:00
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- "mediatek,mt6797-infracfg", "syscon"
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2017-10-05 11:50:22 +08:00
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- "mediatek,mt7622-infracfg", "syscon"
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2015-04-23 16:35:43 +08:00
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- "mediatek,mt8135-infracfg", "syscon"
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- "mediatek,mt8173-infracfg", "syscon"
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- #clock-cells: Must be 1
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- #reset-cells: Must be 1
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The infracfg controller uses the common clk binding from
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Documentation/devicetree/bindings/clock/clock-bindings.txt
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The available clocks are defined in dt-bindings/clock/mt*-clk.h.
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Also it uses the common reset controller binding from
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Documentation/devicetree/bindings/reset/reset.txt.
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The available reset outputs are defined in
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2015-11-20 19:42:44 +08:00
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dt-bindings/reset/mt*-resets.h
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2015-04-23 16:35:43 +08:00
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Example:
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2015-05-07 16:14:58 +08:00
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infracfg: power-controller@10001000 {
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2015-04-23 16:35:43 +08:00
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compatible = "mediatek,mt8173-infracfg", "syscon";
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reg = <0 0x10001000 0 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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