2008-10-23 13:26:29 +08:00
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#ifndef _ASM_X86_MCE_H
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#define _ASM_X86_MCE_H
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2007-10-18 00:04:40 +08:00
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2012-12-15 06:37:13 +08:00
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#include <uapi/asm/mce.h>
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2007-10-18 00:04:40 +08:00
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2012-10-16 00:03:57 +08:00
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struct mca_config {
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bool dont_log_ce;
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2012-10-16 02:25:17 +08:00
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bool cmci_disabled;
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bool ignore_ce;
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2012-10-17 18:05:33 +08:00
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bool disabled;
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bool ser;
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bool bios_cmci_threshold;
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2012-10-16 00:03:57 +08:00
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u8 banks;
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2012-10-16 01:59:18 +08:00
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s8 bootlog;
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2012-10-16 00:03:57 +08:00
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int tolerant;
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2012-10-16 01:59:18 +08:00
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int monarch_timeout;
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2012-10-16 02:25:17 +08:00
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int panic_timeout;
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2012-10-16 01:59:18 +08:00
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u32 rip_msr;
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2012-10-16 00:03:57 +08:00
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};
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2012-10-16 02:25:17 +08:00
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extern struct mca_config mca_cfg;
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2011-12-04 22:12:09 +08:00
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extern void mce_register_decode_chain(struct notifier_block *nb);
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extern void mce_unregister_decode_chain(struct notifier_block *nb);
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2010-01-05 00:17:21 +08:00
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2009-06-15 16:22:15 +08:00
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#include <linux/percpu.h>
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#include <linux/init.h>
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2011-07-27 07:09:06 +08:00
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#include <linux/atomic.h>
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2009-06-15 16:22:15 +08:00
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2009-06-15 16:22:49 +08:00
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extern int mce_p5_enabled;
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2007-10-18 00:04:40 +08:00
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2009-06-15 16:27:47 +08:00
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#ifdef CONFIG_X86_MCE
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2009-11-10 09:38:24 +08:00
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int mcheck_init(void);
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2009-10-16 18:31:32 +08:00
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void mcheck_cpu_init(struct cpuinfo_x86 *c);
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2009-06-15 16:27:47 +08:00
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#else
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2009-11-10 09:38:24 +08:00
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static inline int mcheck_init(void) { return 0; }
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2009-10-16 18:31:32 +08:00
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static inline void mcheck_cpu_init(struct cpuinfo_x86 *c) {}
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2009-06-15 16:27:47 +08:00
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#endif
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2009-06-15 16:22:15 +08:00
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#ifdef CONFIG_X86_ANCIENT_MCE
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void intel_p5_mcheck_init(struct cpuinfo_x86 *c);
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void winchip_mcheck_init(struct cpuinfo_x86 *c);
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2009-06-15 16:22:49 +08:00
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static inline void enable_p5_mce(void) { mce_p5_enabled = 1; }
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2009-06-15 16:22:15 +08:00
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#else
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static inline void intel_p5_mcheck_init(struct cpuinfo_x86 *c) {}
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static inline void winchip_mcheck_init(struct cpuinfo_x86 *c) {}
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2009-06-15 16:22:49 +08:00
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static inline void enable_p5_mce(void) {}
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2009-06-15 16:22:15 +08:00
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#endif
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2009-02-12 20:43:22 +08:00
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void mce_setup(struct mce *m);
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2007-10-18 00:04:40 +08:00
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void mce_log(struct mce *m);
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2012-01-27 07:49:14 +08:00
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DECLARE_PER_CPU(struct device *, mce_device);
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2007-10-18 00:04:40 +08:00
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2009-02-12 20:49:30 +08:00
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/*
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2009-07-09 06:31:45 +08:00
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* Maximum banks number.
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* This is the limit of the current register layout on
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* Intel CPUs.
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2009-02-12 20:49:30 +08:00
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*/
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2009-07-09 06:31:45 +08:00
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#define MAX_NR_BANKS 32
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2009-02-12 20:49:30 +08:00
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2007-10-18 00:04:40 +08:00
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#ifdef CONFIG_X86_MCE_INTEL
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void mce_intel_feature_init(struct cpuinfo_x86 *c);
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2009-02-12 20:49:36 +08:00
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void cmci_clear(void);
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void cmci_reenable(void);
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void cmci_rediscover(int dying);
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void cmci_recheck(void);
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2007-10-18 00:04:40 +08:00
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#else
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static inline void mce_intel_feature_init(struct cpuinfo_x86 *c) { }
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2009-02-12 20:49:36 +08:00
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static inline void cmci_clear(void) {}
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static inline void cmci_reenable(void) {}
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static inline void cmci_rediscover(int dying) {}
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static inline void cmci_recheck(void) {}
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2007-10-18 00:04:40 +08:00
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#endif
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#ifdef CONFIG_X86_MCE_AMD
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void mce_amd_feature_init(struct cpuinfo_x86 *c);
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#else
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static inline void mce_amd_feature_init(struct cpuinfo_x86 *c) { }
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#endif
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2009-05-29 01:05:33 +08:00
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int mce_available(struct cpuinfo_x86 *c);
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2009-02-12 20:49:36 +08:00
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2009-05-28 03:56:52 +08:00
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DECLARE_PER_CPU(unsigned, mce_exception_count);
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2009-05-28 03:56:57 +08:00
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DECLARE_PER_CPU(unsigned, mce_poll_count);
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2009-05-28 03:56:52 +08:00
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2007-10-18 00:04:40 +08:00
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extern atomic_t mce_entry;
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2009-02-12 20:49:34 +08:00
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typedef DECLARE_BITMAP(mce_banks_t, MAX_NR_BANKS);
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DECLARE_PER_CPU(mce_banks_t, mce_poll_banks);
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2009-02-12 20:43:23 +08:00
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enum mcp_flags {
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MCP_TIMESTAMP = (1 << 0), /* log time stamp */
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MCP_UC = (1 << 1), /* log uncorrected errors */
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2009-04-07 23:06:55 +08:00
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MCP_DONTLOG = (1 << 2), /* only clear, don't log */
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2009-02-12 20:43:23 +08:00
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};
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2009-05-29 01:05:33 +08:00
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void machine_check_poll(enum mcp_flags flags, mce_banks_t *b);
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2009-02-12 20:43:23 +08:00
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2009-05-28 03:56:58 +08:00
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int mce_notify_irq(void);
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x86, mce: support action-optional machine checks
Newer Intel CPUs support a new class of machine checks called recoverable
action optional.
Action Optional means that the CPU detected some form of corruption in
the background and tells the OS about using a machine check
exception. The OS can then take appropiate action, like killing the
process with the corrupted data or logging the event properly to disk.
This is done by the new generic high level memory failure handler added
in a earlier patch. The high level handler takes the address with the
failed memory and does the appropiate action, like killing the process.
In this version of the patch the high level handler is stubbed out
with a weak function to not create a direct dependency on the hwpoison
branch.
The high level handler cannot be directly called from the machine check
exception though, because it has to run in a defined process context to
be able to sleep when taking VM locks (it is not expected to sleep for a
long time, just do so in some exceptional cases like lock contention)
Thus the MCE handler has to queue a work item for process context,
trigger process context and then call the high level handler from there.
This patch adds two path to process context: through a per thread kernel
exit notify_user() callback or through a high priority work item.
The first runs when the process exits back to user space, the other when
it goes to sleep and there is no higher priority process.
The machine check handler will schedule both, and whoever runs first
will grab the event. This is done because quick reaction to this
event is critical to avoid a potential more fatal machine check
when the corruption is consumed.
There is a simple lock less ring buffer to queue the corrupted
addresses between the exception handler and the process context handler.
Then in process context it just calls the high level VM code with
the corrupted PFNs.
The code adds the required code to extract the failed address from
the CPU's machine check registers. It doesn't try to handle all
possible cases -- the specification has 6 different ways to specify
memory address -- but only the linear address.
Most of the required checking has been already done earlier in the
mce_severity rule checking engine. Following the Intel
recommendations Action Optional errors are only enabled for known
situations (encoded in MCACODs). The errors are ignored otherwise,
because they are action optional.
v2: Improve comment, disable preemption while processing ring buffer
(reported by Ying Huang)
Signed-off-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2009-05-28 03:56:59 +08:00
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void mce_notify_process(void);
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2007-10-18 00:04:40 +08:00
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2009-04-30 01:31:00 +08:00
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DECLARE_PER_CPU(struct mce, injectm);
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2011-11-04 02:46:47 +08:00
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extern void register_mce_write_callback(ssize_t (*)(struct file *filp,
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const char __user *ubuf,
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size_t usize, loff_t *off));
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2009-04-30 01:31:00 +08:00
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2009-06-15 16:27:47 +08:00
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/*
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* Exception handler
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*/
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/* Call the installed machine check handler for this CPU setup. */
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extern void (*machine_check_vector)(struct pt_regs *, long error_code);
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void do_machine_check(struct pt_regs *, long);
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/*
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* Threshold handler
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*/
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2007-10-18 00:04:40 +08:00
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2009-02-12 20:49:31 +08:00
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extern void (*mce_threshold_vector)(void);
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2009-06-15 16:27:47 +08:00
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extern void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
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2009-02-12 20:49:31 +08:00
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2009-06-15 16:24:40 +08:00
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/*
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* Thermal handler
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*/
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void intel_init_thermal(struct cpuinfo_x86 *c);
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void mce_log_therm_throt_event(__u64 status);
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2009-11-10 09:38:24 +08:00
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2011-01-03 19:52:04 +08:00
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/* Interrupt Handler for core thermal thresholds */
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extern int (*platform_thermal_notify)(__u64 msr_val);
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2009-11-10 09:38:24 +08:00
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#ifdef CONFIG_X86_THERMAL_VECTOR
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extern void mcheck_intel_therm_init(void);
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#else
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static inline void mcheck_intel_therm_init(void) { }
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#endif
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ACPI, APEI, Generic Hardware Error Source memory error support
Generic Hardware Error Source provides a way to report platform
hardware errors (such as that from chipset). It works in so called
"Firmware First" mode, that is, hardware errors are reported to
firmware firstly, then reported to Linux by firmware. This way, some
non-standard hardware error registers or non-standard hardware link
can be checked by firmware to produce more valuable hardware error
information for Linux.
Now, only SCI notification type and memory errors are supported. More
notification type and hardware error type will be added later. These
memory errors are reported to user space through /dev/mcelog via
faking a corrected Machine Check, so that the error memory page can be
offlined by /sbin/mcelog if the error count for one page is beyond the
threshold.
On some machines, Machine Check can not report physical address for
some corrected memory errors, but GHES can do that. So this simplified
GHES is implemented firstly.
Signed-off-by: Huang Ying <ying.huang@intel.com>
Signed-off-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>
2010-05-18 14:35:20 +08:00
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/*
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* Used by APEI to report memory error via /dev/mcelog
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*/
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struct cper_sec_mem_err;
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extern void apei_mce_report_mem_error(int corrected,
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struct cper_sec_mem_err *mem_err);
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2008-10-23 13:26:29 +08:00
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#endif /* _ASM_X86_MCE_H */
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