2015-05-20 10:54:31 +08:00
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/*
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* NVDIMM Firmware Interface Table - NFIT
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*
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* Copyright(c) 2013-2015 Intel Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*/
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#ifndef __NFIT_H__
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#define __NFIT_H__
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2016-02-20 04:16:34 +08:00
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#include <linux/workqueue.h>
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2015-05-20 10:54:31 +08:00
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#include <linux/libnvdimm.h>
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2016-07-24 12:51:21 +08:00
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#include <linux/ndctl.h>
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2015-05-20 10:54:31 +08:00
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#include <linux/types.h>
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#include <linux/uuid.h>
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#include <linux/acpi.h>
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#include <acpi/acuuid.h>
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2016-04-29 07:23:43 +08:00
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/* ACPI 6.1 */
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2015-05-20 10:54:31 +08:00
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#define UUID_NFIT_BUS "2f10e7a4-9e91-11e4-89d3-123b93f75cba"
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2016-04-29 07:23:43 +08:00
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/* http://pmem.io/documents/NVDIMM_DSM_Interface_Example.pdf */
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2015-05-20 10:54:31 +08:00
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#define UUID_NFIT_DIMM "4309ac30-0d11-11e4-9191-0800200c9a66"
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2016-04-29 07:23:43 +08:00
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/* https://github.com/HewlettPackard/hpe-nvm/blob/master/Documentation/ */
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#define UUID_NFIT_DIMM_N_HPE1 "9002c334-acf3-4c0e-9642-a235f0d53bc6"
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#define UUID_NFIT_DIMM_N_HPE2 "5008664b-b758-41a0-a03c-27c2f2d04f7e"
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2016-05-27 00:38:41 +08:00
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/* https://msdn.microsoft.com/library/windows/hardware/mt604741 */
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#define UUID_NFIT_DIMM_N_MSFT "1ee68b36-d4bd-4a1a-9a16-4f8e53d46e05"
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2015-06-24 08:08:34 +08:00
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#define ACPI_NFIT_MEM_FAILED_MASK (ACPI_NFIT_MEM_SAVE_FAILED \
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| ACPI_NFIT_MEM_RESTORE_FAILED | ACPI_NFIT_MEM_FLUSH_FAILED \
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2015-10-19 10:24:52 +08:00
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| ACPI_NFIT_MEM_NOT_ARMED)
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2015-05-20 10:54:31 +08:00
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enum nfit_uuids {
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2016-04-29 07:23:43 +08:00
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/* for simplicity alias the uuid index with the family id */
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NFIT_DEV_DIMM = NVDIMM_FAMILY_INTEL,
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NFIT_DEV_DIMM_N_HPE1 = NVDIMM_FAMILY_HPE1,
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NFIT_DEV_DIMM_N_HPE2 = NVDIMM_FAMILY_HPE2,
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2016-05-27 00:38:41 +08:00
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NFIT_DEV_DIMM_N_MSFT = NVDIMM_FAMILY_MSFT,
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2015-05-20 10:54:31 +08:00
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NFIT_SPA_VOLATILE,
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NFIT_SPA_PM,
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NFIT_SPA_DCR,
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NFIT_SPA_BDW,
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NFIT_SPA_VDISK,
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NFIT_SPA_VCD,
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NFIT_SPA_PDISK,
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NFIT_SPA_PCD,
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NFIT_DEV_BUS,
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NFIT_UUID_MAX,
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};
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2016-04-29 09:35:23 +08:00
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/*
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2016-06-30 02:19:32 +08:00
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* Region format interface codes are stored with the interface as the
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* LSB and the function as the MSB.
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2016-04-29 09:35:23 +08:00
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*/
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2016-06-30 02:19:32 +08:00
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#define NFIT_FIC_BYTE cpu_to_le16(0x101) /* byte-addressable energy backed */
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#define NFIT_FIC_BLK cpu_to_le16(0x201) /* block-addressable non-energy backed */
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#define NFIT_FIC_BYTEN cpu_to_le16(0x301) /* byte-addressable non-energy backed */
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2016-02-02 09:48:42 +08:00
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2015-07-11 01:06:14 +08:00
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enum {
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2016-02-13 09:01:11 +08:00
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NFIT_BLK_READ_FLUSH = 1,
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NFIT_BLK_DCR_LATCH = 2,
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NFIT_ARS_STATUS_DONE = 0,
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NFIT_ARS_STATUS_BUSY = 1 << 16,
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NFIT_ARS_STATUS_NONE = 2 << 16,
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NFIT_ARS_STATUS_INTR = 3 << 16,
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NFIT_ARS_START_BUSY = 6,
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NFIT_ARS_CAP_NONE = 1,
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NFIT_ARS_F_OVERFLOW = 1,
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2016-02-18 05:01:23 +08:00
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NFIT_ARS_TIMEOUT = 90,
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2015-07-11 01:06:14 +08:00
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};
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2015-05-20 10:54:31 +08:00
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struct nfit_spa {
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struct list_head list;
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2016-02-18 05:01:23 +08:00
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struct nd_region *nd_region;
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2016-07-24 12:51:42 +08:00
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unsigned int ars_required:1;
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2016-02-18 05:01:23 +08:00
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u32 clear_err_unit;
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u32 max_ars;
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2016-07-15 08:22:48 +08:00
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struct acpi_nfit_system_address spa[0];
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2015-05-20 10:54:31 +08:00
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};
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struct nfit_dcr {
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struct list_head list;
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2016-07-15 08:22:48 +08:00
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struct acpi_nfit_control_region dcr[0];
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2015-05-20 10:54:31 +08:00
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};
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struct nfit_bdw {
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struct list_head list;
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2016-07-15 08:22:48 +08:00
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struct acpi_nfit_data_region bdw[0];
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2015-05-20 10:54:31 +08:00
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};
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2015-06-25 16:21:02 +08:00
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struct nfit_idt {
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struct list_head list;
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2016-07-15 08:22:48 +08:00
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struct acpi_nfit_interleave idt[0];
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2015-06-25 16:21:02 +08:00
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};
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2015-07-11 01:06:13 +08:00
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struct nfit_flush {
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struct list_head list;
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2016-07-15 08:22:48 +08:00
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struct acpi_nfit_flush_address flush[0];
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2015-07-11 01:06:13 +08:00
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};
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2015-05-20 10:54:31 +08:00
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struct nfit_memdev {
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struct list_head list;
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2016-07-15 08:22:48 +08:00
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struct acpi_nfit_memory_map memdev[0];
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2015-05-20 10:54:31 +08:00
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};
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/* assembled tables for a given dimm/memory-device */
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struct nfit_mem {
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2015-04-25 15:56:17 +08:00
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struct nvdimm *nvdimm;
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2015-05-20 10:54:31 +08:00
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struct acpi_nfit_memory_map *memdev_dcr;
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struct acpi_nfit_memory_map *memdev_pmem;
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2015-06-25 16:21:02 +08:00
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struct acpi_nfit_memory_map *memdev_bdw;
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2015-05-20 10:54:31 +08:00
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struct acpi_nfit_control_region *dcr;
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struct acpi_nfit_data_region *bdw;
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struct acpi_nfit_system_address *spa_dcr;
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struct acpi_nfit_system_address *spa_bdw;
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2015-06-25 16:21:02 +08:00
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struct acpi_nfit_interleave *idt_dcr;
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struct acpi_nfit_interleave *idt_bdw;
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2015-07-11 01:06:13 +08:00
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struct nfit_flush *nfit_flush;
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2015-05-20 10:54:31 +08:00
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struct list_head list;
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2015-06-09 02:27:06 +08:00
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struct acpi_device *adev;
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2016-04-06 06:26:50 +08:00
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struct acpi_nfit_desc *acpi_desc;
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2016-06-08 08:00:04 +08:00
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struct resource *flush_wpq;
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2015-06-09 02:27:06 +08:00
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unsigned long dsm_mask;
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2016-04-29 07:23:43 +08:00
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int family;
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2015-05-20 10:54:31 +08:00
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};
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struct acpi_nfit_desc {
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struct nvdimm_bus_descriptor nd_desc;
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2015-11-21 08:05:49 +08:00
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struct acpi_table_header acpi_header;
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2015-10-28 06:58:27 +08:00
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struct mutex init_mutex;
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2015-05-20 10:54:31 +08:00
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struct list_head memdevs;
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2015-07-11 01:06:13 +08:00
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struct list_head flushes;
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2015-05-20 10:54:31 +08:00
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struct list_head dimms;
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struct list_head spas;
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struct list_head dcrs;
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struct list_head bdws;
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2015-06-25 16:21:02 +08:00
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struct list_head idts;
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2015-05-20 10:54:31 +08:00
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struct nvdimm_bus *nvdimm_bus;
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struct device *dev;
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2016-02-18 05:01:23 +08:00
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struct nd_cmd_ars_status *ars_status;
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size_t ars_status_size;
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2016-02-20 04:16:34 +08:00
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struct work_struct work;
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2016-07-24 12:51:21 +08:00
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struct list_head list;
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2016-07-24 12:51:42 +08:00
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struct kernfs_node *scrub_count_state;
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unsigned int scrub_count;
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2016-02-20 04:16:34 +08:00
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unsigned int cancel:1;
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2016-04-29 07:17:07 +08:00
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unsigned long dimm_cmd_force_en;
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unsigned long bus_cmd_force_en;
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2015-06-18 05:23:32 +08:00
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int (*blk_do_io)(struct nd_blk_region *ndbr, resource_size_t dpa,
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void *iobuf, u64 len, int rw);
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2015-05-20 10:54:31 +08:00
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};
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2015-06-25 16:21:02 +08:00
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enum nd_blk_mmio_selector {
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BDW,
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DCR,
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};
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nd_blk: change aperture mapping from WC to WB
This should result in a pretty sizeable performance gain for reads. For
rough comparison I did some simple read testing using PMEM to compare
reads of write combining (WC) mappings vs write-back (WB). This was
done on a random lab machine.
PMEM reads from a write combining mapping:
# dd of=/dev/null if=/dev/pmem0 bs=4096 count=100000
100000+0 records in
100000+0 records out
409600000 bytes (410 MB) copied, 9.2855 s, 44.1 MB/s
PMEM reads from a write-back mapping:
# dd of=/dev/null if=/dev/pmem0 bs=4096 count=1000000
1000000+0 records in
1000000+0 records out
4096000000 bytes (4.1 GB) copied, 3.44034 s, 1.2 GB/s
To be able to safely support a write-back aperture I needed to add
support for the "read flush" _DSM flag, as outlined in the DSM spec:
http://pmem.io/documents/NVDIMM_DSM_Interface_Example.pdf
This flag tells the ND BLK driver that it needs to flush the cache lines
associated with the aperture after the aperture is moved but before any
new data is read. This ensures that any stale cache lines from the
previous contents of the aperture will be discarded from the processor
cache, and the new data will be read properly from the DIMM. We know
that the cache lines are clean and will be discarded without any
writeback because either a) the previous aperture operation was a read,
and we never modified the contents of the aperture, or b) the previous
aperture operation was a write and we must have written back the dirtied
contents of the aperture to the DIMM before the I/O was completed.
In order to add support for the "read flush" flag I needed to add a
generic routine to invalidate cache lines, mmio_flush_range(). This is
protected by the ARCH_HAS_MMIO_FLUSH Kconfig variable, and is currently
only supported on x86.
Signed-off-by: Ross Zwisler <ross.zwisler@linux.intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2015-08-28 03:14:20 +08:00
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struct nd_blk_addr {
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union {
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void __iomem *base;
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2016-06-04 09:06:47 +08:00
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void *aperture;
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nd_blk: change aperture mapping from WC to WB
This should result in a pretty sizeable performance gain for reads. For
rough comparison I did some simple read testing using PMEM to compare
reads of write combining (WC) mappings vs write-back (WB). This was
done on a random lab machine.
PMEM reads from a write combining mapping:
# dd of=/dev/null if=/dev/pmem0 bs=4096 count=100000
100000+0 records in
100000+0 records out
409600000 bytes (410 MB) copied, 9.2855 s, 44.1 MB/s
PMEM reads from a write-back mapping:
# dd of=/dev/null if=/dev/pmem0 bs=4096 count=1000000
1000000+0 records in
1000000+0 records out
4096000000 bytes (4.1 GB) copied, 3.44034 s, 1.2 GB/s
To be able to safely support a write-back aperture I needed to add
support for the "read flush" _DSM flag, as outlined in the DSM spec:
http://pmem.io/documents/NVDIMM_DSM_Interface_Example.pdf
This flag tells the ND BLK driver that it needs to flush the cache lines
associated with the aperture after the aperture is moved but before any
new data is read. This ensures that any stale cache lines from the
previous contents of the aperture will be discarded from the processor
cache, and the new data will be read properly from the DIMM. We know
that the cache lines are clean and will be discarded without any
writeback because either a) the previous aperture operation was a read,
and we never modified the contents of the aperture, or b) the previous
aperture operation was a write and we must have written back the dirtied
contents of the aperture to the DIMM before the I/O was completed.
In order to add support for the "read flush" flag I needed to add a
generic routine to invalidate cache lines, mmio_flush_range(). This is
protected by the ARCH_HAS_MMIO_FLUSH Kconfig variable, and is currently
only supported on x86.
Signed-off-by: Ross Zwisler <ross.zwisler@linux.intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2015-08-28 03:14:20 +08:00
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};
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};
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2015-06-25 16:21:02 +08:00
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struct nfit_blk {
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struct nfit_blk_mmio {
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nd_blk: change aperture mapping from WC to WB
This should result in a pretty sizeable performance gain for reads. For
rough comparison I did some simple read testing using PMEM to compare
reads of write combining (WC) mappings vs write-back (WB). This was
done on a random lab machine.
PMEM reads from a write combining mapping:
# dd of=/dev/null if=/dev/pmem0 bs=4096 count=100000
100000+0 records in
100000+0 records out
409600000 bytes (410 MB) copied, 9.2855 s, 44.1 MB/s
PMEM reads from a write-back mapping:
# dd of=/dev/null if=/dev/pmem0 bs=4096 count=1000000
1000000+0 records in
1000000+0 records out
4096000000 bytes (4.1 GB) copied, 3.44034 s, 1.2 GB/s
To be able to safely support a write-back aperture I needed to add
support for the "read flush" _DSM flag, as outlined in the DSM spec:
http://pmem.io/documents/NVDIMM_DSM_Interface_Example.pdf
This flag tells the ND BLK driver that it needs to flush the cache lines
associated with the aperture after the aperture is moved but before any
new data is read. This ensures that any stale cache lines from the
previous contents of the aperture will be discarded from the processor
cache, and the new data will be read properly from the DIMM. We know
that the cache lines are clean and will be discarded without any
writeback because either a) the previous aperture operation was a read,
and we never modified the contents of the aperture, or b) the previous
aperture operation was a write and we must have written back the dirtied
contents of the aperture to the DIMM before the I/O was completed.
In order to add support for the "read flush" flag I needed to add a
generic routine to invalidate cache lines, mmio_flush_range(). This is
protected by the ARCH_HAS_MMIO_FLUSH Kconfig variable, and is currently
only supported on x86.
Signed-off-by: Ross Zwisler <ross.zwisler@linux.intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2015-08-28 03:14:20 +08:00
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struct nd_blk_addr addr;
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2015-06-25 16:21:02 +08:00
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u64 size;
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u64 base_offset;
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u32 line_size;
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u32 num_lines;
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u32 table_size;
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struct acpi_nfit_interleave *idt;
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struct acpi_nfit_system_address *spa;
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} mmio[2];
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struct nd_region *nd_region;
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u64 bdw_offset; /* post interleave offset */
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u64 stat_offset;
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u64 cmd_offset;
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2015-07-11 01:06:14 +08:00
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u32 dimm_flags;
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2015-07-11 01:06:13 +08:00
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};
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2016-07-24 12:51:21 +08:00
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extern struct list_head acpi_descs;
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extern struct mutex acpi_desc_lock;
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int acpi_nfit_ars_rescan(struct acpi_nfit_desc *acpi_desc);
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2015-06-25 16:21:02 +08:00
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2016-07-24 12:51:21 +08:00
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#ifdef CONFIG_X86_MCE
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void nfit_mce_register(void);
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void nfit_mce_unregister(void);
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#else
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static inline void nfit_mce_register(void)
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2015-06-25 16:21:02 +08:00
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{
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}
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2016-07-24 12:51:21 +08:00
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static inline void nfit_mce_unregister(void)
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{
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}
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#endif
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int nfit_spa_type(struct acpi_nfit_system_address *spa);
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2015-06-25 16:21:02 +08:00
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2015-05-20 10:54:31 +08:00
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static inline struct acpi_nfit_memory_map *__to_nfit_memdev(
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struct nfit_mem *nfit_mem)
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{
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if (nfit_mem->memdev_dcr)
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return nfit_mem->memdev_dcr;
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return nfit_mem->memdev_pmem;
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}
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2015-04-27 07:26:48 +08:00
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static inline struct acpi_nfit_desc *to_acpi_desc(
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struct nvdimm_bus_descriptor *nd_desc)
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{
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return container_of(nd_desc, struct acpi_nfit_desc, nd_desc);
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}
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2015-06-18 05:23:32 +08:00
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const u8 *to_nfit_uuid(enum nfit_uuids id);
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2016-07-15 07:19:55 +08:00
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int acpi_nfit_init(struct acpi_nfit_desc *acpi_desc, void *nfit, acpi_size sz);
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2016-02-20 04:29:32 +08:00
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void acpi_nfit_desc_init(struct acpi_nfit_desc *acpi_desc, struct device *dev);
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2015-05-20 10:54:31 +08:00
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#endif /* __NFIT_H__ */
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