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sh: intc: userimask support. This adds support for hardware-assisted userspace irq masking for special priority levels. Due to the SR.IMASK interactivity, only some platforms implement this in hardware (including but not limited to SH-4A interrupt controllers, and ARM-based SH-Mobile CPUs). Each CPU needs to wire this up on its own, for now only SH7786 is wired up as an example. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2010-04-13 13:43:03 +08:00
config INTC_USERIMASK
bool "Userspace interrupt masking support"
depends on ARCH_SHMOBILE || (SUPERH && CPU_SH4A)
help
This enables support for hardware-assisted userspace hardirq
masking.
SH-4A and newer interrupt blocks all support a special shadowed
page with all non-masking registers obscured when mapped in to
userspace. This is primarily for use by userspace device
drivers that are using special priority levels.
If in doubt, say N.
sh: intc: IRQ auto-distribution support. This implements support for hardware-managed IRQ balancing as implemented by SH-X3 cores (presently only hooked up for SH7786, but can probably be carried over to other SH-X3 cores, too). CPUs need to specify their distribution register along with the mask definitions, as these follow the same format. Peripheral IRQs that don't opt out of balancing will be automatically distributed at the whim of the hardware block, while each CPU needs to verify whether it is handling the IRQ or not, especially before clearing the mask. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2010-04-15 12:13:52 +08:00
config INTC_BALANCING
bool "Hardware IRQ balancing support"
depends on SMP && SUPERH && CPU_SUBTYPE_SH7786
help
This enables support for IRQ auto-distribution mode on SH-X3
SMP parts. All of the balancing and CPU wakeup decisions are
taken care of automatically by hardware for distributed
vectors.
If in doubt, say N.