2006-06-18 06:52:48 +08:00
|
|
|
/*
|
2008-10-08 03:00:18 +08:00
|
|
|
* MPC83xx/85xx/86xx PCI/PCIE support routing.
|
2006-06-18 06:52:48 +08:00
|
|
|
*
|
2012-07-11 08:26:47 +08:00
|
|
|
* Copyright 2007-2012 Freescale Semiconductor, Inc.
|
2009-01-09 05:55:39 +08:00
|
|
|
* Copyright 2008-2009 MontaVista Software, Inc.
|
2006-06-18 06:52:48 +08:00
|
|
|
*
|
2007-07-10 18:46:35 +08:00
|
|
|
* Initial author: Xianghua Xiao <x.xiao@freescale.com>
|
|
|
|
* Recode: ZHANG WEI <wei.zhang@freescale.com>
|
|
|
|
* Rewrite the routing for Frescale PCI and PCI Express
|
|
|
|
* Roy Zang <tie-fei.zang@freescale.com>
|
2009-01-09 05:55:39 +08:00
|
|
|
* MPC83xx PCI-Express support:
|
|
|
|
* Tony Li <tony.li@freescale.com>
|
|
|
|
* Anton Vorontsov <avorontsov@ru.mvista.com>
|
2006-06-18 06:52:48 +08:00
|
|
|
*
|
|
|
|
* This program is free software; you can redistribute it and/or modify it
|
|
|
|
* under the terms of the GNU General Public License as published by the
|
|
|
|
* Free Software Foundation; either version 2 of the License, or (at your
|
|
|
|
* option) any later version.
|
|
|
|
*/
|
2007-07-10 18:46:35 +08:00
|
|
|
#include <linux/kernel.h>
|
2006-06-18 06:52:48 +08:00
|
|
|
#include <linux/pci.h>
|
2007-07-10 18:46:35 +08:00
|
|
|
#include <linux/delay.h>
|
|
|
|
#include <linux/string.h>
|
|
|
|
#include <linux/init.h>
|
fsl/pci: The new pci suspend/resume implementation
If we do nothing in suspend/resume, some platform PCIe ip-block
can't guarantee the link back to L0 state from sleep, then, when
we read the EP device will hang. Only we send pme turnoff message
in pci controller suspend, and send pme exit message in resume, the
link state will be normal.
When we send pme turnoff message in pci controller suspend, the
links will into l2/l3 ready, then, host cannot communicate with
ep device, but pci-driver will call back EP device to save them
state. So we need to change platform_driver->suspend/resume to
syscore->suspend/resume.
So the new suspend/resume implementation, send pme turnoff message
in suspend, and send pme exit message in resume. And add a PME handler,
to response PME & message interrupt.
Change platform_driver->suspend/resume to syscore->suspend/resume.
pci-driver will call back EP device, to save EP state in
pci_pm_suspend_noirq, so we need to keep the link, until
pci_pm_suspend_noirq finish.
Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
2014-03-20 11:19:37 +08:00
|
|
|
#include <linux/interrupt.h>
|
2010-07-12 12:36:09 +08:00
|
|
|
#include <linux/memblock.h>
|
2009-05-09 04:05:23 +08:00
|
|
|
#include <linux/log2.h>
|
include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 16:04:11 +08:00
|
|
|
#include <linux/slab.h>
|
fsl/pci: The new pci suspend/resume implementation
If we do nothing in suspend/resume, some platform PCIe ip-block
can't guarantee the link back to L0 state from sleep, then, when
we read the EP device will hang. Only we send pme turnoff message
in pci controller suspend, and send pme exit message in resume, the
link state will be normal.
When we send pme turnoff message in pci controller suspend, the
links will into l2/l3 ready, then, host cannot communicate with
ep device, but pci-driver will call back EP device to save them
state. So we need to change platform_driver->suspend/resume to
syscore->suspend/resume.
So the new suspend/resume implementation, send pme turnoff message
in suspend, and send pme exit message in resume. And add a PME handler,
to response PME & message interrupt.
Change platform_driver->suspend/resume to syscore->suspend/resume.
pci-driver will call back EP device, to save EP state in
pci_pm_suspend_noirq, so we need to keep the link, until
pci_pm_suspend_noirq finish.
Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
2014-03-20 11:19:37 +08:00
|
|
|
#include <linux/suspend.h>
|
|
|
|
#include <linux/syscore_ops.h>
|
2013-04-28 13:20:08 +08:00
|
|
|
#include <linux/uaccess.h>
|
2006-06-18 06:52:48 +08:00
|
|
|
|
|
|
|
#include <asm/io.h>
|
|
|
|
#include <asm/prom.h>
|
|
|
|
#include <asm/pci-bridge.h>
|
2013-04-28 13:20:08 +08:00
|
|
|
#include <asm/ppc-pci.h>
|
2007-07-10 18:46:35 +08:00
|
|
|
#include <asm/machdep.h>
|
2013-04-28 13:20:08 +08:00
|
|
|
#include <asm/disassemble.h>
|
|
|
|
#include <asm/ppc-opcode.h>
|
2006-06-18 06:52:48 +08:00
|
|
|
#include <sysdev/fsl_soc.h>
|
2007-07-10 18:44:34 +08:00
|
|
|
#include <sysdev/fsl_pci.h>
|
2006-06-18 06:52:48 +08:00
|
|
|
|
2010-08-05 15:45:08 +08:00
|
|
|
static int fsl_pcie_bus_fixup, is_mpc83xx_pci;
|
2009-01-09 05:55:39 +08:00
|
|
|
|
2013-08-02 16:46:25 +08:00
|
|
|
static void quirk_fsl_pcie_early(struct pci_dev *dev)
|
2009-01-09 05:55:39 +08:00
|
|
|
{
|
2012-09-24 13:50:52 +08:00
|
|
|
u8 hdr_type;
|
2011-05-20 08:56:50 +08:00
|
|
|
|
2009-01-09 05:55:39 +08:00
|
|
|
/* if we aren't a PCIe don't bother */
|
2013-09-05 15:55:27 +08:00
|
|
|
if (!pci_is_pcie(dev))
|
2009-01-09 05:55:39 +08:00
|
|
|
return;
|
|
|
|
|
2011-05-20 08:56:50 +08:00
|
|
|
/* if we aren't in host mode don't bother */
|
2012-09-24 13:50:52 +08:00
|
|
|
pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type);
|
|
|
|
if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE)
|
2011-05-20 08:56:50 +08:00
|
|
|
return;
|
|
|
|
|
2009-01-09 05:55:39 +08:00
|
|
|
dev->class = PCI_CLASS_BRIDGE_PCI << 8;
|
|
|
|
fsl_pcie_bus_fixup = 1;
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2013-04-08 16:15:28 +08:00
|
|
|
static int fsl_indirect_read_config(struct pci_bus *, unsigned int,
|
|
|
|
int, int, u32 *);
|
|
|
|
|
|
|
|
static int fsl_pcie_check_link(struct pci_controller *hose)
|
2009-01-09 05:55:39 +08:00
|
|
|
{
|
2013-04-08 16:15:28 +08:00
|
|
|
u32 val = 0;
|
2009-01-09 05:55:39 +08:00
|
|
|
|
2013-03-14 03:07:15 +08:00
|
|
|
if (hose->indirect_type & PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK) {
|
2015-01-23 09:05:06 +08:00
|
|
|
if (hose->ops->read == fsl_indirect_read_config)
|
|
|
|
__indirect_read_config(hose, hose->first_busno, 0,
|
|
|
|
PCIE_LTSSM, 4, &val);
|
|
|
|
else
|
2013-04-08 16:15:28 +08:00
|
|
|
early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val);
|
2013-03-14 03:07:15 +08:00
|
|
|
if (val < PCIE_LTSSM_L0)
|
|
|
|
return 1;
|
|
|
|
} else {
|
|
|
|
struct ccsr_pci __iomem *pci = hose->private_data;
|
|
|
|
/* for PCIe IP rev 3.0 or greater use CSR0 for link state */
|
|
|
|
val = (in_be32(&pci->pex_csr0) & PEX_CSR0_LTSSM_MASK)
|
|
|
|
>> PEX_CSR0_LTSSM_SHIFT;
|
|
|
|
if (val != PEX_CSR0_LTSSM_L0)
|
|
|
|
return 1;
|
2012-09-21 12:12:52 +08:00
|
|
|
}
|
|
|
|
|
2009-01-09 05:55:39 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2013-04-08 16:15:28 +08:00
|
|
|
static int fsl_indirect_read_config(struct pci_bus *bus, unsigned int devfn,
|
|
|
|
int offset, int len, u32 *val)
|
|
|
|
{
|
|
|
|
struct pci_controller *hose = pci_bus_to_host(bus);
|
|
|
|
|
|
|
|
if (fsl_pcie_check_link(hose))
|
|
|
|
hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
|
|
|
|
else
|
|
|
|
hose->indirect_type &= ~PPC_INDIRECT_TYPE_NO_PCIE_LINK;
|
|
|
|
|
|
|
|
return indirect_read_config(bus, devfn, offset, len, val);
|
|
|
|
}
|
|
|
|
|
2013-06-17 22:02:41 +08:00
|
|
|
#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
|
|
|
|
|
|
|
|
static struct pci_ops fsl_indirect_pcie_ops =
|
2013-04-08 16:15:28 +08:00
|
|
|
{
|
|
|
|
.read = fsl_indirect_read_config,
|
|
|
|
.write = indirect_write_config,
|
|
|
|
};
|
|
|
|
|
2011-12-01 13:38:18 +08:00
|
|
|
#define MAX_PHYS_ADDR_BITS 40
|
|
|
|
static u64 pci64_dma_offset = 1ull << MAX_PHYS_ADDR_BITS;
|
|
|
|
|
2015-04-10 11:15:47 +08:00
|
|
|
#ifdef CONFIG_SWIOTLB
|
|
|
|
static void setup_swiotlb_ops(struct pci_controller *hose)
|
|
|
|
{
|
|
|
|
if (ppc_swiotlb_enable) {
|
|
|
|
hose->controller_ops.dma_dev_setup = pci_dma_dev_setup_swiotlb;
|
|
|
|
set_pci_dma_ops(&swiotlb_dma_ops);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#else
|
|
|
|
static inline void setup_swiotlb_ops(struct pci_controller *hose) {}
|
|
|
|
#endif
|
|
|
|
|
2011-12-01 13:38:18 +08:00
|
|
|
static int fsl_pci_dma_set_mask(struct device *dev, u64 dma_mask)
|
|
|
|
{
|
|
|
|
if (!dev->dma_mask || !dma_supported(dev, dma_mask))
|
|
|
|
return -EIO;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Fixup PCI devices that are able to DMA to above the physical
|
|
|
|
* address width of the SoC such that we can address any internal
|
|
|
|
* SoC address from across PCI if needed
|
|
|
|
*/
|
2013-12-05 20:01:20 +08:00
|
|
|
if ((dev_is_pci(dev)) &&
|
2011-12-01 13:38:18 +08:00
|
|
|
dma_mask >= DMA_BIT_MASK(MAX_PHYS_ADDR_BITS)) {
|
|
|
|
set_dma_ops(dev, &dma_direct_ops);
|
|
|
|
set_dma_offset(dev, pci64_dma_offset);
|
|
|
|
}
|
|
|
|
|
|
|
|
*dev->dma_mask = dma_mask;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-11-08 10:11:07 +08:00
|
|
|
static int setup_one_atmu(struct ccsr_pci __iomem *pci,
|
powerpc/fsl-pci: Better ATMU setup for 85xx/86xx
The code that sets up the outbound ATMU windows, which is used to map CPU
physical addresses into PCI bus addresses where BARs will be mapped, didn't
work so well.
For one, it leaked the ioremap() of the ATMU registers. Another small bug
was the high 20 bits of the PCI bus address were left as zero. It's legal
for prefetchable memory regions to be above 32 bits, so the high 20 bits
might not be zero.
Mainly, it couldn't handle ranges that were not a power of two in size or
were not naturally aligned. The ATMU windows have these requirements (size
& alignment), but the code didn't bother to check if the ranges it was
programming met them. If they didn't, the windows would silently be
programmed incorrectly.
This new code can handle ranges which are not power of two sized nor
naturally aligned. It simply splits the ranges into multiple valid ATMU
windows. As there are only four windows, pooly aligned or sized ranges
(which didn't even work before) may run out of windows. In this case an
error is printed and an effort is made to disable the unmapped resources.
An improvement that could be made would be to make use of the default
outbound window. Iff hose->pci_mem_offset is zero, then it's possible that
some or all of the ranges might not need an outbound window and could just
use the default window.
The default ATMU window can support a pci_mem_offset less than zero too,
but pci_mem_offset is unsigned. One could say the abilities allowed a
powerpc pci_controller is neither subset nor a superset of the abilities of
a Freescale PCIe controller. Thankfully, the most useful bits are in the
intersection of the two abilities.
Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-01-07 12:37:53 +08:00
|
|
|
unsigned int index, const struct resource *res,
|
|
|
|
resource_size_t offset)
|
|
|
|
{
|
|
|
|
resource_size_t pci_addr = res->start - offset;
|
|
|
|
resource_size_t phys_addr = res->start;
|
2011-06-10 00:13:32 +08:00
|
|
|
resource_size_t size = resource_size(res);
|
powerpc/fsl-pci: Better ATMU setup for 85xx/86xx
The code that sets up the outbound ATMU windows, which is used to map CPU
physical addresses into PCI bus addresses where BARs will be mapped, didn't
work so well.
For one, it leaked the ioremap() of the ATMU registers. Another small bug
was the high 20 bits of the PCI bus address were left as zero. It's legal
for prefetchable memory regions to be above 32 bits, so the high 20 bits
might not be zero.
Mainly, it couldn't handle ranges that were not a power of two in size or
were not naturally aligned. The ATMU windows have these requirements (size
& alignment), but the code didn't bother to check if the ranges it was
programming met them. If they didn't, the windows would silently be
programmed incorrectly.
This new code can handle ranges which are not power of two sized nor
naturally aligned. It simply splits the ranges into multiple valid ATMU
windows. As there are only four windows, pooly aligned or sized ranges
(which didn't even work before) may run out of windows. In this case an
error is printed and an effort is made to disable the unmapped resources.
An improvement that could be made would be to make use of the default
outbound window. Iff hose->pci_mem_offset is zero, then it's possible that
some or all of the ranges might not need an outbound window and could just
use the default window.
The default ATMU window can support a pci_mem_offset less than zero too,
but pci_mem_offset is unsigned. One could say the abilities allowed a
powerpc pci_controller is neither subset nor a superset of the abilities of
a Freescale PCIe controller. Thankfully, the most useful bits are in the
intersection of the two abilities.
Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-01-07 12:37:53 +08:00
|
|
|
u32 flags = 0x80044000; /* enable & mem R/W */
|
|
|
|
unsigned int i;
|
|
|
|
|
|
|
|
pr_debug("PCI MEM resource start 0x%016llx, size 0x%016llx.\n",
|
|
|
|
(u64)res->start, (u64)size);
|
|
|
|
|
2008-12-18 03:43:26 +08:00
|
|
|
if (res->flags & IORESOURCE_PREFETCH)
|
|
|
|
flags |= 0x10000000; /* enable relaxed ordering */
|
|
|
|
|
powerpc/fsl-pci: Better ATMU setup for 85xx/86xx
The code that sets up the outbound ATMU windows, which is used to map CPU
physical addresses into PCI bus addresses where BARs will be mapped, didn't
work so well.
For one, it leaked the ioremap() of the ATMU registers. Another small bug
was the high 20 bits of the PCI bus address were left as zero. It's legal
for prefetchable memory regions to be above 32 bits, so the high 20 bits
might not be zero.
Mainly, it couldn't handle ranges that were not a power of two in size or
were not naturally aligned. The ATMU windows have these requirements (size
& alignment), but the code didn't bother to check if the ranges it was
programming met them. If they didn't, the windows would silently be
programmed incorrectly.
This new code can handle ranges which are not power of two sized nor
naturally aligned. It simply splits the ranges into multiple valid ATMU
windows. As there are only four windows, pooly aligned or sized ranges
(which didn't even work before) may run out of windows. In this case an
error is printed and an effort is made to disable the unmapped resources.
An improvement that could be made would be to make use of the default
outbound window. Iff hose->pci_mem_offset is zero, then it's possible that
some or all of the ranges might not need an outbound window and could just
use the default window.
The default ATMU window can support a pci_mem_offset less than zero too,
but pci_mem_offset is unsigned. One could say the abilities allowed a
powerpc pci_controller is neither subset nor a superset of the abilities of
a Freescale PCIe controller. Thankfully, the most useful bits are in the
intersection of the two abilities.
Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-01-07 12:37:53 +08:00
|
|
|
for (i = 0; size > 0; i++) {
|
2014-09-17 20:15:37 +08:00
|
|
|
unsigned int bits = min_t(u32, ilog2(size),
|
powerpc/fsl-pci: Better ATMU setup for 85xx/86xx
The code that sets up the outbound ATMU windows, which is used to map CPU
physical addresses into PCI bus addresses where BARs will be mapped, didn't
work so well.
For one, it leaked the ioremap() of the ATMU registers. Another small bug
was the high 20 bits of the PCI bus address were left as zero. It's legal
for prefetchable memory regions to be above 32 bits, so the high 20 bits
might not be zero.
Mainly, it couldn't handle ranges that were not a power of two in size or
were not naturally aligned. The ATMU windows have these requirements (size
& alignment), but the code didn't bother to check if the ranges it was
programming met them. If they didn't, the windows would silently be
programmed incorrectly.
This new code can handle ranges which are not power of two sized nor
naturally aligned. It simply splits the ranges into multiple valid ATMU
windows. As there are only four windows, pooly aligned or sized ranges
(which didn't even work before) may run out of windows. In this case an
error is printed and an effort is made to disable the unmapped resources.
An improvement that could be made would be to make use of the default
outbound window. Iff hose->pci_mem_offset is zero, then it's possible that
some or all of the ranges might not need an outbound window and could just
use the default window.
The default ATMU window can support a pci_mem_offset less than zero too,
but pci_mem_offset is unsigned. One could say the abilities allowed a
powerpc pci_controller is neither subset nor a superset of the abilities of
a Freescale PCIe controller. Thankfully, the most useful bits are in the
intersection of the two abilities.
Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-01-07 12:37:53 +08:00
|
|
|
__ffs(pci_addr | phys_addr));
|
|
|
|
|
|
|
|
if (index + i >= 5)
|
|
|
|
return -1;
|
|
|
|
|
|
|
|
out_be32(&pci->pow[index + i].potar, pci_addr >> 12);
|
|
|
|
out_be32(&pci->pow[index + i].potear, (u64)pci_addr >> 44);
|
|
|
|
out_be32(&pci->pow[index + i].powbar, phys_addr >> 12);
|
|
|
|
out_be32(&pci->pow[index + i].powar, flags | (bits - 1));
|
|
|
|
|
|
|
|
pci_addr += (resource_size_t)1U << bits;
|
|
|
|
phys_addr += (resource_size_t)1U << bits;
|
|
|
|
size -= (resource_size_t)1U << bits;
|
|
|
|
}
|
|
|
|
|
|
|
|
return i;
|
|
|
|
}
|
|
|
|
|
2007-07-10 18:46:35 +08:00
|
|
|
/* atmu setup for fsl pci/pcie controller */
|
2013-03-14 03:07:15 +08:00
|
|
|
static void setup_pci_atmu(struct pci_controller *hose)
|
2006-06-18 06:52:48 +08:00
|
|
|
{
|
2013-03-14 03:07:15 +08:00
|
|
|
struct ccsr_pci __iomem *pci = hose->private_data;
|
2011-02-24 17:35:04 +08:00
|
|
|
int i, j, n, mem_log, win_idx = 3, start_idx = 1, end_idx = 4;
|
2009-05-09 04:05:23 +08:00
|
|
|
u64 mem, sz, paddr_hi = 0;
|
2013-05-06 11:40:40 +08:00
|
|
|
u64 offset = 0, paddr_lo = ULLONG_MAX;
|
2009-05-09 04:05:23 +08:00
|
|
|
u32 pcicsrbar = 0, pcicsrbar_sz;
|
|
|
|
u32 piwar = PIWAR_EN | PIWAR_PF | PIWAR_TGI_LOCAL |
|
|
|
|
PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
|
2012-11-15 06:37:12 +08:00
|
|
|
const char *name = hose->dn->full_name;
|
2011-12-14 04:51:59 +08:00
|
|
|
const u64 *reg;
|
|
|
|
int len;
|
2006-06-18 06:52:48 +08:00
|
|
|
|
2012-09-03 17:22:10 +08:00
|
|
|
if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
|
|
|
|
if (in_be32(&pci->block_rev1) >= PCIE_IP_REV_2_2) {
|
|
|
|
win_idx = 2;
|
|
|
|
start_idx = 0;
|
|
|
|
end_idx = 3;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
powerpc/fsl-pci: Better ATMU setup for 85xx/86xx
The code that sets up the outbound ATMU windows, which is used to map CPU
physical addresses into PCI bus addresses where BARs will be mapped, didn't
work so well.
For one, it leaked the ioremap() of the ATMU registers. Another small bug
was the high 20 bits of the PCI bus address were left as zero. It's legal
for prefetchable memory regions to be above 32 bits, so the high 20 bits
might not be zero.
Mainly, it couldn't handle ranges that were not a power of two in size or
were not naturally aligned. The ATMU windows have these requirements (size
& alignment), but the code didn't bother to check if the ranges it was
programming met them. If they didn't, the windows would silently be
programmed incorrectly.
This new code can handle ranges which are not power of two sized nor
naturally aligned. It simply splits the ranges into multiple valid ATMU
windows. As there are only four windows, pooly aligned or sized ranges
(which didn't even work before) may run out of windows. In this case an
error is printed and an effort is made to disable the unmapped resources.
An improvement that could be made would be to make use of the default
outbound window. Iff hose->pci_mem_offset is zero, then it's possible that
some or all of the ranges might not need an outbound window and could just
use the default window.
The default ATMU window can support a pci_mem_offset less than zero too,
but pci_mem_offset is unsigned. One could say the abilities allowed a
powerpc pci_controller is neither subset nor a superset of the abilities of
a Freescale PCIe controller. Thankfully, the most useful bits are in the
intersection of the two abilities.
Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-01-07 12:37:53 +08:00
|
|
|
/* Disable all windows (except powar0 since it's ignored) */
|
2007-07-10 18:46:35 +08:00
|
|
|
for(i = 1; i < 5; i++)
|
|
|
|
out_be32(&pci->pow[i].powar, 0);
|
2011-02-24 17:35:04 +08:00
|
|
|
for (i = start_idx; i < end_idx; i++)
|
2007-07-10 18:46:35 +08:00
|
|
|
out_be32(&pci->piw[i].piwar, 0);
|
|
|
|
|
|
|
|
/* Setup outbound MEM window */
|
powerpc/fsl-pci: Better ATMU setup for 85xx/86xx
The code that sets up the outbound ATMU windows, which is used to map CPU
physical addresses into PCI bus addresses where BARs will be mapped, didn't
work so well.
For one, it leaked the ioremap() of the ATMU registers. Another small bug
was the high 20 bits of the PCI bus address were left as zero. It's legal
for prefetchable memory regions to be above 32 bits, so the high 20 bits
might not be zero.
Mainly, it couldn't handle ranges that were not a power of two in size or
were not naturally aligned. The ATMU windows have these requirements (size
& alignment), but the code didn't bother to check if the ranges it was
programming met them. If they didn't, the windows would silently be
programmed incorrectly.
This new code can handle ranges which are not power of two sized nor
naturally aligned. It simply splits the ranges into multiple valid ATMU
windows. As there are only four windows, pooly aligned or sized ranges
(which didn't even work before) may run out of windows. In this case an
error is printed and an effort is made to disable the unmapped resources.
An improvement that could be made would be to make use of the default
outbound window. Iff hose->pci_mem_offset is zero, then it's possible that
some or all of the ranges might not need an outbound window and could just
use the default window.
The default ATMU window can support a pci_mem_offset less than zero too,
but pci_mem_offset is unsigned. One could say the abilities allowed a
powerpc pci_controller is neither subset nor a superset of the abilities of
a Freescale PCIe controller. Thankfully, the most useful bits are in the
intersection of the two abilities.
Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-01-07 12:37:53 +08:00
|
|
|
for(i = 0, j = 1; i < 3; i++) {
|
|
|
|
if (!(hose->mem_resources[i].flags & IORESOURCE_MEM))
|
|
|
|
continue;
|
|
|
|
|
2009-05-09 04:05:23 +08:00
|
|
|
paddr_lo = min(paddr_lo, (u64)hose->mem_resources[i].start);
|
|
|
|
paddr_hi = max(paddr_hi, (u64)hose->mem_resources[i].end);
|
|
|
|
|
2013-05-06 11:40:40 +08:00
|
|
|
/* We assume all memory resources have the same offset */
|
|
|
|
offset = hose->mem_offset[i];
|
|
|
|
n = setup_one_atmu(pci, j, &hose->mem_resources[i], offset);
|
powerpc/fsl-pci: Better ATMU setup for 85xx/86xx
The code that sets up the outbound ATMU windows, which is used to map CPU
physical addresses into PCI bus addresses where BARs will be mapped, didn't
work so well.
For one, it leaked the ioremap() of the ATMU registers. Another small bug
was the high 20 bits of the PCI bus address were left as zero. It's legal
for prefetchable memory regions to be above 32 bits, so the high 20 bits
might not be zero.
Mainly, it couldn't handle ranges that were not a power of two in size or
were not naturally aligned. The ATMU windows have these requirements (size
& alignment), but the code didn't bother to check if the ranges it was
programming met them. If they didn't, the windows would silently be
programmed incorrectly.
This new code can handle ranges which are not power of two sized nor
naturally aligned. It simply splits the ranges into multiple valid ATMU
windows. As there are only four windows, pooly aligned or sized ranges
(which didn't even work before) may run out of windows. In this case an
error is printed and an effort is made to disable the unmapped resources.
An improvement that could be made would be to make use of the default
outbound window. Iff hose->pci_mem_offset is zero, then it's possible that
some or all of the ranges might not need an outbound window and could just
use the default window.
The default ATMU window can support a pci_mem_offset less than zero too,
but pci_mem_offset is unsigned. One could say the abilities allowed a
powerpc pci_controller is neither subset nor a superset of the abilities of
a Freescale PCIe controller. Thankfully, the most useful bits are in the
intersection of the two abilities.
Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-01-07 12:37:53 +08:00
|
|
|
|
|
|
|
if (n < 0 || j >= 5) {
|
|
|
|
pr_err("Ran out of outbound PCI ATMUs for resource %d!\n", i);
|
|
|
|
hose->mem_resources[i].flags |= IORESOURCE_DISABLED;
|
|
|
|
} else
|
|
|
|
j += n;
|
|
|
|
}
|
2007-07-10 18:46:35 +08:00
|
|
|
|
|
|
|
/* Setup outbound IO window */
|
powerpc/fsl-pci: Better ATMU setup for 85xx/86xx
The code that sets up the outbound ATMU windows, which is used to map CPU
physical addresses into PCI bus addresses where BARs will be mapped, didn't
work so well.
For one, it leaked the ioremap() of the ATMU registers. Another small bug
was the high 20 bits of the PCI bus address were left as zero. It's legal
for prefetchable memory regions to be above 32 bits, so the high 20 bits
might not be zero.
Mainly, it couldn't handle ranges that were not a power of two in size or
were not naturally aligned. The ATMU windows have these requirements (size
& alignment), but the code didn't bother to check if the ranges it was
programming met them. If they didn't, the windows would silently be
programmed incorrectly.
This new code can handle ranges which are not power of two sized nor
naturally aligned. It simply splits the ranges into multiple valid ATMU
windows. As there are only four windows, pooly aligned or sized ranges
(which didn't even work before) may run out of windows. In this case an
error is printed and an effort is made to disable the unmapped resources.
An improvement that could be made would be to make use of the default
outbound window. Iff hose->pci_mem_offset is zero, then it's possible that
some or all of the ranges might not need an outbound window and could just
use the default window.
The default ATMU window can support a pci_mem_offset less than zero too,
but pci_mem_offset is unsigned. One could say the abilities allowed a
powerpc pci_controller is neither subset nor a superset of the abilities of
a Freescale PCIe controller. Thankfully, the most useful bits are in the
intersection of the two abilities.
Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-01-07 12:37:53 +08:00
|
|
|
if (hose->io_resource.flags & IORESOURCE_IO) {
|
|
|
|
if (j >= 5) {
|
|
|
|
pr_err("Ran out of outbound PCI ATMUs for IO resource\n");
|
|
|
|
} else {
|
|
|
|
pr_debug("PCI IO resource start 0x%016llx, size 0x%016llx, "
|
|
|
|
"phy base 0x%016llx.\n",
|
2011-06-10 00:13:32 +08:00
|
|
|
(u64)hose->io_resource.start,
|
|
|
|
(u64)resource_size(&hose->io_resource),
|
|
|
|
(u64)hose->io_base_phys);
|
powerpc/fsl-pci: Better ATMU setup for 85xx/86xx
The code that sets up the outbound ATMU windows, which is used to map CPU
physical addresses into PCI bus addresses where BARs will be mapped, didn't
work so well.
For one, it leaked the ioremap() of the ATMU registers. Another small bug
was the high 20 bits of the PCI bus address were left as zero. It's legal
for prefetchable memory regions to be above 32 bits, so the high 20 bits
might not be zero.
Mainly, it couldn't handle ranges that were not a power of two in size or
were not naturally aligned. The ATMU windows have these requirements (size
& alignment), but the code didn't bother to check if the ranges it was
programming met them. If they didn't, the windows would silently be
programmed incorrectly.
This new code can handle ranges which are not power of two sized nor
naturally aligned. It simply splits the ranges into multiple valid ATMU
windows. As there are only four windows, pooly aligned or sized ranges
(which didn't even work before) may run out of windows. In this case an
error is printed and an effort is made to disable the unmapped resources.
An improvement that could be made would be to make use of the default
outbound window. Iff hose->pci_mem_offset is zero, then it's possible that
some or all of the ranges might not need an outbound window and could just
use the default window.
The default ATMU window can support a pci_mem_offset less than zero too,
but pci_mem_offset is unsigned. One could say the abilities allowed a
powerpc pci_controller is neither subset nor a superset of the abilities of
a Freescale PCIe controller. Thankfully, the most useful bits are in the
intersection of the two abilities.
Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-01-07 12:37:53 +08:00
|
|
|
out_be32(&pci->pow[j].potar, (hose->io_resource.start >> 12));
|
|
|
|
out_be32(&pci->pow[j].potear, 0);
|
|
|
|
out_be32(&pci->pow[j].powbar, (hose->io_base_phys >> 12));
|
|
|
|
/* Enable, IO R/W */
|
|
|
|
out_be32(&pci->pow[j].powar, 0x80088000
|
2013-03-29 21:06:17 +08:00
|
|
|
| (ilog2(hose->io_resource.end
|
powerpc/fsl-pci: Better ATMU setup for 85xx/86xx
The code that sets up the outbound ATMU windows, which is used to map CPU
physical addresses into PCI bus addresses where BARs will be mapped, didn't
work so well.
For one, it leaked the ioremap() of the ATMU registers. Another small bug
was the high 20 bits of the PCI bus address were left as zero. It's legal
for prefetchable memory regions to be above 32 bits, so the high 20 bits
might not be zero.
Mainly, it couldn't handle ranges that were not a power of two in size or
were not naturally aligned. The ATMU windows have these requirements (size
& alignment), but the code didn't bother to check if the ranges it was
programming met them. If they didn't, the windows would silently be
programmed incorrectly.
This new code can handle ranges which are not power of two sized nor
naturally aligned. It simply splits the ranges into multiple valid ATMU
windows. As there are only four windows, pooly aligned or sized ranges
(which didn't even work before) may run out of windows. In this case an
error is printed and an effort is made to disable the unmapped resources.
An improvement that could be made would be to make use of the default
outbound window. Iff hose->pci_mem_offset is zero, then it's possible that
some or all of the ranges might not need an outbound window and could just
use the default window.
The default ATMU window can support a pci_mem_offset less than zero too,
but pci_mem_offset is unsigned. One could say the abilities allowed a
powerpc pci_controller is neither subset nor a superset of the abilities of
a Freescale PCIe controller. Thankfully, the most useful bits are in the
intersection of the two abilities.
Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-01-07 12:37:53 +08:00
|
|
|
- hose->io_resource.start + 1) - 1));
|
|
|
|
}
|
2007-07-10 18:46:35 +08:00
|
|
|
}
|
|
|
|
|
2009-05-09 04:05:23 +08:00
|
|
|
/* convert to pci address space */
|
2013-05-06 11:40:40 +08:00
|
|
|
paddr_hi -= offset;
|
|
|
|
paddr_lo -= offset;
|
2009-05-09 04:05:23 +08:00
|
|
|
|
|
|
|
if (paddr_hi == paddr_lo) {
|
|
|
|
pr_err("%s: No outbound window space\n", name);
|
2013-04-13 15:14:41 +08:00
|
|
|
return;
|
2009-05-09 04:05:23 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
if (paddr_lo == 0) {
|
|
|
|
pr_err("%s: No space for inbound window\n", name);
|
2013-04-13 15:14:41 +08:00
|
|
|
return;
|
2009-05-09 04:05:23 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/* setup PCSRBAR/PEXCSRBAR */
|
|
|
|
early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, 0xffffffff);
|
|
|
|
early_read_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, &pcicsrbar_sz);
|
|
|
|
pcicsrbar_sz = ~pcicsrbar_sz + 1;
|
|
|
|
|
|
|
|
if (paddr_hi < (0x100000000ull - pcicsrbar_sz) ||
|
|
|
|
(paddr_lo > 0x100000000ull))
|
|
|
|
pcicsrbar = 0x100000000ull - pcicsrbar_sz;
|
|
|
|
else
|
|
|
|
pcicsrbar = (paddr_lo - pcicsrbar_sz) & -pcicsrbar_sz;
|
|
|
|
early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, pcicsrbar);
|
|
|
|
|
|
|
|
paddr_lo = min(paddr_lo, (u64)pcicsrbar);
|
|
|
|
|
|
|
|
pr_info("%s: PCICSRBAR @ 0x%x\n", name, pcicsrbar);
|
|
|
|
|
|
|
|
/* Setup inbound mem window */
|
2010-07-12 12:36:09 +08:00
|
|
|
mem = memblock_end_of_DRAM();
|
2011-12-14 04:51:59 +08:00
|
|
|
|
|
|
|
/*
|
|
|
|
* The msi-address-64 property, if it exists, indicates the physical
|
|
|
|
* address of the MSIIR register. Normally, this register is located
|
|
|
|
* inside CCSR, so the ATMU that covers all of CCSR is used. But if
|
|
|
|
* this property exists, then we normally need to create a new ATMU
|
|
|
|
* for it. For now, however, we cheat. The only entity that creates
|
|
|
|
* this property is the Freescale hypervisor, and the address is
|
|
|
|
* specified in the partition configuration. Typically, the address
|
|
|
|
* is located in the page immediately after the end of DDR. If so, we
|
|
|
|
* can avoid allocating a new ATMU by extending the DDR ATMU by one
|
|
|
|
* page.
|
|
|
|
*/
|
|
|
|
reg = of_get_property(hose->dn, "msi-address-64", &len);
|
|
|
|
if (reg && (len == sizeof(u64))) {
|
|
|
|
u64 address = be64_to_cpup(reg);
|
|
|
|
|
|
|
|
if ((address >= mem) && (address < (mem + PAGE_SIZE))) {
|
|
|
|
pr_info("%s: extending DDR ATMU to cover MSIIR", name);
|
|
|
|
mem += PAGE_SIZE;
|
|
|
|
} else {
|
|
|
|
/* TODO: Create a new ATMU for MSIIR */
|
|
|
|
pr_warn("%s: msi-address-64 address of %llx is "
|
|
|
|
"unsupported\n", name, address);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2009-05-09 04:05:23 +08:00
|
|
|
sz = min(mem, paddr_lo);
|
2013-03-29 21:06:17 +08:00
|
|
|
mem_log = ilog2(sz);
|
2009-05-09 04:05:23 +08:00
|
|
|
|
|
|
|
/* PCIe can overmap inbound & outbound since RX & TX are separated */
|
|
|
|
if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
|
|
|
|
/* Size window to exact size if power-of-two or one size up */
|
|
|
|
if ((1ull << mem_log) != mem) {
|
2013-05-21 20:04:59 +08:00
|
|
|
mem_log++;
|
2009-05-09 04:05:23 +08:00
|
|
|
if ((1ull << mem_log) > mem)
|
|
|
|
pr_info("%s: Setting PCI inbound window "
|
|
|
|
"greater than memory size\n", name);
|
|
|
|
}
|
|
|
|
|
2011-02-24 17:35:04 +08:00
|
|
|
piwar |= ((mem_log - 1) & PIWAR_SZ_MASK);
|
2009-05-09 04:05:23 +08:00
|
|
|
|
|
|
|
/* Setup inbound memory window */
|
|
|
|
out_be32(&pci->piw[win_idx].pitar, 0x00000000);
|
|
|
|
out_be32(&pci->piw[win_idx].piwbar, 0x00000000);
|
|
|
|
out_be32(&pci->piw[win_idx].piwar, piwar);
|
|
|
|
win_idx--;
|
|
|
|
|
|
|
|
hose->dma_window_base_cur = 0x00000000;
|
|
|
|
hose->dma_window_size = (resource_size_t)sz;
|
2011-12-01 13:38:18 +08:00
|
|
|
|
|
|
|
/*
|
|
|
|
* if we have >4G of memory setup second PCI inbound window to
|
|
|
|
* let devices that are 64-bit address capable to work w/o
|
|
|
|
* SWIOTLB and access the full range of memory
|
|
|
|
*/
|
|
|
|
if (sz != mem) {
|
2013-03-29 21:06:17 +08:00
|
|
|
mem_log = ilog2(mem);
|
2011-12-01 13:38:18 +08:00
|
|
|
|
|
|
|
/* Size window up if we dont fit in exact power-of-2 */
|
|
|
|
if ((1ull << mem_log) != mem)
|
|
|
|
mem_log++;
|
|
|
|
|
|
|
|
piwar = (piwar & ~PIWAR_SZ_MASK) | (mem_log - 1);
|
|
|
|
|
|
|
|
/* Setup inbound memory window */
|
|
|
|
out_be32(&pci->piw[win_idx].pitar, 0x00000000);
|
|
|
|
out_be32(&pci->piw[win_idx].piwbear,
|
|
|
|
pci64_dma_offset >> 44);
|
|
|
|
out_be32(&pci->piw[win_idx].piwbar,
|
|
|
|
pci64_dma_offset >> 12);
|
|
|
|
out_be32(&pci->piw[win_idx].piwar, piwar);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* install our own dma_set_mask handler to fixup dma_ops
|
|
|
|
* and dma_offset
|
|
|
|
*/
|
|
|
|
ppc_md.dma_set_mask = fsl_pci_dma_set_mask;
|
|
|
|
|
|
|
|
pr_info("%s: Setup 64-bit PCI DMA window\n", name);
|
|
|
|
}
|
2009-05-09 04:05:23 +08:00
|
|
|
} else {
|
|
|
|
u64 paddr = 0;
|
|
|
|
|
|
|
|
/* Setup inbound memory window */
|
|
|
|
out_be32(&pci->piw[win_idx].pitar, paddr >> 12);
|
|
|
|
out_be32(&pci->piw[win_idx].piwbar, paddr >> 12);
|
|
|
|
out_be32(&pci->piw[win_idx].piwar, (piwar | (mem_log - 1)));
|
|
|
|
win_idx--;
|
|
|
|
|
|
|
|
paddr += 1ull << mem_log;
|
|
|
|
sz -= 1ull << mem_log;
|
|
|
|
|
|
|
|
if (sz) {
|
2013-03-29 21:06:17 +08:00
|
|
|
mem_log = ilog2(sz);
|
2009-05-09 04:05:23 +08:00
|
|
|
piwar |= (mem_log - 1);
|
|
|
|
|
|
|
|
out_be32(&pci->piw[win_idx].pitar, paddr >> 12);
|
|
|
|
out_be32(&pci->piw[win_idx].piwbar, paddr >> 12);
|
|
|
|
out_be32(&pci->piw[win_idx].piwar, piwar);
|
|
|
|
win_idx--;
|
|
|
|
|
|
|
|
paddr += 1ull << mem_log;
|
|
|
|
}
|
|
|
|
|
|
|
|
hose->dma_window_base_cur = 0x00000000;
|
|
|
|
hose->dma_window_size = (resource_size_t)paddr;
|
|
|
|
}
|
powerpc/fsl-pci: Better ATMU setup for 85xx/86xx
The code that sets up the outbound ATMU windows, which is used to map CPU
physical addresses into PCI bus addresses where BARs will be mapped, didn't
work so well.
For one, it leaked the ioremap() of the ATMU registers. Another small bug
was the high 20 bits of the PCI bus address were left as zero. It's legal
for prefetchable memory regions to be above 32 bits, so the high 20 bits
might not be zero.
Mainly, it couldn't handle ranges that were not a power of two in size or
were not naturally aligned. The ATMU windows have these requirements (size
& alignment), but the code didn't bother to check if the ranges it was
programming met them. If they didn't, the windows would silently be
programmed incorrectly.
This new code can handle ranges which are not power of two sized nor
naturally aligned. It simply splits the ranges into multiple valid ATMU
windows. As there are only four windows, pooly aligned or sized ranges
(which didn't even work before) may run out of windows. In this case an
error is printed and an effort is made to disable the unmapped resources.
An improvement that could be made would be to make use of the default
outbound window. Iff hose->pci_mem_offset is zero, then it's possible that
some or all of the ranges might not need an outbound window and could just
use the default window.
The default ATMU window can support a pci_mem_offset less than zero too,
but pci_mem_offset is unsigned. One could say the abilities allowed a
powerpc pci_controller is neither subset nor a superset of the abilities of
a Freescale PCIe controller. Thankfully, the most useful bits are in the
intersection of the two abilities.
Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-01-07 12:37:53 +08:00
|
|
|
|
2009-05-09 04:05:23 +08:00
|
|
|
if (hose->dma_window_size < mem) {
|
2013-05-21 20:05:00 +08:00
|
|
|
#ifdef CONFIG_SWIOTLB
|
|
|
|
ppc_swiotlb_enable = 1;
|
|
|
|
#else
|
2009-05-09 04:05:23 +08:00
|
|
|
pr_err("%s: ERROR: Memory size exceeds PCI ATMU ability to "
|
|
|
|
"map - enable CONFIG_SWIOTLB to avoid dma errors.\n",
|
|
|
|
name);
|
|
|
|
#endif
|
|
|
|
/* adjusting outbound windows could reclaim space in mem map */
|
|
|
|
if (paddr_hi < 0xffffffffull)
|
|
|
|
pr_warning("%s: WARNING: Outbound window cfg leaves "
|
|
|
|
"gaps in memory map. Adjusting the memory map "
|
|
|
|
"could reduce unnecessary bounce buffering.\n",
|
|
|
|
name);
|
|
|
|
|
|
|
|
pr_info("%s: DMA window size is 0x%llx\n", name,
|
|
|
|
(u64)hose->dma_window_size);
|
|
|
|
}
|
2006-06-18 06:52:48 +08:00
|
|
|
}
|
|
|
|
|
2008-12-30 00:40:32 +08:00
|
|
|
static void __init setup_pci_cmd(struct pci_controller *hose)
|
2006-06-18 06:52:48 +08:00
|
|
|
{
|
|
|
|
u16 cmd;
|
2007-07-21 05:29:09 +08:00
|
|
|
int cap_x;
|
|
|
|
|
2006-06-18 06:52:48 +08:00
|
|
|
early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd);
|
|
|
|
cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
|
2007-07-10 18:46:35 +08:00
|
|
|
| PCI_COMMAND_IO;
|
2006-06-18 06:52:48 +08:00
|
|
|
early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd);
|
2007-07-21 05:29:09 +08:00
|
|
|
|
|
|
|
cap_x = early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX);
|
|
|
|
if (cap_x) {
|
|
|
|
int pci_x_cmd = cap_x + PCI_X_CMD;
|
|
|
|
cmd = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
|
|
|
|
| PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
|
|
|
|
early_write_config_word(hose, 0, 0, pci_x_cmd, cmd);
|
|
|
|
} else {
|
|
|
|
early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
|
|
|
|
}
|
2006-06-28 13:37:45 +08:00
|
|
|
}
|
|
|
|
|
2007-07-20 04:29:53 +08:00
|
|
|
void fsl_pcibios_fixup_bus(struct pci_bus *bus)
|
|
|
|
{
|
2009-04-30 11:10:08 +08:00
|
|
|
struct pci_controller *hose = pci_bus_to_host(bus);
|
2012-02-15 02:22:20 +08:00
|
|
|
int i, is_pcie = 0, no_link;
|
|
|
|
|
|
|
|
/* The root complex bridge comes up with bogus resources,
|
|
|
|
* we copy the PHB ones in.
|
|
|
|
*
|
|
|
|
* With the current generic PCI code, the PHB bus no longer
|
|
|
|
* has bus->resource[0..4] set, so things are a bit more
|
|
|
|
* tricky.
|
|
|
|
*/
|
|
|
|
|
|
|
|
if (fsl_pcie_bus_fixup)
|
|
|
|
is_pcie = early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP);
|
|
|
|
no_link = !!(hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK);
|
|
|
|
|
|
|
|
if (bus->parent == hose->bus && (is_pcie || no_link)) {
|
|
|
|
for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; ++i) {
|
2008-01-15 07:02:19 +08:00
|
|
|
struct resource *res = bus->resource[i];
|
2012-02-15 02:22:20 +08:00
|
|
|
struct resource *par;
|
|
|
|
|
|
|
|
if (!res)
|
|
|
|
continue;
|
|
|
|
if (i == 0)
|
|
|
|
par = &hose->io_resource;
|
|
|
|
else if (i < 4)
|
|
|
|
par = &hose->mem_resources[i-1];
|
|
|
|
else par = NULL;
|
|
|
|
|
|
|
|
res->start = par ? par->start : 0;
|
|
|
|
res->end = par ? par->end : 0;
|
|
|
|
res->flags = par ? par->flags : 0;
|
2007-07-20 04:29:53 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-12-16 02:39:26 +08:00
|
|
|
int fsl_add_bridge(struct platform_device *pdev, int is_primary)
|
2006-06-18 06:52:48 +08:00
|
|
|
{
|
|
|
|
int len;
|
|
|
|
struct pci_controller *hose;
|
|
|
|
struct resource rsrc;
|
2006-07-12 13:39:42 +08:00
|
|
|
const int *bus_range;
|
2012-09-24 13:50:52 +08:00
|
|
|
u8 hdr_type, progif;
|
2013-01-14 19:28:00 +08:00
|
|
|
struct device_node *dev;
|
2013-03-14 03:07:15 +08:00
|
|
|
struct ccsr_pci __iomem *pci;
|
2013-01-14 19:28:00 +08:00
|
|
|
|
|
|
|
dev = pdev->dev.of_node;
|
2006-06-18 06:52:48 +08:00
|
|
|
|
2011-03-31 15:01:09 +08:00
|
|
|
if (!of_device_is_available(dev)) {
|
|
|
|
pr_warning("%s: disabled\n", dev->full_name);
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
|
2007-07-10 18:46:35 +08:00
|
|
|
pr_debug("Adding PCI host bridge %s\n", dev->full_name);
|
2006-06-18 06:52:48 +08:00
|
|
|
|
|
|
|
/* Fetch host bridge registers address */
|
2007-07-10 18:46:35 +08:00
|
|
|
if (of_address_to_resource(dev, 0, &rsrc)) {
|
|
|
|
printk(KERN_WARNING "Can't get pci register base!");
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
2006-06-18 06:52:48 +08:00
|
|
|
|
|
|
|
/* Get bus range if any */
|
2007-04-03 20:26:41 +08:00
|
|
|
bus_range = of_get_property(dev, "bus-range", &len);
|
2006-06-18 06:52:48 +08:00
|
|
|
if (bus_range == NULL || len < 2 * sizeof(int))
|
|
|
|
printk(KERN_WARNING "Can't get bus-range for %s, assume"
|
2007-07-10 18:46:35 +08:00
|
|
|
" bus 0\n", dev->full_name);
|
2006-06-18 06:52:48 +08:00
|
|
|
|
2011-07-12 22:25:51 +08:00
|
|
|
pci_add_flags(PCI_REASSIGN_ALL_BUS);
|
2007-06-27 14:56:50 +08:00
|
|
|
hose = pcibios_alloc_controller(dev);
|
2006-06-18 06:52:48 +08:00
|
|
|
if (!hose)
|
|
|
|
return -ENOMEM;
|
2007-06-27 14:56:50 +08:00
|
|
|
|
2013-01-14 19:28:00 +08:00
|
|
|
/* set platform device as the parent */
|
|
|
|
hose->parent = &pdev->dev;
|
2006-06-18 06:52:48 +08:00
|
|
|
hose->first_busno = bus_range ? bus_range[0] : 0x0;
|
2007-05-22 11:38:26 +08:00
|
|
|
hose->last_busno = bus_range ? bus_range[1] : 0xff;
|
2006-06-18 06:52:48 +08:00
|
|
|
|
2013-03-14 03:07:15 +08:00
|
|
|
pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n",
|
|
|
|
(u64)rsrc.start, (u64)resource_size(&rsrc));
|
|
|
|
|
|
|
|
pci = hose->private_data = ioremap(rsrc.start, resource_size(&rsrc));
|
|
|
|
if (!hose->private_data)
|
|
|
|
goto no_bridge;
|
|
|
|
|
2013-06-17 22:02:41 +08:00
|
|
|
setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
|
|
|
|
PPC_INDIRECT_TYPE_BIG_ENDIAN);
|
2011-05-23 18:23:25 +08:00
|
|
|
|
2013-03-14 03:07:15 +08:00
|
|
|
if (in_be32(&pci->block_rev1) < PCIE_IP_REV_3_0)
|
|
|
|
hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK;
|
|
|
|
|
2012-09-24 13:50:52 +08:00
|
|
|
if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
|
2013-06-17 22:02:41 +08:00
|
|
|
/* use fsl_indirect_read_config for PCIe */
|
|
|
|
hose->ops = &fsl_indirect_pcie_ops;
|
2012-09-24 13:50:52 +08:00
|
|
|
/* For PCIE read HEADER_TYPE to identify controler mode */
|
|
|
|
early_read_config_byte(hose, 0, 0, PCI_HEADER_TYPE, &hdr_type);
|
|
|
|
if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE)
|
|
|
|
goto no_bridge;
|
|
|
|
|
|
|
|
} else {
|
|
|
|
/* For PCI read PROG to identify controller mode */
|
|
|
|
early_read_config_byte(hose, 0, 0, PCI_CLASS_PROG, &progif);
|
2014-08-27 05:46:11 +08:00
|
|
|
if ((progif & 1) &&
|
|
|
|
!of_property_read_bool(dev, "fsl,pci-agent-force-enum"))
|
2012-09-24 13:50:52 +08:00
|
|
|
goto no_bridge;
|
2011-05-23 18:23:25 +08:00
|
|
|
}
|
|
|
|
|
2007-07-10 18:46:35 +08:00
|
|
|
setup_pci_cmd(hose);
|
2006-06-18 06:52:48 +08:00
|
|
|
|
2007-07-10 18:46:35 +08:00
|
|
|
/* check PCI express link status */
|
2007-07-12 02:31:58 +08:00
|
|
|
if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
|
2007-07-25 13:29:53 +08:00
|
|
|
hose->indirect_type |= PPC_INDIRECT_TYPE_EXT_REG |
|
2007-07-12 02:31:58 +08:00
|
|
|
PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS;
|
2013-03-14 03:07:15 +08:00
|
|
|
if (fsl_pcie_check_link(hose))
|
2007-07-12 02:31:58 +08:00
|
|
|
hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
|
|
|
|
}
|
2006-06-18 06:52:48 +08:00
|
|
|
|
2007-11-20 09:47:55 +08:00
|
|
|
printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
|
2007-07-10 18:46:35 +08:00
|
|
|
"Firmware bus number: %d->%d\n",
|
|
|
|
(unsigned long long)rsrc.start, hose->first_busno,
|
|
|
|
hose->last_busno);
|
2006-06-18 06:52:48 +08:00
|
|
|
|
2007-07-10 18:46:35 +08:00
|
|
|
pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
|
2006-06-18 06:52:48 +08:00
|
|
|
hose, hose->cfg_addr, hose->cfg_data);
|
|
|
|
|
|
|
|
/* Interpret the "ranges" property */
|
|
|
|
/* This also maps the I/O region and sets isa_io/mem_base */
|
2007-07-10 18:46:35 +08:00
|
|
|
pci_process_bridge_OF_ranges(hose, dev, is_primary);
|
2006-06-18 06:52:48 +08:00
|
|
|
|
|
|
|
/* Setup PEX window registers */
|
2013-03-14 03:07:15 +08:00
|
|
|
setup_pci_atmu(hose);
|
2006-06-18 06:52:48 +08:00
|
|
|
|
2015-04-10 11:15:47 +08:00
|
|
|
/* Set up controller operations */
|
|
|
|
setup_swiotlb_ops(hose);
|
|
|
|
|
2006-06-18 06:52:48 +08:00
|
|
|
return 0;
|
2012-09-24 13:50:52 +08:00
|
|
|
|
|
|
|
no_bridge:
|
2013-03-14 03:07:15 +08:00
|
|
|
iounmap(hose->private_data);
|
2012-09-24 13:50:52 +08:00
|
|
|
/* unmap cfg_data & cfg_addr separately if not on same page */
|
|
|
|
if (((unsigned long)hose->cfg_data & PAGE_MASK) !=
|
|
|
|
((unsigned long)hose->cfg_addr & PAGE_MASK))
|
|
|
|
iounmap(hose->cfg_data);
|
|
|
|
iounmap(hose->cfg_addr);
|
|
|
|
pcibios_free_controller(hose);
|
|
|
|
return -ENODEV;
|
2006-06-18 06:52:48 +08:00
|
|
|
}
|
2009-10-17 07:31:48 +08:00
|
|
|
#endif /* CONFIG_FSL_SOC_BOOKE || CONFIG_PPC_86xx */
|
2008-06-27 01:07:57 +08:00
|
|
|
|
2013-08-02 16:46:25 +08:00
|
|
|
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID,
|
|
|
|
quirk_fsl_pcie_early);
|
2009-01-09 05:55:39 +08:00
|
|
|
|
2011-05-20 08:56:50 +08:00
|
|
|
#if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x)
|
2009-01-09 05:55:39 +08:00
|
|
|
struct mpc83xx_pcie_priv {
|
|
|
|
void __iomem *cfg_type0;
|
|
|
|
void __iomem *cfg_type1;
|
|
|
|
u32 dev_base;
|
|
|
|
};
|
|
|
|
|
2010-08-05 15:45:08 +08:00
|
|
|
struct pex_inbound_window {
|
|
|
|
u32 ar;
|
|
|
|
u32 tar;
|
|
|
|
u32 barl;
|
|
|
|
u32 barh;
|
|
|
|
};
|
|
|
|
|
2009-01-09 05:55:39 +08:00
|
|
|
/*
|
|
|
|
* With the convention of u-boot, the PCIE outbound window 0 serves
|
|
|
|
* as configuration transactions outbound.
|
|
|
|
*/
|
|
|
|
#define PEX_OUTWIN0_BAR 0xCA4
|
|
|
|
#define PEX_OUTWIN0_TAL 0xCA8
|
|
|
|
#define PEX_OUTWIN0_TAH 0xCAC
|
2010-08-05 15:45:08 +08:00
|
|
|
#define PEX_RC_INWIN_BASE 0xE60
|
|
|
|
#define PEX_RCIWARn_EN 0x1
|
2009-01-09 05:55:39 +08:00
|
|
|
|
|
|
|
static int mpc83xx_pcie_exclude_device(struct pci_bus *bus, unsigned int devfn)
|
|
|
|
{
|
2009-04-30 11:10:08 +08:00
|
|
|
struct pci_controller *hose = pci_bus_to_host(bus);
|
2009-01-09 05:55:39 +08:00
|
|
|
|
|
|
|
if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK)
|
|
|
|
return PCIBIOS_DEVICE_NOT_FOUND;
|
|
|
|
/*
|
|
|
|
* Workaround for the HW bug: for Type 0 configure transactions the
|
|
|
|
* PCI-E controller does not check the device number bits and just
|
|
|
|
* assumes that the device number bits are 0.
|
|
|
|
*/
|
|
|
|
if (bus->number == hose->first_busno ||
|
|
|
|
bus->primary == hose->first_busno) {
|
|
|
|
if (devfn & 0xf8)
|
|
|
|
return PCIBIOS_DEVICE_NOT_FOUND;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (ppc_md.pci_exclude_device) {
|
|
|
|
if (ppc_md.pci_exclude_device(hose, bus->number, devfn))
|
|
|
|
return PCIBIOS_DEVICE_NOT_FOUND;
|
|
|
|
}
|
|
|
|
|
|
|
|
return PCIBIOS_SUCCESSFUL;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void __iomem *mpc83xx_pcie_remap_cfg(struct pci_bus *bus,
|
|
|
|
unsigned int devfn, int offset)
|
|
|
|
{
|
2009-04-30 11:10:08 +08:00
|
|
|
struct pci_controller *hose = pci_bus_to_host(bus);
|
2009-01-09 05:55:39 +08:00
|
|
|
struct mpc83xx_pcie_priv *pcie = hose->dn->data;
|
2009-12-08 06:54:35 +08:00
|
|
|
u32 dev_base = bus->number << 24 | devfn << 16;
|
2009-01-09 05:55:39 +08:00
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = mpc83xx_pcie_exclude_device(bus, devfn);
|
|
|
|
if (ret)
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
offset &= 0xfff;
|
|
|
|
|
|
|
|
/* Type 0 */
|
|
|
|
if (bus->number == hose->first_busno)
|
|
|
|
return pcie->cfg_type0 + offset;
|
|
|
|
|
|
|
|
if (pcie->dev_base == dev_base)
|
|
|
|
goto mapped;
|
|
|
|
|
|
|
|
out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, dev_base);
|
|
|
|
|
|
|
|
pcie->dev_base = dev_base;
|
|
|
|
mapped:
|
|
|
|
return pcie->cfg_type1 + offset;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int mpc83xx_pcie_write_config(struct pci_bus *bus, unsigned int devfn,
|
|
|
|
int offset, int len, u32 val)
|
|
|
|
{
|
2009-12-08 06:54:35 +08:00
|
|
|
struct pci_controller *hose = pci_bus_to_host(bus);
|
2009-01-09 05:55:39 +08:00
|
|
|
|
2009-12-08 06:54:35 +08:00
|
|
|
/* PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS */
|
|
|
|
if (offset == PCI_PRIMARY_BUS && bus->number == hose->first_busno)
|
|
|
|
val &= 0xffffff00;
|
|
|
|
|
2015-01-10 10:34:44 +08:00
|
|
|
return pci_generic_config_write(bus, devfn, offset, len, val);
|
2009-01-09 05:55:39 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static struct pci_ops mpc83xx_pcie_ops = {
|
2015-01-10 10:34:44 +08:00
|
|
|
.map_bus = mpc83xx_pcie_remap_cfg,
|
|
|
|
.read = pci_generic_config_read,
|
2009-01-09 05:55:39 +08:00
|
|
|
.write = mpc83xx_pcie_write_config,
|
|
|
|
};
|
|
|
|
|
|
|
|
static int __init mpc83xx_pcie_setup(struct pci_controller *hose,
|
|
|
|
struct resource *reg)
|
|
|
|
{
|
|
|
|
struct mpc83xx_pcie_priv *pcie;
|
|
|
|
u32 cfg_bar;
|
|
|
|
int ret = -ENOMEM;
|
|
|
|
|
|
|
|
pcie = zalloc_maybe_bootmem(sizeof(*pcie), GFP_KERNEL);
|
|
|
|
if (!pcie)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
pcie->cfg_type0 = ioremap(reg->start, resource_size(reg));
|
|
|
|
if (!pcie->cfg_type0)
|
|
|
|
goto err0;
|
|
|
|
|
|
|
|
cfg_bar = in_le32(pcie->cfg_type0 + PEX_OUTWIN0_BAR);
|
|
|
|
if (!cfg_bar) {
|
|
|
|
/* PCI-E isn't configured. */
|
|
|
|
ret = -ENODEV;
|
|
|
|
goto err1;
|
|
|
|
}
|
|
|
|
|
|
|
|
pcie->cfg_type1 = ioremap(cfg_bar, 0x1000);
|
|
|
|
if (!pcie->cfg_type1)
|
|
|
|
goto err1;
|
|
|
|
|
|
|
|
WARN_ON(hose->dn->data);
|
|
|
|
hose->dn->data = pcie;
|
|
|
|
hose->ops = &mpc83xx_pcie_ops;
|
2013-03-14 03:07:15 +08:00
|
|
|
hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK;
|
2009-01-09 05:55:39 +08:00
|
|
|
|
|
|
|
out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAH, 0);
|
|
|
|
out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, 0);
|
|
|
|
|
2013-03-14 03:07:15 +08:00
|
|
|
if (fsl_pcie_check_link(hose))
|
2009-01-09 05:55:39 +08:00
|
|
|
hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
err1:
|
|
|
|
iounmap(pcie->cfg_type0);
|
|
|
|
err0:
|
|
|
|
kfree(pcie);
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
}
|
|
|
|
|
2008-06-27 01:07:57 +08:00
|
|
|
int __init mpc83xx_add_bridge(struct device_node *dev)
|
|
|
|
{
|
2009-01-09 05:55:39 +08:00
|
|
|
int ret;
|
2008-06-27 01:07:57 +08:00
|
|
|
int len;
|
|
|
|
struct pci_controller *hose;
|
2008-10-08 03:00:18 +08:00
|
|
|
struct resource rsrc_reg;
|
|
|
|
struct resource rsrc_cfg;
|
2008-06-27 01:07:57 +08:00
|
|
|
const int *bus_range;
|
2008-10-08 03:00:18 +08:00
|
|
|
int primary;
|
2008-06-27 01:07:57 +08:00
|
|
|
|
2010-08-05 15:45:08 +08:00
|
|
|
is_mpc83xx_pci = 1;
|
|
|
|
|
2009-01-09 05:55:39 +08:00
|
|
|
if (!of_device_is_available(dev)) {
|
|
|
|
pr_warning("%s: disabled by the firmware.\n",
|
|
|
|
dev->full_name);
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
2008-06-27 01:07:57 +08:00
|
|
|
pr_debug("Adding PCI host bridge %s\n", dev->full_name);
|
|
|
|
|
|
|
|
/* Fetch host bridge registers address */
|
2008-10-08 03:00:18 +08:00
|
|
|
if (of_address_to_resource(dev, 0, &rsrc_reg)) {
|
|
|
|
printk(KERN_WARNING "Can't get pci register base!\n");
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
|
|
|
memset(&rsrc_cfg, 0, sizeof(rsrc_cfg));
|
|
|
|
|
|
|
|
if (of_address_to_resource(dev, 1, &rsrc_cfg)) {
|
|
|
|
printk(KERN_WARNING
|
|
|
|
"No pci config register base in dev tree, "
|
|
|
|
"using default\n");
|
|
|
|
/*
|
|
|
|
* MPC83xx supports up to two host controllers
|
|
|
|
* one at 0x8500 has config space registers at 0x8300
|
|
|
|
* one at 0x8600 has config space registers at 0x8380
|
|
|
|
*/
|
|
|
|
if ((rsrc_reg.start & 0xfffff) == 0x8500)
|
|
|
|
rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8300;
|
|
|
|
else if ((rsrc_reg.start & 0xfffff) == 0x8600)
|
|
|
|
rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8380;
|
|
|
|
}
|
|
|
|
/*
|
|
|
|
* Controller at offset 0x8500 is primary
|
|
|
|
*/
|
|
|
|
if ((rsrc_reg.start & 0xfffff) == 0x8500)
|
|
|
|
primary = 1;
|
|
|
|
else
|
|
|
|
primary = 0;
|
2008-06-27 01:07:57 +08:00
|
|
|
|
|
|
|
/* Get bus range if any */
|
|
|
|
bus_range = of_get_property(dev, "bus-range", &len);
|
|
|
|
if (bus_range == NULL || len < 2 * sizeof(int)) {
|
|
|
|
printk(KERN_WARNING "Can't get bus-range for %s, assume"
|
|
|
|
" bus 0\n", dev->full_name);
|
|
|
|
}
|
|
|
|
|
2011-07-12 22:25:51 +08:00
|
|
|
pci_add_flags(PCI_REASSIGN_ALL_BUS);
|
2008-06-27 01:07:57 +08:00
|
|
|
hose = pcibios_alloc_controller(dev);
|
|
|
|
if (!hose)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
hose->first_busno = bus_range ? bus_range[0] : 0;
|
|
|
|
hose->last_busno = bus_range ? bus_range[1] : 0xff;
|
|
|
|
|
2009-01-09 05:55:39 +08:00
|
|
|
if (of_device_is_compatible(dev, "fsl,mpc8314-pcie")) {
|
|
|
|
ret = mpc83xx_pcie_setup(hose, &rsrc_reg);
|
|
|
|
if (ret)
|
|
|
|
goto err0;
|
|
|
|
} else {
|
2013-06-17 22:02:41 +08:00
|
|
|
setup_indirect_pci(hose, rsrc_cfg.start,
|
|
|
|
rsrc_cfg.start + 4, 0);
|
2009-01-09 05:55:39 +08:00
|
|
|
}
|
2008-06-27 01:07:57 +08:00
|
|
|
|
2008-10-08 05:13:18 +08:00
|
|
|
printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
|
2008-06-27 01:07:57 +08:00
|
|
|
"Firmware bus number: %d->%d\n",
|
2008-10-08 03:00:18 +08:00
|
|
|
(unsigned long long)rsrc_reg.start, hose->first_busno,
|
2008-06-27 01:07:57 +08:00
|
|
|
hose->last_busno);
|
|
|
|
|
|
|
|
pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
|
|
|
|
hose, hose->cfg_addr, hose->cfg_data);
|
|
|
|
|
|
|
|
/* Interpret the "ranges" property */
|
|
|
|
/* This also maps the I/O region and sets isa_io/mem_base */
|
|
|
|
pci_process_bridge_OF_ranges(hose, dev, primary);
|
|
|
|
|
|
|
|
return 0;
|
2009-01-09 05:55:39 +08:00
|
|
|
err0:
|
|
|
|
pcibios_free_controller(hose);
|
|
|
|
return ret;
|
2008-06-27 01:07:57 +08:00
|
|
|
}
|
|
|
|
#endif /* CONFIG_PPC_83xx */
|
2010-08-05 15:45:08 +08:00
|
|
|
|
|
|
|
u64 fsl_pci_immrbar_base(struct pci_controller *hose)
|
|
|
|
{
|
|
|
|
#ifdef CONFIG_PPC_83xx
|
|
|
|
if (is_mpc83xx_pci) {
|
|
|
|
struct mpc83xx_pcie_priv *pcie = hose->dn->data;
|
|
|
|
struct pex_inbound_window *in;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
/* Walk the Root Complex Inbound windows to match IMMR base */
|
|
|
|
in = pcie->cfg_type0 + PEX_RC_INWIN_BASE;
|
|
|
|
for (i = 0; i < 4; i++) {
|
|
|
|
/* not enabled, skip */
|
2014-07-20 05:49:59 +08:00
|
|
|
if (!(in_le32(&in[i].ar) & PEX_RCIWARn_EN))
|
|
|
|
continue;
|
2010-08-05 15:45:08 +08:00
|
|
|
|
|
|
|
if (get_immrbase() == in_le32(&in[i].tar))
|
|
|
|
return (u64)in_le32(&in[i].barh) << 32 |
|
|
|
|
in_le32(&in[i].barl);
|
|
|
|
}
|
|
|
|
|
|
|
|
printk(KERN_WARNING "could not find PCI BAR matching IMMR\n");
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
|
|
|
|
if (!is_mpc83xx_pci) {
|
|
|
|
u32 base;
|
|
|
|
|
|
|
|
pci_bus_read_config_dword(hose->bus,
|
|
|
|
PCI_DEVFN(0, 0), PCI_BASE_ADDRESS_0, &base);
|
2014-01-20 18:54:20 +08:00
|
|
|
|
|
|
|
/*
|
|
|
|
* For PEXCSRBAR, bit 3-0 indicate prefetchable and
|
|
|
|
* address type. So when getting base address, these
|
|
|
|
* bits should be masked
|
|
|
|
*/
|
|
|
|
base &= PCI_BASE_ADDRESS_MEM_MASK;
|
|
|
|
|
2010-08-05 15:45:08 +08:00
|
|
|
return base;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
2012-07-11 08:26:47 +08:00
|
|
|
|
2013-04-28 13:20:08 +08:00
|
|
|
#ifdef CONFIG_E500
|
|
|
|
static int mcheck_handle_load(struct pt_regs *regs, u32 inst)
|
|
|
|
{
|
|
|
|
unsigned int rd, ra, rb, d;
|
|
|
|
|
|
|
|
rd = get_rt(inst);
|
|
|
|
ra = get_ra(inst);
|
|
|
|
rb = get_rb(inst);
|
|
|
|
d = get_d(inst);
|
|
|
|
|
|
|
|
switch (get_op(inst)) {
|
|
|
|
case 31:
|
|
|
|
switch (get_xop(inst)) {
|
|
|
|
case OP_31_XOP_LWZX:
|
|
|
|
case OP_31_XOP_LWBRX:
|
|
|
|
regs->gpr[rd] = 0xffffffff;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case OP_31_XOP_LWZUX:
|
|
|
|
regs->gpr[rd] = 0xffffffff;
|
|
|
|
regs->gpr[ra] += regs->gpr[rb];
|
|
|
|
break;
|
|
|
|
|
|
|
|
case OP_31_XOP_LBZX:
|
|
|
|
regs->gpr[rd] = 0xff;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case OP_31_XOP_LBZUX:
|
|
|
|
regs->gpr[rd] = 0xff;
|
|
|
|
regs->gpr[ra] += regs->gpr[rb];
|
|
|
|
break;
|
|
|
|
|
|
|
|
case OP_31_XOP_LHZX:
|
|
|
|
case OP_31_XOP_LHBRX:
|
|
|
|
regs->gpr[rd] = 0xffff;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case OP_31_XOP_LHZUX:
|
|
|
|
regs->gpr[rd] = 0xffff;
|
|
|
|
regs->gpr[ra] += regs->gpr[rb];
|
|
|
|
break;
|
|
|
|
|
|
|
|
case OP_31_XOP_LHAX:
|
|
|
|
regs->gpr[rd] = ~0UL;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case OP_31_XOP_LHAUX:
|
|
|
|
regs->gpr[rd] = ~0UL;
|
|
|
|
regs->gpr[ra] += regs->gpr[rb];
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
case OP_LWZ:
|
|
|
|
regs->gpr[rd] = 0xffffffff;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case OP_LWZU:
|
|
|
|
regs->gpr[rd] = 0xffffffff;
|
|
|
|
regs->gpr[ra] += (s16)d;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case OP_LBZ:
|
|
|
|
regs->gpr[rd] = 0xff;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case OP_LBZU:
|
|
|
|
regs->gpr[rd] = 0xff;
|
|
|
|
regs->gpr[ra] += (s16)d;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case OP_LHZ:
|
|
|
|
regs->gpr[rd] = 0xffff;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case OP_LHZU:
|
|
|
|
regs->gpr[rd] = 0xffff;
|
|
|
|
regs->gpr[ra] += (s16)d;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case OP_LHA:
|
|
|
|
regs->gpr[rd] = ~0UL;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case OP_LHAU:
|
|
|
|
regs->gpr[rd] = ~0UL;
|
|
|
|
regs->gpr[ra] += (s16)d;
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int is_in_pci_mem_space(phys_addr_t addr)
|
|
|
|
{
|
|
|
|
struct pci_controller *hose;
|
|
|
|
struct resource *res;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
list_for_each_entry(hose, &hose_list, list_node) {
|
|
|
|
if (!(hose->indirect_type & PPC_INDIRECT_TYPE_EXT_REG))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
for (i = 0; i < 3; i++) {
|
|
|
|
res = &hose->mem_resources[i];
|
|
|
|
if ((res->flags & IORESOURCE_MEM) &&
|
|
|
|
addr >= res->start && addr <= res->end)
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int fsl_pci_mcheck_exception(struct pt_regs *regs)
|
|
|
|
{
|
|
|
|
u32 inst;
|
|
|
|
int ret;
|
|
|
|
phys_addr_t addr = 0;
|
|
|
|
|
|
|
|
/* Let KVM/QEMU deal with the exception */
|
|
|
|
if (regs->msr & MSR_GS)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
#ifdef CONFIG_PHYS_64BIT
|
|
|
|
addr = mfspr(SPRN_MCARU);
|
|
|
|
addr <<= 32;
|
|
|
|
#endif
|
|
|
|
addr += mfspr(SPRN_MCAR);
|
|
|
|
|
|
|
|
if (is_in_pci_mem_space(addr)) {
|
|
|
|
if (user_mode(regs)) {
|
|
|
|
pagefault_disable();
|
|
|
|
ret = get_user(regs->nip, &inst);
|
|
|
|
pagefault_enable();
|
|
|
|
} else {
|
|
|
|
ret = probe_kernel_address(regs->nip, inst);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (mcheck_handle_load(regs, inst)) {
|
|
|
|
regs->nip += 4;
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2012-07-11 08:26:47 +08:00
|
|
|
#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
|
|
|
|
static const struct of_device_id pci_ids[] = {
|
|
|
|
{ .compatible = "fsl,mpc8540-pci", },
|
|
|
|
{ .compatible = "fsl,mpc8548-pcie", },
|
|
|
|
{ .compatible = "fsl,mpc8610-pci", },
|
|
|
|
{ .compatible = "fsl,mpc8641-pcie", },
|
2013-12-25 18:06:56 +08:00
|
|
|
{ .compatible = "fsl,qoriq-pcie", },
|
powerpc/85xx: fix various PCI node compatible strings
Fix and/or improve the compatible strings of the PCI device tree nodes for
some Freescale SOCs. This fixes some issues and improves consistency among
the SOCs.
Specifically:
1) The P1022 has a v1 PCIe controller, so the compatible property should just
say "fsl,mpc8548-pcie". U-Boot does not look for "fsl,p1022-pcie", so it
wasn't fixing up the node.
2) The P4080 has a v2.1 PCIe controller, so add that version-specific string
to the device tree. Update the kernel to also look for that string.
Currently, the kernel looks for "fsl,p4080-pcie" specifically, but
eventually that check should be deleted.
3) The P1010 device tree claims compatibility with v2.2 and v2.3, but that's
redundant. No other device tree does this. Remove the v2.2 string.
4) The kernel looks for both "fsl,p1023-pcie" and "fsl,qoriq-pcie-v2.2",
even though the P1023 device trees has always included both strings. Remove
the search for "fsl,p1023-pcie".
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2013-01-18 06:34:32 +08:00
|
|
|
{ .compatible = "fsl,qoriq-pcie-v2.1", },
|
|
|
|
{ .compatible = "fsl,qoriq-pcie-v2.2", },
|
|
|
|
{ .compatible = "fsl,qoriq-pcie-v2.3", },
|
|
|
|
{ .compatible = "fsl,qoriq-pcie-v2.4", },
|
2012-09-21 12:12:52 +08:00
|
|
|
{ .compatible = "fsl,qoriq-pcie-v3.0", },
|
powerpc/85xx: fix various PCI node compatible strings
Fix and/or improve the compatible strings of the PCI device tree nodes for
some Freescale SOCs. This fixes some issues and improves consistency among
the SOCs.
Specifically:
1) The P1022 has a v1 PCIe controller, so the compatible property should just
say "fsl,mpc8548-pcie". U-Boot does not look for "fsl,p1022-pcie", so it
wasn't fixing up the node.
2) The P4080 has a v2.1 PCIe controller, so add that version-specific string
to the device tree. Update the kernel to also look for that string.
Currently, the kernel looks for "fsl,p4080-pcie" specifically, but
eventually that check should be deleted.
3) The P1010 device tree claims compatibility with v2.2 and v2.3, but that's
redundant. No other device tree does this. Remove the v2.2 string.
4) The kernel looks for both "fsl,p1023-pcie" and "fsl,qoriq-pcie-v2.2",
even though the P1023 device trees has always included both strings. Remove
the search for "fsl,p1023-pcie".
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2013-01-18 06:34:32 +08:00
|
|
|
|
|
|
|
/*
|
|
|
|
* The following entries are for compatibility with older device
|
|
|
|
* trees.
|
|
|
|
*/
|
2012-07-11 08:26:47 +08:00
|
|
|
{ .compatible = "fsl,p1022-pcie", },
|
|
|
|
{ .compatible = "fsl,p4080-pcie", },
|
powerpc/85xx: fix various PCI node compatible strings
Fix and/or improve the compatible strings of the PCI device tree nodes for
some Freescale SOCs. This fixes some issues and improves consistency among
the SOCs.
Specifically:
1) The P1022 has a v1 PCIe controller, so the compatible property should just
say "fsl,mpc8548-pcie". U-Boot does not look for "fsl,p1022-pcie", so it
wasn't fixing up the node.
2) The P4080 has a v2.1 PCIe controller, so add that version-specific string
to the device tree. Update the kernel to also look for that string.
Currently, the kernel looks for "fsl,p4080-pcie" specifically, but
eventually that check should be deleted.
3) The P1010 device tree claims compatibility with v2.2 and v2.3, but that's
redundant. No other device tree does this. Remove the v2.2 string.
4) The kernel looks for both "fsl,p1023-pcie" and "fsl,qoriq-pcie-v2.2",
even though the P1023 device trees has always included both strings. Remove
the search for "fsl,p1023-pcie".
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2013-01-18 06:34:32 +08:00
|
|
|
|
2012-07-11 08:26:47 +08:00
|
|
|
{},
|
|
|
|
};
|
|
|
|
|
|
|
|
struct device_node *fsl_pci_primary;
|
|
|
|
|
2012-08-28 15:44:08 +08:00
|
|
|
void fsl_pci_assign_primary(void)
|
2012-07-11 08:26:47 +08:00
|
|
|
{
|
2012-08-28 15:44:08 +08:00
|
|
|
struct device_node *np;
|
2012-07-11 08:26:47 +08:00
|
|
|
|
|
|
|
/* Callers can specify the primary bus using other means. */
|
2012-08-28 15:44:08 +08:00
|
|
|
if (fsl_pci_primary)
|
|
|
|
return;
|
|
|
|
|
|
|
|
/* If a PCI host bridge contains an ISA node, it's primary. */
|
|
|
|
np = of_find_node_by_type(NULL, "isa");
|
|
|
|
while ((fsl_pci_primary = of_get_parent(np))) {
|
|
|
|
of_node_put(np);
|
|
|
|
np = fsl_pci_primary;
|
|
|
|
|
|
|
|
if (of_match_node(pci_ids, np) && of_device_is_available(np))
|
|
|
|
return;
|
2012-07-11 08:26:47 +08:00
|
|
|
}
|
|
|
|
|
2012-08-28 15:44:08 +08:00
|
|
|
/*
|
|
|
|
* If there's no PCI host bridge with ISA, arbitrarily
|
|
|
|
* designate one as primary. This can go away once
|
|
|
|
* various bugs with primary-less systems are fixed.
|
|
|
|
*/
|
|
|
|
for_each_matching_node(np, pci_ids) {
|
|
|
|
if (of_device_is_available(np)) {
|
|
|
|
fsl_pci_primary = np;
|
|
|
|
of_node_put(np);
|
|
|
|
return;
|
2012-07-11 08:26:47 +08:00
|
|
|
}
|
|
|
|
}
|
2012-08-28 15:44:08 +08:00
|
|
|
}
|
|
|
|
|
fsl/pci: The new pci suspend/resume implementation
If we do nothing in suspend/resume, some platform PCIe ip-block
can't guarantee the link back to L0 state from sleep, then, when
we read the EP device will hang. Only we send pme turnoff message
in pci controller suspend, and send pme exit message in resume, the
link state will be normal.
When we send pme turnoff message in pci controller suspend, the
links will into l2/l3 ready, then, host cannot communicate with
ep device, but pci-driver will call back EP device to save them
state. So we need to change platform_driver->suspend/resume to
syscore->suspend/resume.
So the new suspend/resume implementation, send pme turnoff message
in suspend, and send pme exit message in resume. And add a PME handler,
to response PME & message interrupt.
Change platform_driver->suspend/resume to syscore->suspend/resume.
pci-driver will call back EP device, to save EP state in
pci_pm_suspend_noirq, so we need to keep the link, until
pci_pm_suspend_noirq finish.
Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
2014-03-20 11:19:37 +08:00
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
|
|
static irqreturn_t fsl_pci_pme_handle(int irq, void *dev_id)
|
2012-08-28 15:44:08 +08:00
|
|
|
{
|
fsl/pci: The new pci suspend/resume implementation
If we do nothing in suspend/resume, some platform PCIe ip-block
can't guarantee the link back to L0 state from sleep, then, when
we read the EP device will hang. Only we send pme turnoff message
in pci controller suspend, and send pme exit message in resume, the
link state will be normal.
When we send pme turnoff message in pci controller suspend, the
links will into l2/l3 ready, then, host cannot communicate with
ep device, but pci-driver will call back EP device to save them
state. So we need to change platform_driver->suspend/resume to
syscore->suspend/resume.
So the new suspend/resume implementation, send pme turnoff message
in suspend, and send pme exit message in resume. And add a PME handler,
to response PME & message interrupt.
Change platform_driver->suspend/resume to syscore->suspend/resume.
pci-driver will call back EP device, to save EP state in
pci_pm_suspend_noirq, so we need to keep the link, until
pci_pm_suspend_noirq finish.
Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
2014-03-20 11:19:37 +08:00
|
|
|
struct pci_controller *hose = dev_id;
|
|
|
|
struct ccsr_pci __iomem *pci = hose->private_data;
|
|
|
|
u32 dr;
|
2012-08-28 15:44:08 +08:00
|
|
|
|
fsl/pci: The new pci suspend/resume implementation
If we do nothing in suspend/resume, some platform PCIe ip-block
can't guarantee the link back to L0 state from sleep, then, when
we read the EP device will hang. Only we send pme turnoff message
in pci controller suspend, and send pme exit message in resume, the
link state will be normal.
When we send pme turnoff message in pci controller suspend, the
links will into l2/l3 ready, then, host cannot communicate with
ep device, but pci-driver will call back EP device to save them
state. So we need to change platform_driver->suspend/resume to
syscore->suspend/resume.
So the new suspend/resume implementation, send pme turnoff message
in suspend, and send pme exit message in resume. And add a PME handler,
to response PME & message interrupt.
Change platform_driver->suspend/resume to syscore->suspend/resume.
pci-driver will call back EP device, to save EP state in
pci_pm_suspend_noirq, so we need to keep the link, until
pci_pm_suspend_noirq finish.
Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
2014-03-20 11:19:37 +08:00
|
|
|
dr = in_be32(&pci->pex_pme_mes_dr);
|
|
|
|
if (!dr)
|
|
|
|
return IRQ_NONE;
|
2012-07-11 08:26:47 +08:00
|
|
|
|
fsl/pci: The new pci suspend/resume implementation
If we do nothing in suspend/resume, some platform PCIe ip-block
can't guarantee the link back to L0 state from sleep, then, when
we read the EP device will hang. Only we send pme turnoff message
in pci controller suspend, and send pme exit message in resume, the
link state will be normal.
When we send pme turnoff message in pci controller suspend, the
links will into l2/l3 ready, then, host cannot communicate with
ep device, but pci-driver will call back EP device to save them
state. So we need to change platform_driver->suspend/resume to
syscore->suspend/resume.
So the new suspend/resume implementation, send pme turnoff message
in suspend, and send pme exit message in resume. And add a PME handler,
to response PME & message interrupt.
Change platform_driver->suspend/resume to syscore->suspend/resume.
pci-driver will call back EP device, to save EP state in
pci_pm_suspend_noirq, so we need to keep the link, until
pci_pm_suspend_noirq finish.
Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
2014-03-20 11:19:37 +08:00
|
|
|
out_be32(&pci->pex_pme_mes_dr, dr);
|
2012-08-28 15:44:08 +08:00
|
|
|
|
fsl/pci: The new pci suspend/resume implementation
If we do nothing in suspend/resume, some platform PCIe ip-block
can't guarantee the link back to L0 state from sleep, then, when
we read the EP device will hang. Only we send pme turnoff message
in pci controller suspend, and send pme exit message in resume, the
link state will be normal.
When we send pme turnoff message in pci controller suspend, the
links will into l2/l3 ready, then, host cannot communicate with
ep device, but pci-driver will call back EP device to save them
state. So we need to change platform_driver->suspend/resume to
syscore->suspend/resume.
So the new suspend/resume implementation, send pme turnoff message
in suspend, and send pme exit message in resume. And add a PME handler,
to response PME & message interrupt.
Change platform_driver->suspend/resume to syscore->suspend/resume.
pci-driver will call back EP device, to save EP state in
pci_pm_suspend_noirq, so we need to keep the link, until
pci_pm_suspend_noirq finish.
Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
2014-03-20 11:19:37 +08:00
|
|
|
return IRQ_HANDLED;
|
2012-08-28 15:44:08 +08:00
|
|
|
}
|
|
|
|
|
fsl/pci: The new pci suspend/resume implementation
If we do nothing in suspend/resume, some platform PCIe ip-block
can't guarantee the link back to L0 state from sleep, then, when
we read the EP device will hang. Only we send pme turnoff message
in pci controller suspend, and send pme exit message in resume, the
link state will be normal.
When we send pme turnoff message in pci controller suspend, the
links will into l2/l3 ready, then, host cannot communicate with
ep device, but pci-driver will call back EP device to save them
state. So we need to change platform_driver->suspend/resume to
syscore->suspend/resume.
So the new suspend/resume implementation, send pme turnoff message
in suspend, and send pme exit message in resume. And add a PME handler,
to response PME & message interrupt.
Change platform_driver->suspend/resume to syscore->suspend/resume.
pci-driver will call back EP device, to save EP state in
pci_pm_suspend_noirq, so we need to keep the link, until
pci_pm_suspend_noirq finish.
Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
2014-03-20 11:19:37 +08:00
|
|
|
static int fsl_pci_pme_probe(struct pci_controller *hose)
|
2012-11-08 10:11:07 +08:00
|
|
|
{
|
fsl/pci: The new pci suspend/resume implementation
If we do nothing in suspend/resume, some platform PCIe ip-block
can't guarantee the link back to L0 state from sleep, then, when
we read the EP device will hang. Only we send pme turnoff message
in pci controller suspend, and send pme exit message in resume, the
link state will be normal.
When we send pme turnoff message in pci controller suspend, the
links will into l2/l3 ready, then, host cannot communicate with
ep device, but pci-driver will call back EP device to save them
state. So we need to change platform_driver->suspend/resume to
syscore->suspend/resume.
So the new suspend/resume implementation, send pme turnoff message
in suspend, and send pme exit message in resume. And add a PME handler,
to response PME & message interrupt.
Change platform_driver->suspend/resume to syscore->suspend/resume.
pci-driver will call back EP device, to save EP state in
pci_pm_suspend_noirq, so we need to keep the link, until
pci_pm_suspend_noirq finish.
Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
2014-03-20 11:19:37 +08:00
|
|
|
struct ccsr_pci __iomem *pci;
|
|
|
|
struct pci_dev *dev;
|
|
|
|
int pme_irq;
|
|
|
|
int res;
|
|
|
|
u16 pms;
|
2012-11-08 10:11:07 +08:00
|
|
|
|
fsl/pci: The new pci suspend/resume implementation
If we do nothing in suspend/resume, some platform PCIe ip-block
can't guarantee the link back to L0 state from sleep, then, when
we read the EP device will hang. Only we send pme turnoff message
in pci controller suspend, and send pme exit message in resume, the
link state will be normal.
When we send pme turnoff message in pci controller suspend, the
links will into l2/l3 ready, then, host cannot communicate with
ep device, but pci-driver will call back EP device to save them
state. So we need to change platform_driver->suspend/resume to
syscore->suspend/resume.
So the new suspend/resume implementation, send pme turnoff message
in suspend, and send pme exit message in resume. And add a PME handler,
to response PME & message interrupt.
Change platform_driver->suspend/resume to syscore->suspend/resume.
pci-driver will call back EP device, to save EP state in
pci_pm_suspend_noirq, so we need to keep the link, until
pci_pm_suspend_noirq finish.
Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
2014-03-20 11:19:37 +08:00
|
|
|
/* Get hose's pci_dev */
|
|
|
|
dev = list_first_entry(&hose->bus->devices, typeof(*dev), bus_list);
|
|
|
|
|
|
|
|
/* PME Disable */
|
|
|
|
pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pms);
|
|
|
|
pms &= ~PCI_PM_CTRL_PME_ENABLE;
|
|
|
|
pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pms);
|
|
|
|
|
|
|
|
pme_irq = irq_of_parse_and_map(hose->dn, 0);
|
|
|
|
if (!pme_irq) {
|
|
|
|
dev_err(&dev->dev, "Failed to map PME interrupt.\n");
|
|
|
|
|
|
|
|
return -ENXIO;
|
|
|
|
}
|
|
|
|
|
|
|
|
res = devm_request_irq(hose->parent, pme_irq,
|
|
|
|
fsl_pci_pme_handle,
|
|
|
|
IRQF_SHARED,
|
|
|
|
"[PCI] PME", hose);
|
|
|
|
if (res < 0) {
|
2015-05-20 22:54:02 +08:00
|
|
|
dev_err(&dev->dev, "Unable to request irq %d for PME\n", pme_irq);
|
fsl/pci: The new pci suspend/resume implementation
If we do nothing in suspend/resume, some platform PCIe ip-block
can't guarantee the link back to L0 state from sleep, then, when
we read the EP device will hang. Only we send pme turnoff message
in pci controller suspend, and send pme exit message in resume, the
link state will be normal.
When we send pme turnoff message in pci controller suspend, the
links will into l2/l3 ready, then, host cannot communicate with
ep device, but pci-driver will call back EP device to save them
state. So we need to change platform_driver->suspend/resume to
syscore->suspend/resume.
So the new suspend/resume implementation, send pme turnoff message
in suspend, and send pme exit message in resume. And add a PME handler,
to response PME & message interrupt.
Change platform_driver->suspend/resume to syscore->suspend/resume.
pci-driver will call back EP device, to save EP state in
pci_pm_suspend_noirq, so we need to keep the link, until
pci_pm_suspend_noirq finish.
Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
2014-03-20 11:19:37 +08:00
|
|
|
irq_dispose_mapping(pme_irq);
|
2012-11-08 10:11:07 +08:00
|
|
|
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
|
fsl/pci: The new pci suspend/resume implementation
If we do nothing in suspend/resume, some platform PCIe ip-block
can't guarantee the link back to L0 state from sleep, then, when
we read the EP device will hang. Only we send pme turnoff message
in pci controller suspend, and send pme exit message in resume, the
link state will be normal.
When we send pme turnoff message in pci controller suspend, the
links will into l2/l3 ready, then, host cannot communicate with
ep device, but pci-driver will call back EP device to save them
state. So we need to change platform_driver->suspend/resume to
syscore->suspend/resume.
So the new suspend/resume implementation, send pme turnoff message
in suspend, and send pme exit message in resume. And add a PME handler,
to response PME & message interrupt.
Change platform_driver->suspend/resume to syscore->suspend/resume.
pci-driver will call back EP device, to save EP state in
pci_pm_suspend_noirq, so we need to keep the link, until
pci_pm_suspend_noirq finish.
Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
2014-03-20 11:19:37 +08:00
|
|
|
pci = hose->private_data;
|
|
|
|
|
|
|
|
/* Enable PTOD, ENL23D & EXL23D */
|
2014-04-15 15:43:18 +08:00
|
|
|
clrbits32(&pci->pex_pme_mes_disr,
|
fsl/pci: The new pci suspend/resume implementation
If we do nothing in suspend/resume, some platform PCIe ip-block
can't guarantee the link back to L0 state from sleep, then, when
we read the EP device will hang. Only we send pme turnoff message
in pci controller suspend, and send pme exit message in resume, the
link state will be normal.
When we send pme turnoff message in pci controller suspend, the
links will into l2/l3 ready, then, host cannot communicate with
ep device, but pci-driver will call back EP device to save them
state. So we need to change platform_driver->suspend/resume to
syscore->suspend/resume.
So the new suspend/resume implementation, send pme turnoff message
in suspend, and send pme exit message in resume. And add a PME handler,
to response PME & message interrupt.
Change platform_driver->suspend/resume to syscore->suspend/resume.
pci-driver will call back EP device, to save EP state in
pci_pm_suspend_noirq, so we need to keep the link, until
pci_pm_suspend_noirq finish.
Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
2014-03-20 11:19:37 +08:00
|
|
|
PME_DISR_EN_PTOD | PME_DISR_EN_ENL23D | PME_DISR_EN_EXL23D);
|
|
|
|
|
|
|
|
out_be32(&pci->pex_pme_mes_ier, 0);
|
|
|
|
setbits32(&pci->pex_pme_mes_ier,
|
|
|
|
PME_DISR_EN_PTOD | PME_DISR_EN_ENL23D | PME_DISR_EN_EXL23D);
|
|
|
|
|
|
|
|
/* PME Enable */
|
|
|
|
pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pms);
|
|
|
|
pms |= PCI_PM_CTRL_PME_ENABLE;
|
|
|
|
pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pms);
|
2012-11-08 10:11:07 +08:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
fsl/pci: The new pci suspend/resume implementation
If we do nothing in suspend/resume, some platform PCIe ip-block
can't guarantee the link back to L0 state from sleep, then, when
we read the EP device will hang. Only we send pme turnoff message
in pci controller suspend, and send pme exit message in resume, the
link state will be normal.
When we send pme turnoff message in pci controller suspend, the
links will into l2/l3 ready, then, host cannot communicate with
ep device, but pci-driver will call back EP device to save them
state. So we need to change platform_driver->suspend/resume to
syscore->suspend/resume.
So the new suspend/resume implementation, send pme turnoff message
in suspend, and send pme exit message in resume. And add a PME handler,
to response PME & message interrupt.
Change platform_driver->suspend/resume to syscore->suspend/resume.
pci-driver will call back EP device, to save EP state in
pci_pm_suspend_noirq, so we need to keep the link, until
pci_pm_suspend_noirq finish.
Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
2014-03-20 11:19:37 +08:00
|
|
|
static void send_pme_turnoff_message(struct pci_controller *hose)
|
|
|
|
{
|
|
|
|
struct ccsr_pci __iomem *pci = hose->private_data;
|
|
|
|
u32 dr;
|
|
|
|
int i;
|
2012-11-08 10:11:07 +08:00
|
|
|
|
fsl/pci: The new pci suspend/resume implementation
If we do nothing in suspend/resume, some platform PCIe ip-block
can't guarantee the link back to L0 state from sleep, then, when
we read the EP device will hang. Only we send pme turnoff message
in pci controller suspend, and send pme exit message in resume, the
link state will be normal.
When we send pme turnoff message in pci controller suspend, the
links will into l2/l3 ready, then, host cannot communicate with
ep device, but pci-driver will call back EP device to save them
state. So we need to change platform_driver->suspend/resume to
syscore->suspend/resume.
So the new suspend/resume implementation, send pme turnoff message
in suspend, and send pme exit message in resume. And add a PME handler,
to response PME & message interrupt.
Change platform_driver->suspend/resume to syscore->suspend/resume.
pci-driver will call back EP device, to save EP state in
pci_pm_suspend_noirq, so we need to keep the link, until
pci_pm_suspend_noirq finish.
Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
2014-03-20 11:19:37 +08:00
|
|
|
/* Send PME_Turn_Off Message Request */
|
|
|
|
setbits32(&pci->pex_pmcr, PEX_PMCR_PTOMR);
|
2012-11-08 10:11:07 +08:00
|
|
|
|
fsl/pci: The new pci suspend/resume implementation
If we do nothing in suspend/resume, some platform PCIe ip-block
can't guarantee the link back to L0 state from sleep, then, when
we read the EP device will hang. Only we send pme turnoff message
in pci controller suspend, and send pme exit message in resume, the
link state will be normal.
When we send pme turnoff message in pci controller suspend, the
links will into l2/l3 ready, then, host cannot communicate with
ep device, but pci-driver will call back EP device to save them
state. So we need to change platform_driver->suspend/resume to
syscore->suspend/resume.
So the new suspend/resume implementation, send pme turnoff message
in suspend, and send pme exit message in resume. And add a PME handler,
to response PME & message interrupt.
Change platform_driver->suspend/resume to syscore->suspend/resume.
pci-driver will call back EP device, to save EP state in
pci_pm_suspend_noirq, so we need to keep the link, until
pci_pm_suspend_noirq finish.
Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
2014-03-20 11:19:37 +08:00
|
|
|
/* Wait trun off done */
|
|
|
|
for (i = 0; i < 150; i++) {
|
|
|
|
dr = in_be32(&pci->pex_pme_mes_dr);
|
|
|
|
if (dr) {
|
|
|
|
out_be32(&pci->pex_pme_mes_dr, dr);
|
|
|
|
break;
|
|
|
|
}
|
2012-11-08 10:11:07 +08:00
|
|
|
|
fsl/pci: The new pci suspend/resume implementation
If we do nothing in suspend/resume, some platform PCIe ip-block
can't guarantee the link back to L0 state from sleep, then, when
we read the EP device will hang. Only we send pme turnoff message
in pci controller suspend, and send pme exit message in resume, the
link state will be normal.
When we send pme turnoff message in pci controller suspend, the
links will into l2/l3 ready, then, host cannot communicate with
ep device, but pci-driver will call back EP device to save them
state. So we need to change platform_driver->suspend/resume to
syscore->suspend/resume.
So the new suspend/resume implementation, send pme turnoff message
in suspend, and send pme exit message in resume. And add a PME handler,
to response PME & message interrupt.
Change platform_driver->suspend/resume to syscore->suspend/resume.
pci-driver will call back EP device, to save EP state in
pci_pm_suspend_noirq, so we need to keep the link, until
pci_pm_suspend_noirq finish.
Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
2014-03-20 11:19:37 +08:00
|
|
|
udelay(1000);
|
|
|
|
}
|
|
|
|
}
|
2012-11-08 10:11:07 +08:00
|
|
|
|
fsl/pci: The new pci suspend/resume implementation
If we do nothing in suspend/resume, some platform PCIe ip-block
can't guarantee the link back to L0 state from sleep, then, when
we read the EP device will hang. Only we send pme turnoff message
in pci controller suspend, and send pme exit message in resume, the
link state will be normal.
When we send pme turnoff message in pci controller suspend, the
links will into l2/l3 ready, then, host cannot communicate with
ep device, but pci-driver will call back EP device to save them
state. So we need to change platform_driver->suspend/resume to
syscore->suspend/resume.
So the new suspend/resume implementation, send pme turnoff message
in suspend, and send pme exit message in resume. And add a PME handler,
to response PME & message interrupt.
Change platform_driver->suspend/resume to syscore->suspend/resume.
pci-driver will call back EP device, to save EP state in
pci_pm_suspend_noirq, so we need to keep the link, until
pci_pm_suspend_noirq finish.
Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
2014-03-20 11:19:37 +08:00
|
|
|
static void fsl_pci_syscore_do_suspend(struct pci_controller *hose)
|
|
|
|
{
|
|
|
|
send_pme_turnoff_message(hose);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int fsl_pci_syscore_suspend(void)
|
|
|
|
{
|
|
|
|
struct pci_controller *hose, *tmp;
|
|
|
|
|
|
|
|
list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
|
|
|
|
fsl_pci_syscore_do_suspend(hose);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void fsl_pci_syscore_do_resume(struct pci_controller *hose)
|
|
|
|
{
|
|
|
|
struct ccsr_pci __iomem *pci = hose->private_data;
|
|
|
|
u32 dr;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
/* Send Exit L2 State Message */
|
|
|
|
setbits32(&pci->pex_pmcr, PEX_PMCR_EXL2S);
|
|
|
|
|
|
|
|
/* Wait exit done */
|
|
|
|
for (i = 0; i < 150; i++) {
|
|
|
|
dr = in_be32(&pci->pex_pme_mes_dr);
|
|
|
|
if (dr) {
|
|
|
|
out_be32(&pci->pex_pme_mes_dr, dr);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
udelay(1000);
|
|
|
|
}
|
|
|
|
|
|
|
|
setup_pci_atmu(hose);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void fsl_pci_syscore_resume(void)
|
|
|
|
{
|
|
|
|
struct pci_controller *hose, *tmp;
|
|
|
|
|
|
|
|
list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
|
|
|
|
fsl_pci_syscore_do_resume(hose);
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct syscore_ops pci_syscore_pm_ops = {
|
|
|
|
.suspend = fsl_pci_syscore_suspend,
|
|
|
|
.resume = fsl_pci_syscore_resume,
|
|
|
|
};
|
2012-11-08 10:11:07 +08:00
|
|
|
#endif
|
|
|
|
|
fsl/pci: The new pci suspend/resume implementation
If we do nothing in suspend/resume, some platform PCIe ip-block
can't guarantee the link back to L0 state from sleep, then, when
we read the EP device will hang. Only we send pme turnoff message
in pci controller suspend, and send pme exit message in resume, the
link state will be normal.
When we send pme turnoff message in pci controller suspend, the
links will into l2/l3 ready, then, host cannot communicate with
ep device, but pci-driver will call back EP device to save them
state. So we need to change platform_driver->suspend/resume to
syscore->suspend/resume.
So the new suspend/resume implementation, send pme turnoff message
in suspend, and send pme exit message in resume. And add a PME handler,
to response PME & message interrupt.
Change platform_driver->suspend/resume to syscore->suspend/resume.
pci-driver will call back EP device, to save EP state in
pci_pm_suspend_noirq, so we need to keep the link, until
pci_pm_suspend_noirq finish.
Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
2014-03-20 11:19:37 +08:00
|
|
|
void fsl_pcibios_fixup_phb(struct pci_controller *phb)
|
|
|
|
{
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
|
|
fsl_pci_pme_probe(phb);
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
|
|
static int fsl_pci_probe(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct device_node *node;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
node = pdev->dev.of_node;
|
|
|
|
ret = fsl_add_bridge(pdev, fsl_pci_primary == node);
|
|
|
|
|
|
|
|
mpc85xx_pci_err_probe(pdev);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-08-28 15:44:08 +08:00
|
|
|
static struct platform_driver fsl_pci_driver = {
|
|
|
|
.driver = {
|
|
|
|
.name = "fsl-pci",
|
|
|
|
.of_match_table = pci_ids,
|
|
|
|
},
|
|
|
|
.probe = fsl_pci_probe,
|
|
|
|
};
|
|
|
|
|
|
|
|
static int __init fsl_pci_init(void)
|
|
|
|
{
|
fsl/pci: The new pci suspend/resume implementation
If we do nothing in suspend/resume, some platform PCIe ip-block
can't guarantee the link back to L0 state from sleep, then, when
we read the EP device will hang. Only we send pme turnoff message
in pci controller suspend, and send pme exit message in resume, the
link state will be normal.
When we send pme turnoff message in pci controller suspend, the
links will into l2/l3 ready, then, host cannot communicate with
ep device, but pci-driver will call back EP device to save them
state. So we need to change platform_driver->suspend/resume to
syscore->suspend/resume.
So the new suspend/resume implementation, send pme turnoff message
in suspend, and send pme exit message in resume. And add a PME handler,
to response PME & message interrupt.
Change platform_driver->suspend/resume to syscore->suspend/resume.
pci-driver will call back EP device, to save EP state in
pci_pm_suspend_noirq, so we need to keep the link, until
pci_pm_suspend_noirq finish.
Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
2014-03-20 11:19:37 +08:00
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
|
|
register_syscore_ops(&pci_syscore_pm_ops);
|
|
|
|
#endif
|
2012-08-28 15:44:08 +08:00
|
|
|
return platform_driver_register(&fsl_pci_driver);
|
2012-07-11 08:26:47 +08:00
|
|
|
}
|
2012-08-28 15:44:08 +08:00
|
|
|
arch_initcall(fsl_pci_init);
|
2012-07-11 08:26:47 +08:00
|
|
|
#endif
|