2009-08-18 20:23:37 +08:00
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#ifndef BCM63XX_CPU_H_
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#define BCM63XX_CPU_H_
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#include <linux/types.h>
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#include <linux/init.h>
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/*
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* Macro to fetch bcm63xx cpu id and revision, should be optimized at
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* compile time if only one CPU support is enabled (idea stolen from
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* arm mach-types)
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*/
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#define BCM6338_CPU_ID 0x6338
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#define BCM6345_CPU_ID 0x6345
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#define BCM6348_CPU_ID 0x6348
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#define BCM6358_CPU_ID 0x6358
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void __init bcm63xx_cpu_init(void);
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u16 __bcm63xx_get_cpu_id(void);
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u16 bcm63xx_get_cpu_rev(void);
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unsigned int bcm63xx_get_cpu_freq(void);
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#ifdef CONFIG_BCM63XX_CPU_6338
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# ifdef bcm63xx_get_cpu_id
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# undef bcm63xx_get_cpu_id
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# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
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# define BCMCPU_RUNTIME_DETECT
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# else
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# define bcm63xx_get_cpu_id() BCM6338_CPU_ID
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# endif
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# define BCMCPU_IS_6338() (bcm63xx_get_cpu_id() == BCM6338_CPU_ID)
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#else
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# define BCMCPU_IS_6338() (0)
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#endif
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#ifdef CONFIG_BCM63XX_CPU_6345
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# ifdef bcm63xx_get_cpu_id
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# undef bcm63xx_get_cpu_id
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# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
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# define BCMCPU_RUNTIME_DETECT
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# else
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# define bcm63xx_get_cpu_id() BCM6345_CPU_ID
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# endif
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# define BCMCPU_IS_6345() (bcm63xx_get_cpu_id() == BCM6345_CPU_ID)
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#else
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# define BCMCPU_IS_6345() (0)
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#endif
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#ifdef CONFIG_BCM63XX_CPU_6348
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# ifdef bcm63xx_get_cpu_id
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# undef bcm63xx_get_cpu_id
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# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
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# define BCMCPU_RUNTIME_DETECT
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# else
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# define bcm63xx_get_cpu_id() BCM6348_CPU_ID
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# endif
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# define BCMCPU_IS_6348() (bcm63xx_get_cpu_id() == BCM6348_CPU_ID)
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#else
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# define BCMCPU_IS_6348() (0)
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#endif
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#ifdef CONFIG_BCM63XX_CPU_6358
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# ifdef bcm63xx_get_cpu_id
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# undef bcm63xx_get_cpu_id
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# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
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# define BCMCPU_RUNTIME_DETECT
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# else
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# define bcm63xx_get_cpu_id() BCM6358_CPU_ID
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# endif
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# define BCMCPU_IS_6358() (bcm63xx_get_cpu_id() == BCM6358_CPU_ID)
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#else
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# define BCMCPU_IS_6358() (0)
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#endif
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#ifndef bcm63xx_get_cpu_id
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#error "No CPU support configured"
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#endif
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/*
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* While registers sets are (mostly) the same across 63xx CPU, base
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* address of these sets do change.
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*/
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enum bcm63xx_regs_set {
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RSET_DSL_LMEM = 0,
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RSET_PERF,
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RSET_TIMER,
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RSET_WDT,
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RSET_UART0,
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2010-01-31 01:34:55 +08:00
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RSET_UART1,
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2009-08-18 20:23:37 +08:00
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RSET_GPIO,
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RSET_SPI,
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RSET_UDC0,
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RSET_OHCI0,
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RSET_OHCI_PRIV,
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RSET_USBH_PRIV,
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RSET_MPI,
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RSET_PCMCIA,
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RSET_DSL,
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RSET_ENET0,
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RSET_ENET1,
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RSET_ENETDMA,
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RSET_EHCI0,
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RSET_SDRAM,
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RSET_MEMC,
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RSET_DDR,
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};
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#define RSET_DSL_LMEM_SIZE (64 * 1024 * 4)
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#define RSET_DSL_SIZE 4096
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#define RSET_WDT_SIZE 12
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#define RSET_ENET_SIZE 2048
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#define RSET_ENETDMA_SIZE 2048
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#define RSET_UART_SIZE 24
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#define RSET_UDC_SIZE 256
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#define RSET_OHCI_SIZE 256
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#define RSET_EHCI_SIZE 256
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#define RSET_PCMCIA_SIZE 12
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/*
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* 6338 register sets base address
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*/
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#define BCM_6338_DSL_LMEM_BASE (0xfff00000)
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#define BCM_6338_PERF_BASE (0xfffe0000)
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#define BCM_6338_BB_BASE (0xfffe0100)
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#define BCM_6338_TIMER_BASE (0xfffe0200)
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#define BCM_6338_WDT_BASE (0xfffe021c)
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#define BCM_6338_UART0_BASE (0xfffe0300)
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2010-01-31 01:34:55 +08:00
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#define BCM_6338_UART1_BASE (0xdeadbeef)
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2009-08-18 20:23:37 +08:00
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#define BCM_6338_GPIO_BASE (0xfffe0400)
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#define BCM_6338_SPI_BASE (0xfffe0c00)
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#define BCM_6338_UDC0_BASE (0xdeadbeef)
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#define BCM_6338_USBDMA_BASE (0xfffe2400)
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#define BCM_6338_OHCI0_BASE (0xdeadbeef)
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#define BCM_6338_OHCI_PRIV_BASE (0xfffe3000)
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#define BCM_6338_USBH_PRIV_BASE (0xdeadbeef)
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#define BCM_6338_MPI_BASE (0xfffe3160)
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#define BCM_6338_PCMCIA_BASE (0xdeadbeef)
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#define BCM_6338_SDRAM_REGS_BASE (0xfffe3100)
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#define BCM_6338_DSL_BASE (0xfffe1000)
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#define BCM_6338_SAR_BASE (0xfffe2000)
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#define BCM_6338_UBUS_BASE (0xdeadbeef)
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#define BCM_6338_ENET0_BASE (0xfffe2800)
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#define BCM_6338_ENET1_BASE (0xdeadbeef)
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#define BCM_6338_ENETDMA_BASE (0xfffe2400)
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#define BCM_6338_EHCI0_BASE (0xdeadbeef)
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#define BCM_6338_SDRAM_BASE (0xfffe3100)
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#define BCM_6338_MEMC_BASE (0xdeadbeef)
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#define BCM_6338_DDR_BASE (0xdeadbeef)
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/*
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* 6345 register sets base address
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*/
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#define BCM_6345_DSL_LMEM_BASE (0xfff00000)
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#define BCM_6345_PERF_BASE (0xfffe0000)
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#define BCM_6345_BB_BASE (0xfffe0100)
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#define BCM_6345_TIMER_BASE (0xfffe0200)
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#define BCM_6345_WDT_BASE (0xfffe021c)
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#define BCM_6345_UART0_BASE (0xfffe0300)
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2010-01-31 01:34:55 +08:00
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#define BCM_6345_UART1_BASE (0xdeadbeef)
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2009-08-18 20:23:37 +08:00
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#define BCM_6345_GPIO_BASE (0xfffe0400)
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#define BCM_6345_SPI_BASE (0xdeadbeef)
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#define BCM_6345_UDC0_BASE (0xdeadbeef)
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#define BCM_6345_USBDMA_BASE (0xfffe2800)
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#define BCM_6345_ENET0_BASE (0xfffe1800)
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#define BCM_6345_ENETDMA_BASE (0xfffe2800)
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#define BCM_6345_PCMCIA_BASE (0xfffe2028)
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#define BCM_6345_MPI_BASE (0xdeadbeef)
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#define BCM_6345_OHCI0_BASE (0xfffe2100)
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#define BCM_6345_OHCI_PRIV_BASE (0xfffe2200)
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#define BCM_6345_USBH_PRIV_BASE (0xdeadbeef)
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#define BCM_6345_SDRAM_REGS_BASE (0xfffe2300)
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#define BCM_6345_DSL_BASE (0xdeadbeef)
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#define BCM_6345_SAR_BASE (0xdeadbeef)
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#define BCM_6345_UBUS_BASE (0xdeadbeef)
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#define BCM_6345_ENET1_BASE (0xdeadbeef)
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#define BCM_6345_EHCI0_BASE (0xdeadbeef)
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#define BCM_6345_SDRAM_BASE (0xfffe2300)
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#define BCM_6345_MEMC_BASE (0xdeadbeef)
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#define BCM_6345_DDR_BASE (0xdeadbeef)
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/*
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* 6348 register sets base address
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*/
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#define BCM_6348_DSL_LMEM_BASE (0xfff00000)
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#define BCM_6348_PERF_BASE (0xfffe0000)
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#define BCM_6348_TIMER_BASE (0xfffe0200)
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#define BCM_6348_WDT_BASE (0xfffe021c)
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#define BCM_6348_UART0_BASE (0xfffe0300)
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2010-01-31 01:34:55 +08:00
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#define BCM_6348_UART1_BASE (0xdeadbeef)
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2009-08-18 20:23:37 +08:00
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#define BCM_6348_GPIO_BASE (0xfffe0400)
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#define BCM_6348_SPI_BASE (0xfffe0c00)
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#define BCM_6348_UDC0_BASE (0xfffe1000)
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#define BCM_6348_OHCI0_BASE (0xfffe1b00)
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#define BCM_6348_OHCI_PRIV_BASE (0xfffe1c00)
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#define BCM_6348_USBH_PRIV_BASE (0xdeadbeef)
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#define BCM_6348_MPI_BASE (0xfffe2000)
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#define BCM_6348_PCMCIA_BASE (0xfffe2054)
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#define BCM_6348_SDRAM_REGS_BASE (0xfffe2300)
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#define BCM_6348_DSL_BASE (0xfffe3000)
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#define BCM_6348_ENET0_BASE (0xfffe6000)
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#define BCM_6348_ENET1_BASE (0xfffe6800)
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#define BCM_6348_ENETDMA_BASE (0xfffe7000)
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#define BCM_6348_EHCI0_BASE (0xdeadbeef)
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#define BCM_6348_SDRAM_BASE (0xfffe2300)
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#define BCM_6348_MEMC_BASE (0xdeadbeef)
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#define BCM_6348_DDR_BASE (0xdeadbeef)
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/*
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* 6358 register sets base address
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*/
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#define BCM_6358_DSL_LMEM_BASE (0xfff00000)
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#define BCM_6358_PERF_BASE (0xfffe0000)
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#define BCM_6358_TIMER_BASE (0xfffe0040)
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#define BCM_6358_WDT_BASE (0xfffe005c)
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#define BCM_6358_UART0_BASE (0xfffe0100)
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#define BCM_6358_UART1_BASE (0xfffe0120)
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2009-08-18 20:23:37 +08:00
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#define BCM_6358_GPIO_BASE (0xfffe0080)
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#define BCM_6358_SPI_BASE (0xdeadbeef)
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#define BCM_6358_UDC0_BASE (0xfffe0800)
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#define BCM_6358_OHCI0_BASE (0xfffe1400)
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#define BCM_6358_OHCI_PRIV_BASE (0xdeadbeef)
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#define BCM_6358_USBH_PRIV_BASE (0xfffe1500)
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#define BCM_6358_MPI_BASE (0xfffe1000)
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#define BCM_6358_PCMCIA_BASE (0xfffe1054)
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#define BCM_6358_SDRAM_REGS_BASE (0xfffe2300)
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#define BCM_6358_DSL_BASE (0xfffe3000)
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#define BCM_6358_ENET0_BASE (0xfffe4000)
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#define BCM_6358_ENET1_BASE (0xfffe4800)
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#define BCM_6358_ENETDMA_BASE (0xfffe5000)
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#define BCM_6358_EHCI0_BASE (0xfffe1300)
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#define BCM_6358_SDRAM_BASE (0xdeadbeef)
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#define BCM_6358_MEMC_BASE (0xfffe1200)
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#define BCM_6358_DDR_BASE (0xfffe12a0)
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extern const unsigned long *bcm63xx_regs_base;
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2011-11-05 02:09:29 +08:00
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#define __GEN_RSET_BASE(__cpu, __rset) \
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case RSET_## __rset : \
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return BCM_## __cpu ##_## __rset ##_BASE;
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#define __GEN_RSET(__cpu) \
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switch (set) { \
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__GEN_RSET_BASE(__cpu, DSL_LMEM) \
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__GEN_RSET_BASE(__cpu, PERF) \
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__GEN_RSET_BASE(__cpu, TIMER) \
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__GEN_RSET_BASE(__cpu, WDT) \
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__GEN_RSET_BASE(__cpu, UART0) \
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__GEN_RSET_BASE(__cpu, UART1) \
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__GEN_RSET_BASE(__cpu, GPIO) \
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__GEN_RSET_BASE(__cpu, SPI) \
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__GEN_RSET_BASE(__cpu, UDC0) \
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__GEN_RSET_BASE(__cpu, OHCI0) \
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__GEN_RSET_BASE(__cpu, OHCI_PRIV) \
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__GEN_RSET_BASE(__cpu, USBH_PRIV) \
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__GEN_RSET_BASE(__cpu, MPI) \
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__GEN_RSET_BASE(__cpu, PCMCIA) \
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__GEN_RSET_BASE(__cpu, DSL) \
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__GEN_RSET_BASE(__cpu, ENET0) \
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__GEN_RSET_BASE(__cpu, ENET1) \
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__GEN_RSET_BASE(__cpu, ENETDMA) \
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__GEN_RSET_BASE(__cpu, EHCI0) \
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__GEN_RSET_BASE(__cpu, SDRAM) \
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__GEN_RSET_BASE(__cpu, MEMC) \
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__GEN_RSET_BASE(__cpu, DDR) \
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}
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#define __GEN_CPU_REGS_TABLE(__cpu) \
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[RSET_DSL_LMEM] = BCM_## __cpu ##_DSL_LMEM_BASE, \
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[RSET_PERF] = BCM_## __cpu ##_PERF_BASE, \
|
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[RSET_TIMER] = BCM_## __cpu ##_TIMER_BASE, \
|
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[RSET_WDT] = BCM_## __cpu ##_WDT_BASE, \
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[RSET_UART0] = BCM_## __cpu ##_UART0_BASE, \
|
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[RSET_UART1] = BCM_## __cpu ##_UART1_BASE, \
|
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[RSET_GPIO] = BCM_## __cpu ##_GPIO_BASE, \
|
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[RSET_SPI] = BCM_## __cpu ##_SPI_BASE, \
|
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[RSET_UDC0] = BCM_## __cpu ##_UDC0_BASE, \
|
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|
[RSET_OHCI0] = BCM_## __cpu ##_OHCI0_BASE, \
|
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|
|
|
[RSET_OHCI_PRIV] = BCM_## __cpu ##_OHCI_PRIV_BASE, \
|
|
|
|
|
[RSET_USBH_PRIV] = BCM_## __cpu ##_USBH_PRIV_BASE, \
|
|
|
|
|
[RSET_MPI] = BCM_## __cpu ##_MPI_BASE, \
|
|
|
|
|
[RSET_PCMCIA] = BCM_## __cpu ##_PCMCIA_BASE, \
|
|
|
|
|
[RSET_DSL] = BCM_## __cpu ##_DSL_BASE, \
|
|
|
|
|
[RSET_ENET0] = BCM_## __cpu ##_ENET0_BASE, \
|
|
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|
|
[RSET_ENET1] = BCM_## __cpu ##_ENET1_BASE, \
|
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|
|
[RSET_ENETDMA] = BCM_## __cpu ##_ENETDMA_BASE, \
|
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|
|
|
[RSET_EHCI0] = BCM_## __cpu ##_EHCI0_BASE, \
|
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|
[RSET_SDRAM] = BCM_## __cpu ##_SDRAM_BASE, \
|
|
|
|
|
[RSET_MEMC] = BCM_## __cpu ##_MEMC_BASE, \
|
|
|
|
|
[RSET_DDR] = BCM_## __cpu ##_DDR_BASE, \
|
|
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|
|
|
|
|
|
|
2009-08-18 20:23:37 +08:00
|
|
|
static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
|
|
|
|
|
{
|
|
|
|
|
#ifdef BCMCPU_RUNTIME_DETECT
|
|
|
|
|
return bcm63xx_regs_base[set];
|
|
|
|
|
#else
|
|
|
|
|
#ifdef CONFIG_BCM63XX_CPU_6338
|
2011-11-05 02:09:29 +08:00
|
|
|
__GEN_RSET(6338)
|
2009-08-18 20:23:37 +08:00
|
|
|
#endif
|
|
|
|
|
#ifdef CONFIG_BCM63XX_CPU_6345
|
2011-11-05 02:09:29 +08:00
|
|
|
__GEN_RSET(6345)
|
2009-08-18 20:23:37 +08:00
|
|
|
#endif
|
|
|
|
|
#ifdef CONFIG_BCM63XX_CPU_6348
|
2011-11-05 02:09:29 +08:00
|
|
|
__GEN_RSET(6348)
|
2009-08-18 20:23:37 +08:00
|
|
|
#endif
|
|
|
|
|
#ifdef CONFIG_BCM63XX_CPU_6358
|
2011-11-05 02:09:29 +08:00
|
|
|
__GEN_RSET(6358)
|
2009-08-18 20:23:37 +08:00
|
|
|
#endif
|
|
|
|
|
#endif
|
|
|
|
|
/* unreached */
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* IRQ number changes across CPU too
|
|
|
|
|
*/
|
|
|
|
|
enum bcm63xx_irq {
|
|
|
|
|
IRQ_TIMER = 0,
|
|
|
|
|
IRQ_UART0,
|
2010-01-31 01:34:55 +08:00
|
|
|
IRQ_UART1,
|
2009-08-18 20:23:37 +08:00
|
|
|
IRQ_DSL,
|
|
|
|
|
IRQ_ENET0,
|
|
|
|
|
IRQ_ENET1,
|
|
|
|
|
IRQ_ENET_PHY,
|
|
|
|
|
IRQ_OHCI0,
|
|
|
|
|
IRQ_EHCI0,
|
|
|
|
|
IRQ_ENET0_RXDMA,
|
|
|
|
|
IRQ_ENET0_TXDMA,
|
|
|
|
|
IRQ_ENET1_RXDMA,
|
|
|
|
|
IRQ_ENET1_TXDMA,
|
|
|
|
|
IRQ_PCI,
|
|
|
|
|
IRQ_PCMCIA,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* 6338 irqs
|
|
|
|
|
*/
|
|
|
|
|
#define BCM_6338_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
|
|
|
|
|
#define BCM_6338_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
|
2011-11-05 02:09:29 +08:00
|
|
|
#define BCM_6338_UART1_IRQ 0
|
2009-08-18 20:23:37 +08:00
|
|
|
#define BCM_6338_DSL_IRQ (IRQ_INTERNAL_BASE + 5)
|
|
|
|
|
#define BCM_6338_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
|
2011-11-05 02:09:29 +08:00
|
|
|
#define BCM_6338_ENET1_IRQ 0
|
2009-08-18 20:23:37 +08:00
|
|
|
#define BCM_6338_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
|
2011-11-05 02:09:29 +08:00
|
|
|
#define BCM_6338_OHCI0_IRQ 0
|
|
|
|
|
#define BCM_6338_EHCI0_IRQ 0
|
2009-08-18 20:23:37 +08:00
|
|
|
#define BCM_6338_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15)
|
|
|
|
|
#define BCM_6338_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16)
|
2011-11-05 02:09:29 +08:00
|
|
|
#define BCM_6338_ENET1_RXDMA_IRQ 0
|
|
|
|
|
#define BCM_6338_ENET1_TXDMA_IRQ 0
|
|
|
|
|
#define BCM_6338_PCI_IRQ 0
|
|
|
|
|
#define BCM_6338_PCMCIA_IRQ 0
|
2009-08-18 20:23:37 +08:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* 6345 irqs
|
|
|
|
|
*/
|
|
|
|
|
#define BCM_6345_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
|
|
|
|
|
#define BCM_6345_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
|
2011-11-05 02:09:29 +08:00
|
|
|
#define BCM_6345_UART1_IRQ 0
|
2009-08-18 20:23:37 +08:00
|
|
|
#define BCM_6345_DSL_IRQ (IRQ_INTERNAL_BASE + 3)
|
|
|
|
|
#define BCM_6345_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
|
2011-11-05 02:09:29 +08:00
|
|
|
#define BCM_6345_ENET1_IRQ 0
|
2009-08-18 20:23:37 +08:00
|
|
|
#define BCM_6345_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12)
|
2011-11-05 02:09:29 +08:00
|
|
|
#define BCM_6345_OHCI0_IRQ 0
|
|
|
|
|
#define BCM_6345_EHCI0_IRQ 0
|
2009-08-18 20:23:37 +08:00
|
|
|
#define BCM_6345_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 1)
|
|
|
|
|
#define BCM_6345_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 2)
|
2011-11-05 02:09:29 +08:00
|
|
|
#define BCM_6345_ENET1_RXDMA_IRQ 0
|
|
|
|
|
#define BCM_6345_ENET1_TXDMA_IRQ 0
|
|
|
|
|
#define BCM_6345_PCI_IRQ 0
|
|
|
|
|
#define BCM_6345_PCMCIA_IRQ 0
|
2009-08-18 20:23:37 +08:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* 6348 irqs
|
|
|
|
|
*/
|
|
|
|
|
#define BCM_6348_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
|
|
|
|
|
#define BCM_6348_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
|
2011-11-05 02:09:29 +08:00
|
|
|
#define BCM_6348_UART1_IRQ 0
|
2009-08-18 20:23:37 +08:00
|
|
|
#define BCM_6348_DSL_IRQ (IRQ_INTERNAL_BASE + 4)
|
|
|
|
|
#define BCM_6348_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
|
2011-11-05 02:09:29 +08:00
|
|
|
#define BCM_6348_ENET1_IRQ (IRQ_INTERNAL_BASE + 7)
|
2009-08-18 20:23:37 +08:00
|
|
|
#define BCM_6348_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
|
|
|
|
|
#define BCM_6348_OHCI0_IRQ (IRQ_INTERNAL_BASE + 12)
|
2011-11-05 02:09:29 +08:00
|
|
|
#define BCM_6348_EHCI0_IRQ 0
|
2009-08-18 20:23:37 +08:00
|
|
|
#define BCM_6348_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 20)
|
|
|
|
|
#define BCM_6348_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 21)
|
|
|
|
|
#define BCM_6348_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 22)
|
|
|
|
|
#define BCM_6348_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 23)
|
|
|
|
|
#define BCM_6348_PCI_IRQ (IRQ_INTERNAL_BASE + 24)
|
2011-11-05 02:09:29 +08:00
|
|
|
#define BCM_6348_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24)
|
2009-08-18 20:23:37 +08:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* 6358 irqs
|
|
|
|
|
*/
|
|
|
|
|
#define BCM_6358_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
|
|
|
|
|
#define BCM_6358_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
|
2010-01-31 01:34:55 +08:00
|
|
|
#define BCM_6358_UART1_IRQ (IRQ_INTERNAL_BASE + 3)
|
2011-11-05 02:09:29 +08:00
|
|
|
#define BCM_6358_DSL_IRQ (IRQ_INTERNAL_BASE + 29)
|
2009-08-18 20:23:37 +08:00
|
|
|
#define BCM_6358_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
|
2011-11-05 02:09:29 +08:00
|
|
|
#define BCM_6358_ENET1_IRQ (IRQ_INTERNAL_BASE + 6)
|
2009-08-18 20:23:37 +08:00
|
|
|
#define BCM_6358_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
|
2011-11-05 02:09:29 +08:00
|
|
|
#define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5)
|
2009-08-18 20:23:37 +08:00
|
|
|
#define BCM_6358_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10)
|
|
|
|
|
#define BCM_6358_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15)
|
|
|
|
|
#define BCM_6358_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16)
|
|
|
|
|
#define BCM_6358_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 17)
|
|
|
|
|
#define BCM_6358_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 18)
|
|
|
|
|
#define BCM_6358_PCI_IRQ (IRQ_INTERNAL_BASE + 31)
|
|
|
|
|
#define BCM_6358_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24)
|
|
|
|
|
|
|
|
|
|
extern const int *bcm63xx_irqs;
|
|
|
|
|
|
2011-11-05 02:09:29 +08:00
|
|
|
#define __GEN_CPU_IRQ_TABLE(__cpu) \
|
|
|
|
|
[IRQ_TIMER] = BCM_## __cpu ##_TIMER_IRQ, \
|
|
|
|
|
[IRQ_UART0] = BCM_## __cpu ##_UART0_IRQ, \
|
|
|
|
|
[IRQ_UART1] = BCM_## __cpu ##_UART1_IRQ, \
|
|
|
|
|
[IRQ_DSL] = BCM_## __cpu ##_DSL_IRQ, \
|
|
|
|
|
[IRQ_ENET0] = BCM_## __cpu ##_ENET0_IRQ, \
|
|
|
|
|
[IRQ_ENET1] = BCM_## __cpu ##_ENET1_IRQ, \
|
|
|
|
|
[IRQ_ENET_PHY] = BCM_## __cpu ##_ENET_PHY_IRQ, \
|
|
|
|
|
[IRQ_OHCI0] = BCM_## __cpu ##_OHCI0_IRQ, \
|
|
|
|
|
[IRQ_EHCI0] = BCM_## __cpu ##_EHCI0_IRQ, \
|
|
|
|
|
[IRQ_ENET0_RXDMA] = BCM_## __cpu ##_ENET0_RXDMA_IRQ, \
|
|
|
|
|
[IRQ_ENET0_TXDMA] = BCM_## __cpu ##_ENET0_TXDMA_IRQ, \
|
|
|
|
|
[IRQ_ENET1_RXDMA] = BCM_## __cpu ##_ENET1_RXDMA_IRQ, \
|
|
|
|
|
[IRQ_ENET1_TXDMA] = BCM_## __cpu ##_ENET1_TXDMA_IRQ, \
|
|
|
|
|
[IRQ_PCI] = BCM_## __cpu ##_PCI_IRQ, \
|
|
|
|
|
[IRQ_PCMCIA] = BCM_## __cpu ##_PCMCIA_IRQ, \
|
|
|
|
|
|
2009-08-18 20:23:37 +08:00
|
|
|
static inline int bcm63xx_get_irq_number(enum bcm63xx_irq irq)
|
|
|
|
|
{
|
|
|
|
|
return bcm63xx_irqs[irq];
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* return installed memory size
|
|
|
|
|
*/
|
|
|
|
|
unsigned int bcm63xx_get_memory_size(void);
|
|
|
|
|
|
|
|
|
|
#endif /* !BCM63XX_CPU_H_ */
|
