331 lines
9.3 KiB
C
331 lines
9.3 KiB
C
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/*
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* include/asm-xtensa/mmu_context.h
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*
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* Switch an MMU context.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2001 - 2005 Tensilica Inc.
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*/
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#ifndef _XTENSA_MMU_CONTEXT_H
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#define _XTENSA_MMU_CONTEXT_H
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#include <linux/config.h>
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#include <linux/stringify.h>
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#include <asm/pgtable.h>
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#include <asm/mmu_context.h>
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#include <asm/cacheflush.h>
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#include <asm/tlbflush.h>
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/*
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* Linux was ported to Xtensa assuming all auto-refill ways in set 0
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* had the same properties (a very likely assumption). Multiple sets
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* of auto-refill ways will still work properly, but not as optimally
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* as the Xtensa designer may have assumed.
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*
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* We make this case a hard #error, killing the kernel build, to alert
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* the developer to this condition (which is more likely an error).
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* You super-duper clever developers can change it to a warning or
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* remove it altogether if you think you know what you're doing. :)
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*/
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#if (XCHAL_HAVE_TLBS != 1)
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# error "Linux must have an MMU!"
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#endif
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#if ((XCHAL_ITLB_ARF_WAYS == 0) || (XCHAL_DTLB_ARF_WAYS == 0))
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# error "MMU must have auto-refill ways"
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#endif
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#if ((XCHAL_ITLB_ARF_SETS != 1) || (XCHAL_DTLB_ARF_SETS != 1))
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# error Linux may not use all auto-refill ways as efficiently as you think
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#endif
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#if (XCHAL_MMU_MAX_PTE_PAGE_SIZE != XCHAL_MMU_MIN_PTE_PAGE_SIZE)
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# error Only one page size allowed!
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#endif
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extern unsigned long asid_cache;
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extern pgd_t *current_pgd;
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/*
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* Define the number of entries per auto-refill way in set 0 of both I and D
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* TLBs. We deal only with set 0 here (an assumption further explained in
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* assertions.h). Also, define the total number of ARF entries in both TLBs.
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*/
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#define ITLB_ENTRIES_PER_ARF_WAY (XCHAL_ITLB_SET(XCHAL_ITLB_ARF_SET0,ENTRIES))
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#define DTLB_ENTRIES_PER_ARF_WAY (XCHAL_DTLB_SET(XCHAL_DTLB_ARF_SET0,ENTRIES))
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#define ITLB_ENTRIES \
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(ITLB_ENTRIES_PER_ARF_WAY * (XCHAL_ITLB_SET(XCHAL_ITLB_ARF_SET0,WAYS)))
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#define DTLB_ENTRIES \
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(DTLB_ENTRIES_PER_ARF_WAY * (XCHAL_DTLB_SET(XCHAL_DTLB_ARF_SET0,WAYS)))
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/*
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* SMALLEST_NTLB_ENTRIES is the smaller of ITLB_ENTRIES and DTLB_ENTRIES.
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* In practice, they are probably equal. This macro simplifies function
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* flush_tlb_range().
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*/
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#if (DTLB_ENTRIES < ITLB_ENTRIES)
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# define SMALLEST_NTLB_ENTRIES DTLB_ENTRIES
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#else
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# define SMALLEST_NTLB_ENTRIES ITLB_ENTRIES
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#endif
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/*
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* asid_cache tracks only the ASID[USER_RING] field of the RASID special
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* register, which is the current user-task asid allocation value.
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* mm->context has the same meaning. When it comes time to write the
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* asid_cache or mm->context values to the RASID special register, we first
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* shift the value left by 8, then insert the value.
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* ASID[0] always contains the kernel's asid value, and we reserve three
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* other asid values that we never assign to user tasks.
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*/
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#define ASID_INC 0x1
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#define ASID_MASK ((1 << XCHAL_MMU_ASID_BITS) - 1)
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/*
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* XCHAL_MMU_ASID_INVALID is a configurable Xtensa processor constant
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* indicating invalid address space. XCHAL_MMU_ASID_KERNEL is a configurable
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* Xtensa processor constant indicating the kernel address space. They can
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* be arbitrary values.
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*
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* We identify three more unique, reserved ASID values to use in the unused
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* ring positions. No other user process will be assigned these reserved
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* ASID values.
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*
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* For example, given that
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*
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* XCHAL_MMU_ASID_INVALID == 0
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* XCHAL_MMU_ASID_KERNEL == 1
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*
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* the following maze of #if statements would generate
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*
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* ASID_RESERVED_1 == 2
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* ASID_RESERVED_2 == 3
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* ASID_RESERVED_3 == 4
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* ASID_FIRST_NONRESERVED == 5
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*/
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#if (XCHAL_MMU_ASID_INVALID != XCHAL_MMU_ASID_KERNEL + 1)
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# define ASID_RESERVED_1 ((XCHAL_MMU_ASID_KERNEL + 1) & ASID_MASK)
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#else
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# define ASID_RESERVED_1 ((XCHAL_MMU_ASID_KERNEL + 2) & ASID_MASK)
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#endif
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#if (XCHAL_MMU_ASID_INVALID != ASID_RESERVED_1 + 1)
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# define ASID_RESERVED_2 ((ASID_RESERVED_1 + 1) & ASID_MASK)
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#else
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# define ASID_RESERVED_2 ((ASID_RESERVED_1 + 2) & ASID_MASK)
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#endif
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#if (XCHAL_MMU_ASID_INVALID != ASID_RESERVED_2 + 1)
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# define ASID_RESERVED_3 ((ASID_RESERVED_2 + 1) & ASID_MASK)
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#else
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# define ASID_RESERVED_3 ((ASID_RESERVED_2 + 2) & ASID_MASK)
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#endif
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#if (XCHAL_MMU_ASID_INVALID != ASID_RESERVED_3 + 1)
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# define ASID_FIRST_NONRESERVED ((ASID_RESERVED_3 + 1) & ASID_MASK)
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#else
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# define ASID_FIRST_NONRESERVED ((ASID_RESERVED_3 + 2) & ASID_MASK)
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#endif
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#define ASID_ALL_RESERVED ( ((ASID_RESERVED_1) << 24) + \
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((ASID_RESERVED_2) << 16) + \
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((ASID_RESERVED_3) << 8) + \
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((XCHAL_MMU_ASID_KERNEL)) )
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/*
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* NO_CONTEXT is the invalid ASID value that we don't ever assign to
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* any user or kernel context. NO_CONTEXT is a better mnemonic than
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* XCHAL_MMU_ASID_INVALID, so we use it in code instead.
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*/
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#define NO_CONTEXT XCHAL_MMU_ASID_INVALID
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#if (KERNEL_RING != 0)
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# error The KERNEL_RING really should be zero.
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#endif
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#if (USER_RING >= XCHAL_MMU_RINGS)
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# error USER_RING cannot be greater than the highest numbered ring.
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#endif
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#if (USER_RING == KERNEL_RING)
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# error The user and kernel rings really should not be equal.
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#endif
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#if (USER_RING == 1)
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#define ASID_INSERT(x) ( ((ASID_RESERVED_1) << 24) + \
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((ASID_RESERVED_2) << 16) + \
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(((x) & (ASID_MASK)) << 8) + \
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((XCHAL_MMU_ASID_KERNEL)) )
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#elif (USER_RING == 2)
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#define ASID_INSERT(x) ( ((ASID_RESERVED_1) << 24) + \
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(((x) & (ASID_MASK)) << 16) + \
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((ASID_RESERVED_2) << 8) + \
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((XCHAL_MMU_ASID_KERNEL)) )
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#elif (USER_RING == 3)
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#define ASID_INSERT(x) ( (((x) & (ASID_MASK)) << 24) + \
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((ASID_RESERVED_1) << 16) + \
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((ASID_RESERVED_2) << 8) + \
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((XCHAL_MMU_ASID_KERNEL)) )
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#else
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#error Goofy value for USER_RING
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#endif /* USER_RING == 1 */
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/*
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* All unused by hardware upper bits will be considered
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* as a software asid extension.
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*/
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#define ASID_VERSION_MASK ((unsigned long)~(ASID_MASK|(ASID_MASK-1)))
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#define ASID_FIRST_VERSION \
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((unsigned long)(~ASID_VERSION_MASK) + 1 + ASID_FIRST_NONRESERVED)
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extern inline void set_rasid_register (unsigned long val)
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{
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__asm__ __volatile__ (" wsr %0, "__stringify(RASID)"\n\t"
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" isync\n" : : "a" (val));
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}
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extern inline unsigned long get_rasid_register (void)
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{
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unsigned long tmp;
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__asm__ __volatile__ (" rsr %0, "__stringify(RASID)"\n\t" : "=a" (tmp));
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return tmp;
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}
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#if ((XCHAL_MMU_ASID_INVALID == 0) && (XCHAL_MMU_ASID_KERNEL == 1))
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extern inline void
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get_new_mmu_context(struct mm_struct *mm, unsigned long asid)
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{
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extern void flush_tlb_all(void);
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if (! ((asid += ASID_INC) & ASID_MASK) ) {
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flush_tlb_all(); /* start new asid cycle */
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if (!asid) /* fix version if needed */
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asid = ASID_FIRST_VERSION - ASID_FIRST_NONRESERVED;
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asid += ASID_FIRST_NONRESERVED;
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}
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mm->context = asid_cache = asid;
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}
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#else
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#warning ASID_{INVALID,KERNEL} values impose non-optimal get_new_mmu_context implementation
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/* XCHAL_MMU_ASID_INVALID == 0 and XCHAL_MMU_ASID_KERNEL ==1 are
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really the best, but if you insist... */
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extern inline int validate_asid (unsigned long asid)
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{
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switch (asid) {
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case XCHAL_MMU_ASID_INVALID:
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case XCHAL_MMU_ASID_KERNEL:
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case ASID_RESERVED_1:
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case ASID_RESERVED_2:
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case ASID_RESERVED_3:
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return 0; /* can't use these values as ASIDs */
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}
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return 1; /* valid */
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}
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extern inline void
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get_new_mmu_context(struct mm_struct *mm, unsigned long asid)
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{
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extern void flush_tlb_all(void);
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while (1) {
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asid += ASID_INC;
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if ( ! (asid & ASID_MASK) ) {
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flush_tlb_all(); /* start new asid cycle */
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if (!asid) /* fix version if needed */
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asid = ASID_FIRST_VERSION - ASID_FIRST_NONRESERVED;
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asid += ASID_FIRST_NONRESERVED;
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break; /* no need to validate here */
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}
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if (validate_asid (asid & ASID_MASK))
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break;
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}
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mm->context = asid_cache = asid;
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}
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#endif
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/*
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* Initialize the context related info for a new mm_struct
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* instance.
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*/
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extern inline int
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init_new_context(struct task_struct *tsk, struct mm_struct *mm)
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{
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mm->context = NO_CONTEXT;
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return 0;
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}
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extern inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
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struct task_struct *tsk)
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{
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unsigned long asid = asid_cache;
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/* Check if our ASID is of an older version and thus invalid */
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if ((next->context ^ asid) & ASID_VERSION_MASK)
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get_new_mmu_context(next, asid);
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set_rasid_register (ASID_INSERT(next->context));
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invalidate_page_directory();
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}
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#define deactivate_mm(tsk, mm) do { } while(0)
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/*
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* Destroy context related info for an mm_struct that is about
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* to be put to rest.
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*/
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extern inline void destroy_context(struct mm_struct *mm)
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{
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/* Nothing to do. */
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}
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/*
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* After we have set current->mm to a new value, this activates
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* the context for the new mm so we see the new mappings.
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*/
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extern inline void
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activate_mm(struct mm_struct *prev, struct mm_struct *next)
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{
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/* Unconditionally get a new ASID. */
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get_new_mmu_context(next, asid_cache);
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set_rasid_register (ASID_INSERT(next->context));
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invalidate_page_directory();
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}
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static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
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{
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/* Nothing to do. */
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}
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#endif /* _XTENSA_MMU_CONTEXT_H */
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