2009-05-29 01:56:16 +08:00
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/*
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* OMAP3 Power Management Routines
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*
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* Copyright (C) 2006-2008 Nokia Corporation
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* Tony Lindgren <tony@atomide.com>
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* Jouni Hogander
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*
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2008-09-26 20:20:07 +08:00
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* Copyright (C) 2007 Texas Instruments, Inc.
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* Rajendra Nayak <rnayak@ti.com>
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*
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2009-05-29 01:56:16 +08:00
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* Copyright (C) 2005 Texas Instruments, Inc.
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* Richard Woodruff <r-woodruff2@ti.com>
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*
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* Based on pm.c for omap1
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/pm.h>
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#include <linux/suspend.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/list.h>
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#include <linux/err.h>
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#include <linux/gpio.h>
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2009-10-21 00:40:47 +08:00
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#include <plat/sram.h>
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#include <plat/clockdomain.h>
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#include <plat/powerdomain.h>
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#include <plat/control.h>
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#include <plat/serial.h>
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2008-09-26 20:19:56 +08:00
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#include <plat/sdrc.h>
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2008-09-26 20:20:07 +08:00
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#include <plat/prcm.h>
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#include <plat/gpmc.h>
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2008-08-28 21:13:31 +08:00
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#include <plat/dma.h>
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2009-05-29 01:56:16 +08:00
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2008-09-26 20:19:34 +08:00
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#include <asm/tlbflush.h>
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2009-05-29 01:56:16 +08:00
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#include "cm.h"
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#include "cm-regbits-34xx.h"
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#include "prm-regbits-34xx.h"
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#include "prm.h"
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#include "pm.h"
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2008-09-26 20:20:07 +08:00
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/* Scratchpad offsets */
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#define OMAP343X_TABLE_ADDRESS_OFFSET 0x31
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#define OMAP343X_TABLE_VALUE_OFFSET 0x30
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#define OMAP343X_CONTROL_REG_VALUE_OFFSET 0x32
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2009-05-29 01:56:16 +08:00
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struct power_state {
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struct powerdomain *pwrdm;
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u32 next_state;
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2009-06-25 02:39:18 +08:00
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#ifdef CONFIG_SUSPEND
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2009-05-29 01:56:16 +08:00
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u32 saved_state;
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2009-06-25 02:39:18 +08:00
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#endif
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2009-05-29 01:56:16 +08:00
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struct list_head node;
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};
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static LIST_HEAD(pwrst_list);
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static void (*_omap_sram_idle)(u32 *addr, int save_state);
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2008-09-26 20:19:22 +08:00
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static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
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static struct powerdomain *core_pwrdm, *per_pwrdm;
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static int set_pwrdm_state(struct powerdomain *pwrdm, u32 state);
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2009-05-29 01:56:16 +08:00
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2008-09-26 20:20:07 +08:00
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static inline void omap3_per_save_context(void)
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{
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omap_gpio_save_context();
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}
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static inline void omap3_per_restore_context(void)
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{
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omap_gpio_restore_context();
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}
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static void omap3_core_save_context(void)
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{
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u32 control_padconf_off;
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/* Save the padconf registers */
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control_padconf_off = omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_OFF);
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control_padconf_off |= START_PADCONF_SAVE;
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omap_ctrl_writel(control_padconf_off, OMAP343X_CONTROL_PADCONF_OFF);
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/* wait for the save to complete */
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while (!omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS)
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& PADCONF_SAVE_DONE)
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;
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/* Save the Interrupt controller context */
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omap_intc_save_context();
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/* Save the GPMC context */
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omap3_gpmc_save_context();
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/* Save the system control module context, padconf already save above*/
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omap3_control_save_context();
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2008-08-28 21:13:31 +08:00
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omap_dma_global_context_save();
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2008-09-26 20:20:07 +08:00
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}
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static void omap3_core_restore_context(void)
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{
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/* Restore the control module context, padconf restored by h/w */
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omap3_control_restore_context();
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/* Restore the GPMC context */
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omap3_gpmc_restore_context();
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/* Restore the interrupt controller context */
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omap_intc_restore_context();
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2008-08-28 21:13:31 +08:00
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omap_dma_global_context_restore();
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2008-09-26 20:20:07 +08:00
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}
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2009-06-27 13:07:25 +08:00
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/*
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* PRCM Interrupt Handler Helper Function
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*
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* The purpose of this function is to clear any wake-up events latched
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* in the PRCM PM_WKST_x registers. It is possible that a wake-up event
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* may occur whilst attempting to clear a PM_WKST_x register and thus
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* set another bit in this register. A while loop is used to ensure
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* that any peripheral wake-up events occurring while attempting to
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* clear the PM_WKST_x are detected and cleared.
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*/
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2009-07-23 01:29:02 +08:00
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static int prcm_clear_mod_irqs(s16 module, u8 regs)
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2009-05-29 01:56:16 +08:00
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{
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2009-07-18 08:33:09 +08:00
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u32 wkst, fclk, iclk, clken;
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2009-06-27 13:07:25 +08:00
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u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
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u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
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u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
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2009-07-23 01:18:07 +08:00
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u16 grpsel_off = (regs == 3) ?
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OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
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2009-07-23 01:29:02 +08:00
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int c = 0;
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2009-05-29 01:56:16 +08:00
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2009-06-27 13:07:25 +08:00
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wkst = prm_read_mod_reg(module, wkst_off);
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2009-07-23 01:18:07 +08:00
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wkst &= prm_read_mod_reg(module, grpsel_off);
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2009-05-29 01:56:16 +08:00
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if (wkst) {
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2009-06-27 13:07:25 +08:00
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iclk = cm_read_mod_reg(module, iclk_off);
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fclk = cm_read_mod_reg(module, fclk_off);
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while (wkst) {
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2009-07-18 08:33:09 +08:00
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clken = wkst;
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cm_set_mod_reg_bits(clken, module, iclk_off);
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/*
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* For USBHOST, we don't know whether HOST1 or
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* HOST2 woke us up, so enable both f-clocks
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*/
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if (module == OMAP3430ES2_USBHOST_MOD)
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clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
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cm_set_mod_reg_bits(clken, module, fclk_off);
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2009-06-27 13:07:25 +08:00
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prm_write_mod_reg(wkst, module, wkst_off);
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wkst = prm_read_mod_reg(module, wkst_off);
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2009-07-23 01:29:02 +08:00
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c++;
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2009-06-27 13:07:25 +08:00
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}
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cm_write_mod_reg(iclk, module, iclk_off);
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cm_write_mod_reg(fclk, module, fclk_off);
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2009-05-29 01:56:16 +08:00
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}
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2009-07-23 01:29:02 +08:00
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return c;
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}
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static int _prcm_int_handle_wakeup(void)
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{
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int c;
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c = prcm_clear_mod_irqs(WKUP_MOD, 1);
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c += prcm_clear_mod_irqs(CORE_MOD, 1);
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c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1);
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if (omap_rev() > OMAP3430_REV_ES1_0) {
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c += prcm_clear_mod_irqs(CORE_MOD, 3);
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c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1);
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}
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return c;
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2009-06-27 13:07:25 +08:00
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}
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2009-05-29 01:56:16 +08:00
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2009-06-27 13:07:25 +08:00
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/*
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* PRCM Interrupt Handler
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*
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* The PRM_IRQSTATUS_MPU register indicates if there are any pending
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* interrupts from the PRCM for the MPU. These bits must be cleared in
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* order to clear the PRCM interrupt. The PRCM interrupt handler is
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* implemented to simply clear the PRM_IRQSTATUS_MPU in order to clear
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* the PRCM interrupt. Please note that bit 0 of the PRM_IRQSTATUS_MPU
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* register indicates that a wake-up event is pending for the MPU and
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* this bit can only be cleared if the all the wake-up events latched
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* in the various PM_WKST_x registers have been cleared. The interrupt
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* handler is implemented using a do-while loop so that if a wake-up
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* event occurred during the processing of the prcm interrupt handler
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* (setting a bit in the corresponding PM_WKST_x register and thus
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* preventing us from clearing bit 0 of the PRM_IRQSTATUS_MPU register)
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* this would be handled.
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*/
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static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
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{
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u32 irqstatus_mpu;
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2009-07-23 01:29:02 +08:00
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int c = 0;
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2009-06-27 13:07:25 +08:00
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do {
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irqstatus_mpu = prm_read_mod_reg(OCP_MOD,
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OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
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2009-07-23 01:29:02 +08:00
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if (irqstatus_mpu & (OMAP3430_WKUP_ST | OMAP3430_IO_ST)) {
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c = _prcm_int_handle_wakeup();
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/*
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* Is the MPU PRCM interrupt handler racing with the
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* IVA2 PRCM interrupt handler ?
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*/
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WARN(c == 0, "prcm: WARNING: PRCM indicated MPU wakeup "
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"but no wakeup sources are marked\n");
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} else {
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/* XXX we need to expand our PRCM interrupt handler */
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WARN(1, "prcm: WARNING: PRCM interrupt received, but "
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"no code to handle it (%08x)\n", irqstatus_mpu);
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}
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2009-06-27 13:07:25 +08:00
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prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
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OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
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2009-05-29 01:56:16 +08:00
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2009-06-27 13:07:25 +08:00
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} while (prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET));
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2009-05-29 01:56:16 +08:00
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return IRQ_HANDLED;
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}
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2008-09-26 20:19:34 +08:00
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static void restore_control_register(u32 val)
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{
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__asm__ __volatile__ ("mcr p15, 0, %0, c1, c0, 0" : : "r" (val));
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}
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/* Function to restore the table entry that was modified for enabling MMU */
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static void restore_table_entry(void)
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{
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u32 *scratchpad_address;
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u32 previous_value, control_reg_value;
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u32 *address;
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scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD);
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/* Get address of entry that was modified */
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address = (u32 *)__raw_readl(scratchpad_address +
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OMAP343X_TABLE_ADDRESS_OFFSET);
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/* Get the previous value which needs to be restored */
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previous_value = __raw_readl(scratchpad_address +
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OMAP343X_TABLE_VALUE_OFFSET);
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address = __va(address);
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*address = previous_value;
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flush_tlb_all();
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control_reg_value = __raw_readl(scratchpad_address
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+ OMAP343X_CONTROL_REG_VALUE_OFFSET);
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/* This will enable caches and prediction */
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restore_control_register(control_reg_value);
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}
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2009-05-29 01:56:16 +08:00
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static void omap_sram_idle(void)
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{
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/* Variable to tell what needs to be saved and restored
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* in omap_sram_idle*/
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/* save_state = 0 => Nothing to save and restored */
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/* save_state = 1 => Only L1 and logic lost */
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/* save_state = 2 => Only L2 lost */
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/* save_state = 3 => L1, L2 and logic lost */
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2008-09-26 20:19:22 +08:00
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int save_state = 0;
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int mpu_next_state = PWRDM_POWER_ON;
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int per_next_state = PWRDM_POWER_ON;
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int core_next_state = PWRDM_POWER_ON;
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2008-09-26 20:20:07 +08:00
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int core_prev_state, per_prev_state;
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2009-05-29 01:56:16 +08:00
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if (!_omap_sram_idle)
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return;
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2008-09-26 20:19:22 +08:00
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pwrdm_clear_all_prev_pwrst(mpu_pwrdm);
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pwrdm_clear_all_prev_pwrst(neon_pwrdm);
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pwrdm_clear_all_prev_pwrst(core_pwrdm);
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pwrdm_clear_all_prev_pwrst(per_pwrdm);
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2009-05-29 01:56:16 +08:00
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mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
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switch (mpu_next_state) {
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2008-09-26 20:19:22 +08:00
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case PWRDM_POWER_ON:
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2009-05-29 01:56:16 +08:00
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case PWRDM_POWER_RET:
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/* No need to save context */
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save_state = 0;
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break;
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2008-09-26 20:19:56 +08:00
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case PWRDM_POWER_OFF:
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save_state = 3;
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break;
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2009-05-29 01:56:16 +08:00
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default:
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/* Invalid state */
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printk(KERN_ERR "Invalid mpu state in sram_idle\n");
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return;
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}
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2008-10-15 22:48:44 +08:00
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pwrdm_pre_transition();
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2008-09-26 20:19:22 +08:00
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/* NEON control */
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if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
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set_pwrdm_state(neon_pwrdm, mpu_next_state);
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/* CORE & PER */
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core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
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if (core_next_state < PWRDM_POWER_ON) {
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omap2_gpio_prepare_for_retention();
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omap_uart_prepare_idle(0);
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omap_uart_prepare_idle(1);
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/* PER changes only with core */
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per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
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2008-09-26 20:20:07 +08:00
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|
|
if (per_next_state < PWRDM_POWER_ON) {
|
2008-09-26 20:19:22 +08:00
|
|
|
omap_uart_prepare_idle(2);
|
2008-09-26 20:20:07 +08:00
|
|
|
if (per_next_state == PWRDM_POWER_OFF)
|
|
|
|
omap3_per_save_context();
|
|
|
|
}
|
|
|
|
if (core_next_state == PWRDM_POWER_OFF) {
|
|
|
|
omap3_core_save_context();
|
|
|
|
omap3_prcm_save_context();
|
|
|
|
}
|
2008-09-26 20:19:22 +08:00
|
|
|
/* Enable IO-PAD wakeup */
|
|
|
|
prm_set_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN);
|
|
|
|
}
|
2009-05-29 01:56:16 +08:00
|
|
|
|
2008-09-26 20:19:56 +08:00
|
|
|
/*
|
|
|
|
* omap3_arm_context is the location where ARM registers
|
|
|
|
* get saved. The restore path then reads from this
|
|
|
|
* location and restores them back.
|
|
|
|
*/
|
|
|
|
_omap_sram_idle(omap3_arm_context, save_state);
|
2009-05-29 01:56:16 +08:00
|
|
|
cpu_init();
|
|
|
|
|
2008-09-26 20:19:34 +08:00
|
|
|
/* Restore table entry modified during MMU restoration */
|
|
|
|
if (pwrdm_read_prev_pwrst(mpu_pwrdm) == PWRDM_POWER_OFF)
|
|
|
|
restore_table_entry();
|
|
|
|
|
2008-09-26 20:19:22 +08:00
|
|
|
if (core_next_state < PWRDM_POWER_ON) {
|
|
|
|
if (per_next_state < PWRDM_POWER_ON)
|
|
|
|
omap_uart_resume_idle(2);
|
|
|
|
omap_uart_resume_idle(1);
|
|
|
|
omap_uart_resume_idle(0);
|
|
|
|
|
|
|
|
/* Disable IO-PAD wakeup */
|
|
|
|
prm_clear_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN);
|
2008-09-26 20:20:07 +08:00
|
|
|
core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm);
|
|
|
|
if (core_prev_state == PWRDM_POWER_OFF) {
|
|
|
|
omap3_core_restore_context();
|
|
|
|
omap3_prcm_restore_context();
|
|
|
|
omap3_sram_restore_context();
|
|
|
|
}
|
|
|
|
if (per_next_state < PWRDM_POWER_ON) {
|
|
|
|
per_prev_state =
|
|
|
|
pwrdm_read_prev_pwrst(per_pwrdm);
|
|
|
|
if (per_prev_state == PWRDM_POWER_OFF)
|
|
|
|
omap3_per_restore_context();
|
|
|
|
}
|
2008-09-26 20:19:22 +08:00
|
|
|
omap2_gpio_resume_after_retention();
|
|
|
|
}
|
2008-10-15 22:48:44 +08:00
|
|
|
|
|
|
|
pwrdm_post_transition();
|
|
|
|
|
2009-05-29 01:56:16 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Check if functional clocks are enabled before entering
|
|
|
|
* sleep. This function could be behind CONFIG_PM_DEBUG
|
|
|
|
* when all drivers are configuring their sysconfig registers
|
|
|
|
* properly and using their clocks properly.
|
|
|
|
*/
|
|
|
|
static int omap3_fclks_active(void)
|
|
|
|
{
|
|
|
|
u32 fck_core1 = 0, fck_core3 = 0, fck_sgx = 0, fck_dss = 0,
|
|
|
|
fck_cam = 0, fck_per = 0, fck_usbhost = 0;
|
|
|
|
|
|
|
|
fck_core1 = cm_read_mod_reg(CORE_MOD,
|
|
|
|
CM_FCLKEN1);
|
|
|
|
if (omap_rev() > OMAP3430_REV_ES1_0) {
|
|
|
|
fck_core3 = cm_read_mod_reg(CORE_MOD,
|
|
|
|
OMAP3430ES2_CM_FCLKEN3);
|
|
|
|
fck_sgx = cm_read_mod_reg(OMAP3430ES2_SGX_MOD,
|
|
|
|
CM_FCLKEN);
|
|
|
|
fck_usbhost = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
|
|
|
|
CM_FCLKEN);
|
|
|
|
} else
|
|
|
|
fck_sgx = cm_read_mod_reg(GFX_MOD,
|
|
|
|
OMAP3430ES2_CM_FCLKEN3);
|
|
|
|
fck_dss = cm_read_mod_reg(OMAP3430_DSS_MOD,
|
|
|
|
CM_FCLKEN);
|
|
|
|
fck_cam = cm_read_mod_reg(OMAP3430_CAM_MOD,
|
|
|
|
CM_FCLKEN);
|
|
|
|
fck_per = cm_read_mod_reg(OMAP3430_PER_MOD,
|
|
|
|
CM_FCLKEN);
|
OMAP3: PM: UART: disable clocks when idle and off-mode support
This patch allows the UART clocks to be disabled when the OMAP UARTs
are inactive, thus permitting the chip to hit retention in idle.
After the expiration of an activity timer, each UART is allowed to
disable its clocks so the system can enter retention. The activity
timer is (re)activated on any UART interrupt, UART wake event or any
IO pad wakeup. The actual disable of the UART clocks is done in the
'prepare_idle' hook called from the OMAP idle loop.
While the activity timer is active, the smart-idle mode of the UART is
also disabled. This is due to a "feature" of the UART module that
after a UART wakeup, the smart-idle mode may be entered before the
UART has communicated the interrupt, or upon TX, an idle mode may be
entered before the TX FIFOs are emptied.
Upon suspend, the 'prepare_suspend' hook cancels any pending activity
timers and allows the clocks to be disabled immediately.
In addition, upon disabling clocks the UART state is saved in case
of an off-mode transition while clocks are off.
Special thanks to Tero Kristo for the initial ideas and first versions
of UART idle support, and to Jouni Hogander for extra testing and
bugfixes.
Tested on OMAP3 (Beagle, RX51, SDP, EVM) and OMAP2 (n810)
Cc: Tero Kristo <tero.kristo@nokia.com>
Cc: Jouni Hogander <jouni.hogander@nokia.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
2009-02-05 02:51:40 +08:00
|
|
|
|
|
|
|
/* Ignore UART clocks. These are handled by UART core (serial.c) */
|
|
|
|
fck_core1 &= ~(OMAP3430_EN_UART1 | OMAP3430_EN_UART2);
|
|
|
|
fck_per &= ~OMAP3430_EN_UART3;
|
|
|
|
|
2009-05-29 01:56:16 +08:00
|
|
|
if (fck_core1 | fck_core3 | fck_sgx | fck_dss |
|
|
|
|
fck_cam | fck_per | fck_usbhost)
|
|
|
|
return 1;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int omap3_can_sleep(void)
|
|
|
|
{
|
OMAP3: PM: UART: disable clocks when idle and off-mode support
This patch allows the UART clocks to be disabled when the OMAP UARTs
are inactive, thus permitting the chip to hit retention in idle.
After the expiration of an activity timer, each UART is allowed to
disable its clocks so the system can enter retention. The activity
timer is (re)activated on any UART interrupt, UART wake event or any
IO pad wakeup. The actual disable of the UART clocks is done in the
'prepare_idle' hook called from the OMAP idle loop.
While the activity timer is active, the smart-idle mode of the UART is
also disabled. This is due to a "feature" of the UART module that
after a UART wakeup, the smart-idle mode may be entered before the
UART has communicated the interrupt, or upon TX, an idle mode may be
entered before the TX FIFOs are emptied.
Upon suspend, the 'prepare_suspend' hook cancels any pending activity
timers and allows the clocks to be disabled immediately.
In addition, upon disabling clocks the UART state is saved in case
of an off-mode transition while clocks are off.
Special thanks to Tero Kristo for the initial ideas and first versions
of UART idle support, and to Jouni Hogander for extra testing and
bugfixes.
Tested on OMAP3 (Beagle, RX51, SDP, EVM) and OMAP2 (n810)
Cc: Tero Kristo <tero.kristo@nokia.com>
Cc: Jouni Hogander <jouni.hogander@nokia.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
2009-02-05 02:51:40 +08:00
|
|
|
if (!omap_uart_can_sleep())
|
|
|
|
return 0;
|
2009-05-29 01:56:16 +08:00
|
|
|
if (omap3_fclks_active())
|
|
|
|
return 0;
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* This sets pwrdm state (other than mpu & core. Currently only ON &
|
|
|
|
* RET are supported. Function is assuming that clkdm doesn't have
|
|
|
|
* hw_sup mode enabled. */
|
|
|
|
static int set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
|
|
|
|
{
|
|
|
|
u32 cur_state;
|
|
|
|
int sleep_switch = 0;
|
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
if (pwrdm == NULL || IS_ERR(pwrdm))
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
while (!(pwrdm->pwrsts & (1 << state))) {
|
|
|
|
if (state == PWRDM_POWER_OFF)
|
|
|
|
return ret;
|
|
|
|
state--;
|
|
|
|
}
|
|
|
|
|
|
|
|
cur_state = pwrdm_read_next_pwrst(pwrdm);
|
|
|
|
if (cur_state == state)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
if (pwrdm_read_pwrst(pwrdm) < PWRDM_POWER_ON) {
|
|
|
|
omap2_clkdm_wakeup(pwrdm->pwrdm_clkdms[0]);
|
|
|
|
sleep_switch = 1;
|
|
|
|
pwrdm_wait_transition(pwrdm);
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = pwrdm_set_next_pwrst(pwrdm, state);
|
|
|
|
if (ret) {
|
|
|
|
printk(KERN_ERR "Unable to set state of powerdomain: %s\n",
|
|
|
|
pwrdm->name);
|
|
|
|
goto err;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (sleep_switch) {
|
|
|
|
omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]);
|
|
|
|
pwrdm_wait_transition(pwrdm);
|
2008-10-15 22:48:44 +08:00
|
|
|
pwrdm_state_switch(pwrdm);
|
2009-05-29 01:56:16 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
err:
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void omap3_pm_idle(void)
|
|
|
|
{
|
|
|
|
local_irq_disable();
|
|
|
|
local_fiq_disable();
|
|
|
|
|
|
|
|
if (!omap3_can_sleep())
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
if (omap_irq_pending())
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
omap_sram_idle();
|
|
|
|
|
|
|
|
out:
|
|
|
|
local_fiq_enable();
|
|
|
|
local_irq_enable();
|
|
|
|
}
|
|
|
|
|
2009-06-25 02:39:18 +08:00
|
|
|
#ifdef CONFIG_SUSPEND
|
2009-03-05 22:32:23 +08:00
|
|
|
static suspend_state_t suspend_state;
|
|
|
|
|
2009-05-29 01:56:16 +08:00
|
|
|
static int omap3_pm_prepare(void)
|
|
|
|
{
|
|
|
|
disable_hlt();
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int omap3_pm_suspend(void)
|
|
|
|
{
|
|
|
|
struct power_state *pwrst;
|
|
|
|
int state, ret = 0;
|
|
|
|
|
|
|
|
/* Read current next_pwrsts */
|
|
|
|
list_for_each_entry(pwrst, &pwrst_list, node)
|
|
|
|
pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
|
|
|
|
/* Set ones wanted by suspend */
|
|
|
|
list_for_each_entry(pwrst, &pwrst_list, node) {
|
|
|
|
if (set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
|
|
|
|
goto restore;
|
|
|
|
if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
|
|
|
|
goto restore;
|
|
|
|
}
|
|
|
|
|
OMAP3: PM: UART: disable clocks when idle and off-mode support
This patch allows the UART clocks to be disabled when the OMAP UARTs
are inactive, thus permitting the chip to hit retention in idle.
After the expiration of an activity timer, each UART is allowed to
disable its clocks so the system can enter retention. The activity
timer is (re)activated on any UART interrupt, UART wake event or any
IO pad wakeup. The actual disable of the UART clocks is done in the
'prepare_idle' hook called from the OMAP idle loop.
While the activity timer is active, the smart-idle mode of the UART is
also disabled. This is due to a "feature" of the UART module that
after a UART wakeup, the smart-idle mode may be entered before the
UART has communicated the interrupt, or upon TX, an idle mode may be
entered before the TX FIFOs are emptied.
Upon suspend, the 'prepare_suspend' hook cancels any pending activity
timers and allows the clocks to be disabled immediately.
In addition, upon disabling clocks the UART state is saved in case
of an off-mode transition while clocks are off.
Special thanks to Tero Kristo for the initial ideas and first versions
of UART idle support, and to Jouni Hogander for extra testing and
bugfixes.
Tested on OMAP3 (Beagle, RX51, SDP, EVM) and OMAP2 (n810)
Cc: Tero Kristo <tero.kristo@nokia.com>
Cc: Jouni Hogander <jouni.hogander@nokia.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
2009-02-05 02:51:40 +08:00
|
|
|
omap_uart_prepare_suspend();
|
2009-05-29 01:56:16 +08:00
|
|
|
omap_sram_idle();
|
|
|
|
|
|
|
|
restore:
|
|
|
|
/* Restore next_pwrsts */
|
|
|
|
list_for_each_entry(pwrst, &pwrst_list, node) {
|
|
|
|
state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
|
|
|
|
if (state > pwrst->next_state) {
|
|
|
|
printk(KERN_INFO "Powerdomain (%s) didn't enter "
|
|
|
|
"target state %d\n",
|
|
|
|
pwrst->pwrdm->name, pwrst->next_state);
|
|
|
|
ret = -1;
|
|
|
|
}
|
2008-10-29 18:06:04 +08:00
|
|
|
set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
|
2009-05-29 01:56:16 +08:00
|
|
|
}
|
|
|
|
if (ret)
|
|
|
|
printk(KERN_ERR "Could not enter target state in pm_suspend\n");
|
|
|
|
else
|
|
|
|
printk(KERN_INFO "Successfully put all powerdomains "
|
|
|
|
"to target state\n");
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2009-03-05 22:32:23 +08:00
|
|
|
static int omap3_pm_enter(suspend_state_t unused)
|
2009-05-29 01:56:16 +08:00
|
|
|
{
|
|
|
|
int ret = 0;
|
|
|
|
|
2009-03-05 22:32:23 +08:00
|
|
|
switch (suspend_state) {
|
2009-05-29 01:56:16 +08:00
|
|
|
case PM_SUSPEND_STANDBY:
|
|
|
|
case PM_SUSPEND_MEM:
|
|
|
|
ret = omap3_pm_suspend();
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
ret = -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void omap3_pm_finish(void)
|
|
|
|
{
|
|
|
|
enable_hlt();
|
|
|
|
}
|
|
|
|
|
2009-03-05 22:32:23 +08:00
|
|
|
/* Hooks to enable / disable UART interrupts during suspend */
|
|
|
|
static int omap3_pm_begin(suspend_state_t state)
|
|
|
|
{
|
|
|
|
suspend_state = state;
|
|
|
|
omap_uart_enable_irqs(0);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void omap3_pm_end(void)
|
|
|
|
{
|
|
|
|
suspend_state = PM_SUSPEND_ON;
|
|
|
|
omap_uart_enable_irqs(1);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2009-05-29 01:56:16 +08:00
|
|
|
static struct platform_suspend_ops omap_pm_ops = {
|
2009-03-05 22:32:23 +08:00
|
|
|
.begin = omap3_pm_begin,
|
|
|
|
.end = omap3_pm_end,
|
2009-05-29 01:56:16 +08:00
|
|
|
.prepare = omap3_pm_prepare,
|
|
|
|
.enter = omap3_pm_enter,
|
|
|
|
.finish = omap3_pm_finish,
|
|
|
|
.valid = suspend_valid_only_mem,
|
|
|
|
};
|
2009-06-25 02:39:18 +08:00
|
|
|
#endif /* CONFIG_SUSPEND */
|
2009-05-29 01:56:16 +08:00
|
|
|
|
2008-11-26 03:48:24 +08:00
|
|
|
|
|
|
|
/**
|
|
|
|
* omap3_iva_idle(): ensure IVA is in idle so it can be put into
|
|
|
|
* retention
|
|
|
|
*
|
|
|
|
* In cases where IVA2 is activated by bootcode, it may prevent
|
|
|
|
* full-chip retention or off-mode because it is not idle. This
|
|
|
|
* function forces the IVA2 into idle state so it can go
|
|
|
|
* into retention/off and thus allow full-chip retention/off.
|
|
|
|
*
|
|
|
|
**/
|
|
|
|
static void __init omap3_iva_idle(void)
|
|
|
|
{
|
|
|
|
/* ensure IVA2 clock is disabled */
|
|
|
|
cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
|
|
|
|
|
|
|
|
/* if no clock activity, nothing else to do */
|
|
|
|
if (!(cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
|
|
|
|
OMAP3430_CLKACTIVITY_IVA2_MASK))
|
|
|
|
return;
|
|
|
|
|
|
|
|
/* Reset IVA2 */
|
|
|
|
prm_write_mod_reg(OMAP3430_RST1_IVA2 |
|
|
|
|
OMAP3430_RST2_IVA2 |
|
|
|
|
OMAP3430_RST3_IVA2,
|
|
|
|
OMAP3430_IVA2_MOD, RM_RSTCTRL);
|
|
|
|
|
|
|
|
/* Enable IVA2 clock */
|
|
|
|
cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2,
|
|
|
|
OMAP3430_IVA2_MOD, CM_FCLKEN);
|
|
|
|
|
|
|
|
/* Set IVA2 boot mode to 'idle' */
|
|
|
|
omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
|
|
|
|
OMAP343X_CONTROL_IVA2_BOOTMOD);
|
|
|
|
|
|
|
|
/* Un-reset IVA2 */
|
|
|
|
prm_write_mod_reg(0, OMAP3430_IVA2_MOD, RM_RSTCTRL);
|
|
|
|
|
|
|
|
/* Disable IVA2 clock */
|
|
|
|
cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
|
|
|
|
|
|
|
|
/* Reset IVA2 */
|
|
|
|
prm_write_mod_reg(OMAP3430_RST1_IVA2 |
|
|
|
|
OMAP3430_RST2_IVA2 |
|
|
|
|
OMAP3430_RST3_IVA2,
|
|
|
|
OMAP3430_IVA2_MOD, RM_RSTCTRL);
|
|
|
|
}
|
|
|
|
|
2009-04-29 06:27:44 +08:00
|
|
|
static void __init omap3_d2d_idle(void)
|
2009-05-29 01:56:16 +08:00
|
|
|
{
|
2009-04-29 06:27:44 +08:00
|
|
|
u16 mask, padconf;
|
|
|
|
|
|
|
|
/* In a stand alone OMAP3430 where there is not a stacked
|
|
|
|
* modem for the D2D Idle Ack and D2D MStandby must be pulled
|
|
|
|
* high. S CONTROL_PADCONF_SAD2D_IDLEACK and
|
|
|
|
* CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */
|
|
|
|
mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
|
|
|
|
padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
|
|
|
|
padconf |= mask;
|
|
|
|
omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
|
|
|
|
|
|
|
|
padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
|
|
|
|
padconf |= mask;
|
|
|
|
omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
|
|
|
|
|
2009-05-29 01:56:16 +08:00
|
|
|
/* reset modem */
|
|
|
|
prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON |
|
|
|
|
OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST,
|
|
|
|
CORE_MOD, RM_RSTCTRL);
|
|
|
|
prm_write_mod_reg(0, CORE_MOD, RM_RSTCTRL);
|
2009-04-29 06:27:44 +08:00
|
|
|
}
|
2009-05-29 01:56:16 +08:00
|
|
|
|
2009-04-29 06:27:44 +08:00
|
|
|
static void __init prcm_setup_regs(void)
|
|
|
|
{
|
2009-05-29 01:56:16 +08:00
|
|
|
/* XXX Reset all wkdeps. This should be done when initializing
|
|
|
|
* powerdomains */
|
|
|
|
prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP);
|
|
|
|
prm_write_mod_reg(0, MPU_MOD, PM_WKDEP);
|
|
|
|
prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP);
|
|
|
|
prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP);
|
|
|
|
prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP);
|
|
|
|
prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP);
|
|
|
|
if (omap_rev() > OMAP3430_REV_ES1_0) {
|
|
|
|
prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP);
|
|
|
|
prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
|
|
|
|
} else
|
|
|
|
prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Enable interface clock autoidle for all modules.
|
|
|
|
* Note that in the long run this should be done by clockfw
|
|
|
|
*/
|
|
|
|
cm_write_mod_reg(
|
2009-04-29 06:27:44 +08:00
|
|
|
OMAP3430_AUTO_MODEM |
|
2009-05-29 01:56:16 +08:00
|
|
|
OMAP3430ES2_AUTO_MMC3 |
|
|
|
|
OMAP3430ES2_AUTO_ICR |
|
|
|
|
OMAP3430_AUTO_AES2 |
|
|
|
|
OMAP3430_AUTO_SHA12 |
|
|
|
|
OMAP3430_AUTO_DES2 |
|
|
|
|
OMAP3430_AUTO_MMC2 |
|
|
|
|
OMAP3430_AUTO_MMC1 |
|
|
|
|
OMAP3430_AUTO_MSPRO |
|
|
|
|
OMAP3430_AUTO_HDQ |
|
|
|
|
OMAP3430_AUTO_MCSPI4 |
|
|
|
|
OMAP3430_AUTO_MCSPI3 |
|
|
|
|
OMAP3430_AUTO_MCSPI2 |
|
|
|
|
OMAP3430_AUTO_MCSPI1 |
|
|
|
|
OMAP3430_AUTO_I2C3 |
|
|
|
|
OMAP3430_AUTO_I2C2 |
|
|
|
|
OMAP3430_AUTO_I2C1 |
|
|
|
|
OMAP3430_AUTO_UART2 |
|
|
|
|
OMAP3430_AUTO_UART1 |
|
|
|
|
OMAP3430_AUTO_GPT11 |
|
|
|
|
OMAP3430_AUTO_GPT10 |
|
|
|
|
OMAP3430_AUTO_MCBSP5 |
|
|
|
|
OMAP3430_AUTO_MCBSP1 |
|
|
|
|
OMAP3430ES1_AUTO_FAC | /* This is es1 only */
|
|
|
|
OMAP3430_AUTO_MAILBOXES |
|
|
|
|
OMAP3430_AUTO_OMAPCTRL |
|
|
|
|
OMAP3430ES1_AUTO_FSHOSTUSB |
|
|
|
|
OMAP3430_AUTO_HSOTGUSB |
|
2009-04-29 06:27:44 +08:00
|
|
|
OMAP3430_AUTO_SAD2D |
|
2009-05-29 01:56:16 +08:00
|
|
|
OMAP3430_AUTO_SSI,
|
|
|
|
CORE_MOD, CM_AUTOIDLE1);
|
|
|
|
|
|
|
|
cm_write_mod_reg(
|
|
|
|
OMAP3430_AUTO_PKA |
|
|
|
|
OMAP3430_AUTO_AES1 |
|
|
|
|
OMAP3430_AUTO_RNG |
|
|
|
|
OMAP3430_AUTO_SHA11 |
|
|
|
|
OMAP3430_AUTO_DES1,
|
|
|
|
CORE_MOD, CM_AUTOIDLE2);
|
|
|
|
|
|
|
|
if (omap_rev() > OMAP3430_REV_ES1_0) {
|
|
|
|
cm_write_mod_reg(
|
2009-04-29 06:27:44 +08:00
|
|
|
OMAP3430_AUTO_MAD2D |
|
2009-05-29 01:56:16 +08:00
|
|
|
OMAP3430ES2_AUTO_USBTLL,
|
|
|
|
CORE_MOD, CM_AUTOIDLE3);
|
|
|
|
}
|
|
|
|
|
|
|
|
cm_write_mod_reg(
|
|
|
|
OMAP3430_AUTO_WDT2 |
|
|
|
|
OMAP3430_AUTO_WDT1 |
|
|
|
|
OMAP3430_AUTO_GPIO1 |
|
|
|
|
OMAP3430_AUTO_32KSYNC |
|
|
|
|
OMAP3430_AUTO_GPT12 |
|
|
|
|
OMAP3430_AUTO_GPT1 ,
|
|
|
|
WKUP_MOD, CM_AUTOIDLE);
|
|
|
|
|
|
|
|
cm_write_mod_reg(
|
|
|
|
OMAP3430_AUTO_DSS,
|
|
|
|
OMAP3430_DSS_MOD,
|
|
|
|
CM_AUTOIDLE);
|
|
|
|
|
|
|
|
cm_write_mod_reg(
|
|
|
|
OMAP3430_AUTO_CAM,
|
|
|
|
OMAP3430_CAM_MOD,
|
|
|
|
CM_AUTOIDLE);
|
|
|
|
|
|
|
|
cm_write_mod_reg(
|
|
|
|
OMAP3430_AUTO_GPIO6 |
|
|
|
|
OMAP3430_AUTO_GPIO5 |
|
|
|
|
OMAP3430_AUTO_GPIO4 |
|
|
|
|
OMAP3430_AUTO_GPIO3 |
|
|
|
|
OMAP3430_AUTO_GPIO2 |
|
|
|
|
OMAP3430_AUTO_WDT3 |
|
|
|
|
OMAP3430_AUTO_UART3 |
|
|
|
|
OMAP3430_AUTO_GPT9 |
|
|
|
|
OMAP3430_AUTO_GPT8 |
|
|
|
|
OMAP3430_AUTO_GPT7 |
|
|
|
|
OMAP3430_AUTO_GPT6 |
|
|
|
|
OMAP3430_AUTO_GPT5 |
|
|
|
|
OMAP3430_AUTO_GPT4 |
|
|
|
|
OMAP3430_AUTO_GPT3 |
|
|
|
|
OMAP3430_AUTO_GPT2 |
|
|
|
|
OMAP3430_AUTO_MCBSP4 |
|
|
|
|
OMAP3430_AUTO_MCBSP3 |
|
|
|
|
OMAP3430_AUTO_MCBSP2,
|
|
|
|
OMAP3430_PER_MOD,
|
|
|
|
CM_AUTOIDLE);
|
|
|
|
|
|
|
|
if (omap_rev() > OMAP3430_REV_ES1_0) {
|
|
|
|
cm_write_mod_reg(
|
|
|
|
OMAP3430ES2_AUTO_USBHOST,
|
|
|
|
OMAP3430ES2_USBHOST_MOD,
|
|
|
|
CM_AUTOIDLE);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Set all plls to autoidle. This is needed until autoidle is
|
|
|
|
* enabled by clockfw
|
|
|
|
*/
|
|
|
|
cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT,
|
|
|
|
OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
|
|
|
|
cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT,
|
|
|
|
MPU_MOD,
|
|
|
|
CM_AUTOIDLE2);
|
|
|
|
cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) |
|
|
|
|
(1 << OMAP3430_AUTO_CORE_DPLL_SHIFT),
|
|
|
|
PLL_MOD,
|
|
|
|
CM_AUTOIDLE);
|
|
|
|
cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT,
|
|
|
|
PLL_MOD,
|
|
|
|
CM_AUTOIDLE2);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Enable control of expternal oscillator through
|
|
|
|
* sys_clkreq. In the long run clock framework should
|
|
|
|
* take care of this.
|
|
|
|
*/
|
|
|
|
prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
|
|
|
|
1 << OMAP_AUTOEXTCLKMODE_SHIFT,
|
|
|
|
OMAP3430_GR_MOD,
|
|
|
|
OMAP3_PRM_CLKSRC_CTRL_OFFSET);
|
|
|
|
|
|
|
|
/* setup wakup source */
|
|
|
|
prm_write_mod_reg(OMAP3430_EN_IO | OMAP3430_EN_GPIO1 |
|
|
|
|
OMAP3430_EN_GPT1 | OMAP3430_EN_GPT12,
|
|
|
|
WKUP_MOD, PM_WKEN);
|
|
|
|
/* No need to write EN_IO, that is always enabled */
|
|
|
|
prm_write_mod_reg(OMAP3430_EN_GPIO1 | OMAP3430_EN_GPT1 |
|
|
|
|
OMAP3430_EN_GPT12,
|
|
|
|
WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
|
|
|
|
/* For some reason IO doesn't generate wakeup event even if
|
|
|
|
* it is selected to mpu wakeup goup */
|
|
|
|
prm_write_mod_reg(OMAP3430_IO_EN | OMAP3430_WKUP_EN,
|
|
|
|
OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
|
2008-11-26 03:48:24 +08:00
|
|
|
|
2009-10-23 05:48:13 +08:00
|
|
|
/* Enable wakeups in PER */
|
OMAP3: PM: Enable GPIO module-level wakeups
Currently, only GPIOs in the wakeup domain (GPIOs in bank 0) are
enabled as wakups. This patch also enables GPIOs in the PER
powerdomain (banks 2-6) to be used as possible wakeup sources.
In addition, this patch ensures that all GPIO wakeups can wakeup
the MPU using the PM_MPUGRPSEL_<pwrdm> registers.
NOTE: this doesn't enable the individual GPIOs as wakeups, this simply
enables the per-bank wakeups at the powerdomain level.
This problem was discovered by Mike Chan when preventing the CORE
powerdomain from going into retention/off. When CORE was allowed to
hit retention, GPIO wakeups via IO pad were working fine, but when
CORE remained on, GPIO module-level wakeups were not working properly.
To test, prevent CORE from going inactive/retention/off, thus
preventing the IO chain from being armed:
# echo 3 > /debug/pm_debug/core_pwrdm/suspend
This ensures that GPIO wakeups happen via module-level wakeups and
not via IO pad.
Tested on 3430SDP using the touchscreen GPIO (gpio 2, in WKUP)
Tested on Zoom2 using the QUART interrup GPIO (gpio 102, in PER)
Also, c.f. OMAP PM wiki for troubleshooting GPIO wakeup issues:
http://elinux.org/OMAP_Power_Management
Reported-by: Mike Chan <mikechan@google.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
2009-09-10 23:53:08 +08:00
|
|
|
prm_write_mod_reg(OMAP3430_EN_GPIO2 | OMAP3430_EN_GPIO3 |
|
|
|
|
OMAP3430_EN_GPIO4 | OMAP3430_EN_GPIO5 |
|
2009-10-23 05:48:13 +08:00
|
|
|
OMAP3430_EN_GPIO6 | OMAP3430_EN_UART3,
|
|
|
|
OMAP3430_PER_MOD, PM_WKEN);
|
OMAP3: PM: Enable GPIO module-level wakeups
Currently, only GPIOs in the wakeup domain (GPIOs in bank 0) are
enabled as wakups. This patch also enables GPIOs in the PER
powerdomain (banks 2-6) to be used as possible wakeup sources.
In addition, this patch ensures that all GPIO wakeups can wakeup
the MPU using the PM_MPUGRPSEL_<pwrdm> registers.
NOTE: this doesn't enable the individual GPIOs as wakeups, this simply
enables the per-bank wakeups at the powerdomain level.
This problem was discovered by Mike Chan when preventing the CORE
powerdomain from going into retention/off. When CORE was allowed to
hit retention, GPIO wakeups via IO pad were working fine, but when
CORE remained on, GPIO module-level wakeups were not working properly.
To test, prevent CORE from going inactive/retention/off, thus
preventing the IO chain from being armed:
# echo 3 > /debug/pm_debug/core_pwrdm/suspend
This ensures that GPIO wakeups happen via module-level wakeups and
not via IO pad.
Tested on 3430SDP using the touchscreen GPIO (gpio 2, in WKUP)
Tested on Zoom2 using the QUART interrup GPIO (gpio 102, in PER)
Also, c.f. OMAP PM wiki for troubleshooting GPIO wakeup issues:
http://elinux.org/OMAP_Power_Management
Reported-by: Mike Chan <mikechan@google.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
2009-09-10 23:53:08 +08:00
|
|
|
/* and allow them to wake up MPU */
|
|
|
|
prm_write_mod_reg(OMAP3430_GRPSEL_GPIO2 | OMAP3430_EN_GPIO3 |
|
|
|
|
OMAP3430_GRPSEL_GPIO4 | OMAP3430_EN_GPIO5 |
|
2009-10-23 05:48:13 +08:00
|
|
|
OMAP3430_GRPSEL_GPIO6 | OMAP3430_EN_UART3,
|
OMAP3: PM: Enable GPIO module-level wakeups
Currently, only GPIOs in the wakeup domain (GPIOs in bank 0) are
enabled as wakups. This patch also enables GPIOs in the PER
powerdomain (banks 2-6) to be used as possible wakeup sources.
In addition, this patch ensures that all GPIO wakeups can wakeup
the MPU using the PM_MPUGRPSEL_<pwrdm> registers.
NOTE: this doesn't enable the individual GPIOs as wakeups, this simply
enables the per-bank wakeups at the powerdomain level.
This problem was discovered by Mike Chan when preventing the CORE
powerdomain from going into retention/off. When CORE was allowed to
hit retention, GPIO wakeups via IO pad were working fine, but when
CORE remained on, GPIO module-level wakeups were not working properly.
To test, prevent CORE from going inactive/retention/off, thus
preventing the IO chain from being armed:
# echo 3 > /debug/pm_debug/core_pwrdm/suspend
This ensures that GPIO wakeups happen via module-level wakeups and
not via IO pad.
Tested on 3430SDP using the touchscreen GPIO (gpio 2, in WKUP)
Tested on Zoom2 using the QUART interrup GPIO (gpio 102, in PER)
Also, c.f. OMAP PM wiki for troubleshooting GPIO wakeup issues:
http://elinux.org/OMAP_Power_Management
Reported-by: Mike Chan <mikechan@google.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
2009-09-10 23:53:08 +08:00
|
|
|
OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
|
|
|
|
|
2009-05-06 07:34:25 +08:00
|
|
|
/* Don't attach IVA interrupts */
|
|
|
|
prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
|
|
|
|
prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
|
|
|
|
prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
|
|
|
|
prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
|
|
|
|
|
2009-04-28 07:14:54 +08:00
|
|
|
/* Clear any pending 'reset' flags */
|
|
|
|
prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST);
|
|
|
|
prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST);
|
|
|
|
prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST);
|
|
|
|
prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST);
|
|
|
|
prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST);
|
|
|
|
prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST);
|
|
|
|
prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST);
|
|
|
|
|
2009-04-27 22:50:23 +08:00
|
|
|
/* Clear any pending PRCM interrupts */
|
|
|
|
prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
|
|
|
|
|
2009-05-06 07:34:25 +08:00
|
|
|
/* Don't attach IVA interrupts */
|
|
|
|
prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
|
|
|
|
prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
|
|
|
|
prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
|
|
|
|
prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
|
|
|
|
|
2009-04-28 07:14:54 +08:00
|
|
|
/* Clear any pending 'reset' flags */
|
|
|
|
prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST);
|
|
|
|
prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST);
|
|
|
|
prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST);
|
|
|
|
prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST);
|
|
|
|
prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST);
|
|
|
|
prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST);
|
|
|
|
prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST);
|
|
|
|
|
2009-04-27 22:50:23 +08:00
|
|
|
/* Clear any pending PRCM interrupts */
|
|
|
|
prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
|
|
|
|
|
2008-11-26 03:48:24 +08:00
|
|
|
omap3_iva_idle();
|
2009-04-29 06:27:44 +08:00
|
|
|
omap3_d2d_idle();
|
2009-05-29 01:56:16 +08:00
|
|
|
}
|
|
|
|
|
2008-11-26 18:26:24 +08:00
|
|
|
int omap3_pm_get_suspend_state(struct powerdomain *pwrdm)
|
|
|
|
{
|
|
|
|
struct power_state *pwrst;
|
|
|
|
|
|
|
|
list_for_each_entry(pwrst, &pwrst_list, node) {
|
|
|
|
if (pwrst->pwrdm == pwrdm)
|
|
|
|
return pwrst->next_state;
|
|
|
|
}
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state)
|
|
|
|
{
|
|
|
|
struct power_state *pwrst;
|
|
|
|
|
|
|
|
list_for_each_entry(pwrst, &pwrst_list, node) {
|
|
|
|
if (pwrst->pwrdm == pwrdm) {
|
|
|
|
pwrst->next_state = state;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2008-10-15 23:13:47 +08:00
|
|
|
static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
|
2009-05-29 01:56:16 +08:00
|
|
|
{
|
|
|
|
struct power_state *pwrst;
|
|
|
|
|
|
|
|
if (!pwrdm->pwrsts)
|
|
|
|
return 0;
|
|
|
|
|
2009-08-22 21:20:26 +08:00
|
|
|
pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
|
2009-05-29 01:56:16 +08:00
|
|
|
if (!pwrst)
|
|
|
|
return -ENOMEM;
|
|
|
|
pwrst->pwrdm = pwrdm;
|
|
|
|
pwrst->next_state = PWRDM_POWER_RET;
|
|
|
|
list_add(&pwrst->node, &pwrst_list);
|
|
|
|
|
|
|
|
if (pwrdm_has_hdwr_sar(pwrdm))
|
|
|
|
pwrdm_enable_hdwr_sar(pwrdm);
|
|
|
|
|
|
|
|
return set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Enable hw supervised mode for all clockdomains if it's
|
|
|
|
* supported. Initiate sleep transition for other clockdomains, if
|
|
|
|
* they are not used
|
|
|
|
*/
|
2008-10-15 23:13:47 +08:00
|
|
|
static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
|
2009-05-29 01:56:16 +08:00
|
|
|
{
|
|
|
|
if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
|
|
|
|
omap2_clkdm_allow_idle(clkdm);
|
|
|
|
else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
|
|
|
|
atomic_read(&clkdm->usecount) == 0)
|
|
|
|
omap2_clkdm_sleep(clkdm);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2008-09-26 20:19:14 +08:00
|
|
|
void omap_push_sram_idle(void)
|
|
|
|
{
|
|
|
|
_omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend,
|
|
|
|
omap34xx_cpu_suspend_sz);
|
|
|
|
}
|
|
|
|
|
2009-06-11 00:02:25 +08:00
|
|
|
static int __init omap3_pm_init(void)
|
2009-05-29 01:56:16 +08:00
|
|
|
{
|
|
|
|
struct power_state *pwrst, *tmp;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
if (!cpu_is_omap34xx())
|
|
|
|
return -ENODEV;
|
|
|
|
|
|
|
|
printk(KERN_ERR "Power Management for TI OMAP3.\n");
|
|
|
|
|
|
|
|
/* XXX prcm_setup_regs needs to be before enabling hw
|
|
|
|
* supervised mode for powerdomains */
|
|
|
|
prcm_setup_regs();
|
2008-09-26 20:20:07 +08:00
|
|
|
omap3_save_scratchpad_contents();
|
2009-05-29 01:56:16 +08:00
|
|
|
|
|
|
|
ret = request_irq(INT_34XX_PRCM_MPU_IRQ,
|
|
|
|
(irq_handler_t)prcm_interrupt_handler,
|
|
|
|
IRQF_DISABLED, "prcm", NULL);
|
|
|
|
if (ret) {
|
|
|
|
printk(KERN_ERR "request_irq failed to register for 0x%x\n",
|
|
|
|
INT_34XX_PRCM_MPU_IRQ);
|
|
|
|
goto err1;
|
|
|
|
}
|
|
|
|
|
2008-10-15 23:13:47 +08:00
|
|
|
ret = pwrdm_for_each(pwrdms_setup, NULL);
|
2009-05-29 01:56:16 +08:00
|
|
|
if (ret) {
|
|
|
|
printk(KERN_ERR "Failed to setup powerdomains\n");
|
|
|
|
goto err2;
|
|
|
|
}
|
|
|
|
|
2008-10-15 23:13:47 +08:00
|
|
|
(void) clkdm_for_each(clkdms_setup, NULL);
|
2009-05-29 01:56:16 +08:00
|
|
|
|
|
|
|
mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
|
|
|
|
if (mpu_pwrdm == NULL) {
|
|
|
|
printk(KERN_ERR "Failed to get mpu_pwrdm\n");
|
|
|
|
goto err2;
|
|
|
|
}
|
|
|
|
|
2008-09-26 20:19:22 +08:00
|
|
|
neon_pwrdm = pwrdm_lookup("neon_pwrdm");
|
|
|
|
per_pwrdm = pwrdm_lookup("per_pwrdm");
|
|
|
|
core_pwrdm = pwrdm_lookup("core_pwrdm");
|
|
|
|
|
2008-09-26 20:19:14 +08:00
|
|
|
omap_push_sram_idle();
|
2009-06-25 02:39:18 +08:00
|
|
|
#ifdef CONFIG_SUSPEND
|
2009-05-29 01:56:16 +08:00
|
|
|
suspend_set_ops(&omap_pm_ops);
|
2009-06-25 02:39:18 +08:00
|
|
|
#endif /* CONFIG_SUSPEND */
|
2009-05-29 01:56:16 +08:00
|
|
|
|
|
|
|
pm_idle = omap3_pm_idle;
|
|
|
|
|
2008-09-26 20:19:22 +08:00
|
|
|
pwrdm_add_wkdep(neon_pwrdm, mpu_pwrdm);
|
|
|
|
/*
|
|
|
|
* REVISIT: This wkdep is only necessary when GPIO2-6 are enabled for
|
|
|
|
* IO-pad wakeup. Otherwise it will unnecessarily waste power
|
|
|
|
* waking up PER with every CORE wakeup - see
|
|
|
|
* http://marc.info/?l=linux-omap&m=121852150710062&w=2
|
|
|
|
*/
|
|
|
|
pwrdm_add_wkdep(per_pwrdm, core_pwrdm);
|
|
|
|
|
2009-05-29 01:56:16 +08:00
|
|
|
err1:
|
|
|
|
return ret;
|
|
|
|
err2:
|
|
|
|
free_irq(INT_34XX_PRCM_MPU_IRQ, NULL);
|
|
|
|
list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
|
|
|
|
list_del(&pwrst->node);
|
|
|
|
kfree(pwrst);
|
|
|
|
}
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
late_initcall(omap3_pm_init);
|