p71924506
/
linux_old1
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity
linux_old1/arch/arm/mach-omap2/omap-headsmp.S

50 lines
1.3 KiB
ArmAsm
Raw Normal View History

ARM: OMAP4: SMP: Add OMAP4430 SMP board files This patch adds SMP platform files support for OMAP4430SDP. TI's OMAP4430 SOC is based on ARM Cortex-A9 SMP architecture. It's a dual core SOC with GIC used for interrupt handling and SCU for cache coherency. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
2009-04-28 23:21:52 +08:00
/*
* Secondary CPU startup routine source file.
*
* Copyright (C) 2009 Texas Instruments, Inc.
*
* Author:
* Santosh Shilimkar <santosh.shilimkar@ti.com>
*
* Interface functions needed for the SMP. This file is based on arm
* realview smp platform.
* Copyright (c) 2003 ARM Limited.
*
* This program is free software,you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/linkage.h>
#include <linux/init.h>
/* Physical address needed since MMU not enabled yet on secondary core */
#define OMAP4_AUX_CORE_BOOT1_PA 0x48281804
__INIT
/*
* OMAP4 specific entry point for secondary CPU to jump from ROM
* code. This routine also provides a holding flag into which
* secondary core is held until we're ready for it to initialise.
OMAP4: AuxCoreBoot registers only accessible in secure mode The AuxCoreBoot0 and AuxCoreBoot1 can be only accessed in secure mode. Replace the current code with secure monitor API's to access/modify these registers. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2009-12-12 08:16:35 +08:00
* The primary core will update this flag using a hardware
* register AuxCoreBoot0.
ARM: OMAP4: SMP: Add OMAP4430 SMP board files This patch adds SMP platform files support for OMAP4430SDP. TI's OMAP4430 SOC is based on ARM Cortex-A9 SMP architecture. It's a dual core SOC with GIC used for interrupt handling and SCU for cache coherency. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
2009-04-28 23:21:52 +08:00
*/
ENTRY(omap_secondary_startup)
OMAP4: AuxCoreBoot registers only accessible in secure mode The AuxCoreBoot0 and AuxCoreBoot1 can be only accessed in secure mode. Replace the current code with secure monitor API's to access/modify these registers. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2009-12-12 08:16:35 +08:00
hold: ldr r12,=0x103
dsb
omap4: Fix build break when used with gcc-4.4.1 (2009-q3) This patch adds argument to smc calls as gcc-4.4.1 requires it otherwise the build breaks with 2009-q3 toolchanin. arch/arm/mach-omap2/omap-headsmp.S: Assembler messages: arch/arm/mach-omap2/omap-headsmp.S:36: Error: missing expression -- `smc' arch/arm/mach-omap2/omap-headsmp.S:55: Error: missing expression -- `smc' arch/arm/mach-omap2/omap-headsmp.S:63: Error: missing expression -- `smc' make[1]: *** [arch/arm/mach-omap2/omap-headsmp.o] Error 1 Signed-off-by: Richard Woodruff <r-woodruff2@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2010-04-07 15:47:21 +08:00
smc #0 @ read from AuxCoreBoot0
OMAP4: AuxCoreBoot registers only accessible in secure mode The AuxCoreBoot0 and AuxCoreBoot1 can be only accessed in secure mode. Replace the current code with secure monitor API's to access/modify these registers. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2009-12-12 08:16:35 +08:00
mov r0, r0, lsr #9
mrc p15, 0, r4, c0, c0, 5
and r4, r4, #0x0f
cmp r0, r4
ARM: OMAP4: SMP: Add OMAP4430 SMP board files This patch adds SMP platform files support for OMAP4430SDP. TI's OMAP4430 SOC is based on ARM Cortex-A9 SMP architecture. It's a dual core SOC with GIC used for interrupt handling and SCU for cache coherency. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
2009-04-28 23:21:52 +08:00
bne hold
/*
OMAP4: AuxCoreBoot registers only accessible in secure mode The AuxCoreBoot0 and AuxCoreBoot1 can be only accessed in secure mode. Replace the current code with secure monitor API's to access/modify these registers. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2009-12-12 08:16:35 +08:00
* we've been released from the wait loop,secondary_stack
ARM: OMAP4: SMP: Add OMAP4430 SMP board files This patch adds SMP platform files support for OMAP4430SDP. TI's OMAP4430 SOC is based on ARM Cortex-A9 SMP architecture. It's a dual core SOC with GIC used for interrupt handling and SCU for cache coherency. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
2009-04-28 23:21:52 +08:00
* should now contain the SVC stack for this core
*/
b secondary_startup
ARM: omap4: Convert END() to ENDPROC() for correct linkage with CONFIG_THUMB2_KERNEL Code marked with ENTRY() also needs a matching ENDPROC() directive, in order to ensure that the type and instruction set of the symbol are correctly annotated. ENDPROC() tags the affected symbol as a function symbol, which will ensure that link-time fixups don't accidentally switch to the wrong instruction set. Signed-off-by: Dave Martin <dave.martin@linaro.org> Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
2011-03-04 23:33:54 +08:00
ENDPROC(omap_secondary_startup)
ARM: OMAP4: SMP: Add OMAP4430 SMP board files This patch adds SMP platform files support for OMAP4430SDP. TI's OMAP4430 SOC is based on ARM Cortex-A9 SMP architecture. It's a dual core SOC with GIC used for interrupt handling and SCU for cache coherency. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
2009-04-28 23:21:52 +08:00