2013-10-18 01:21:36 +08:00
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#ifndef __LINUX_GPIO_DRIVER_H
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#define __LINUX_GPIO_DRIVER_H
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2015-10-20 17:10:38 +08:00
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#include <linux/device.h>
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2013-10-18 01:21:36 +08:00
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#include <linux/types.h>
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2013-11-25 17:34:24 +08:00
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#include <linux/module.h>
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2014-03-25 17:40:18 +08:00
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#include <linux/irq.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/irqdomain.h>
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gpiolib: irqchip: use different lockdep class for each gpio irqchip
Since IRQ chip helpers were introduced drivers lose ability to
register separate lockdep classes for each registered GPIO IRQ
chip and the gpiolib now is using shared lockdep class for
all GPIO IRQ chips (gpiochip_irq_lock_class).
As result, lockdep will produce warning when there are min two
stacked GPIO chips and all of them are interrupt controllers.
HW configuration which generates lockdep warning (TI dra7-evm):
[SOC GPIO bankA.gpioX]
<- irq - [pcf875x.gpioY]
<- irq - DevZ.enable_irq_wake(pcf_gpioY_irq);
The issue was reported in [1] and discussed [2].
=============================================
[ INFO: possible recursive locking detected ]
4.2.0-rc6-00013-g5d050ed-dirty #55 Not tainted
---------------------------------------------
sh/63 is trying to acquire lock:
(class){......}, at: [<c009b91c>] __irq_get_desc_lock+0x50/0x94
but task is already holding lock:
(class){......}, at: [<c009b91c>] __irq_get_desc_lock+0x50/0x94
other info that might help us debug this:
Possible unsafe locking scenario:
CPU0
----
lock(class);
lock(class);
*** DEADLOCK ***
May be due to missing lock nesting notation
7 locks held by sh/63:
#0: (sb_writers#4){.+.+.+}, at: [<c016bbb8>] vfs_write+0x13c/0x164
#1: (&of->mutex){+.+.+.}, at: [<c01debf4>] kernfs_fop_write+0x4c/0x1a0
#2: (s_active#36){.+.+.+}, at: [<c01debfc>] kernfs_fop_write+0x54/0x1a0
#3: (pm_mutex){+.+.+.}, at: [<c009758c>] pm_suspend+0xec/0x4c4
#4: (&dev->mutex){......}, at: [<c03f77f8>] __device_suspend+0xd4/0x398
#5: (&gpio->lock){+.+.+.}, at: [<c009b940>] __irq_get_desc_lock+0x74/0x94
#6: (class){......}, at: [<c009b91c>] __irq_get_desc_lock+0x50/0x94
stack backtrace:
CPU: 0 PID: 63 Comm: sh Not tainted 4.2.0-rc6-00013-g5d050ed-dirty #55
Hardware name: Generic DRA74X (Flattened Device Tree)
[<c0016e24>] (unwind_backtrace) from [<c0013338>] (show_stack+0x10/0x14)
[<c0013338>] (show_stack) from [<c05f6b24>] (dump_stack+0x84/0x9c)
[<c05f6b24>] (dump_stack) from [<c00903f4>] (__lock_acquire+0x19c0/0x1e20)
[<c00903f4>] (__lock_acquire) from [<c0091098>] (lock_acquire+0xa8/0x128)
[<c0091098>] (lock_acquire) from [<c05fd61c>] (_raw_spin_lock_irqsave+0x38/0x4c)
[<c05fd61c>] (_raw_spin_lock_irqsave) from [<c009b91c>] (__irq_get_desc_lock+0x50/0x94)
[<c009b91c>] (__irq_get_desc_lock) from [<c009c4f4>] (irq_set_irq_wake+0x20/0xfc)
[<c009c4f4>] (irq_set_irq_wake) from [<c0393ac4>] (pcf857x_irq_set_wake+0x24/0x54)
[<c0393ac4>] (pcf857x_irq_set_wake) from [<c009c560>] (irq_set_irq_wake+0x8c/0xfc)
[<c009c560>] (irq_set_irq_wake) from [<c04a02ac>] (gpio_keys_suspend+0x70/0xd4)
[<c04a02ac>] (gpio_keys_suspend) from [<c03f6a00>] (dpm_run_callback+0x50/0x124)
[<c03f6a00>] (dpm_run_callback) from [<c03f7830>] (__device_suspend+0x10c/0x398)
[<c03f7830>] (__device_suspend) from [<c03f90f0>] (dpm_suspend+0x134/0x2f4)
[<c03f90f0>] (dpm_suspend) from [<c0096e20>] (suspend_devices_and_enter+0xa8/0x728)
[<c0096e20>] (suspend_devices_and_enter) from [<c00977cc>] (pm_suspend+0x32c/0x4c4)
[<c00977cc>] (pm_suspend) from [<c0096060>] (state_store+0x64/0xb8)
[<c0096060>] (state_store) from [<c01dec64>] (kernfs_fop_write+0xbc/0x1a0)
[<c01dec64>] (kernfs_fop_write) from [<c016b280>] (__vfs_write+0x20/0xd8)
[<c016b280>] (__vfs_write) from [<c016bb0c>] (vfs_write+0x90/0x164)
[<c016bb0c>] (vfs_write) from [<c016c330>] (SyS_write+0x44/0x9c)
[<c016c330>] (SyS_write) from [<c000f500>] (ret_fast_syscall+0x0/0x54)
Lets fix it by using separate lockdep class for each registered GPIO
IRQ Chip. This is done by wrapping gpiochip_irqchip_add call into macros.
The implementation of this patch inspired by solution done by Nicolas
Boichat for regmap [3]
[1] http://www.spinics.net/lists/linux-gpio/msg05844.html
[2] http://www.spinics.net/lists/linux-gpio/msg06021.html
[3] http://www.spinics.net/lists/arm-kernel/msg429834.html
Cc: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: Roger Quadros <rogerq@ti.com>
Reported-by: Roger Quadros <rogerq@ti.com>
Tested-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-08-17 20:35:23 +08:00
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#include <linux/lockdep.h>
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2015-03-18 08:56:17 +08:00
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#include <linux/pinctrl/pinctrl.h>
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2015-12-04 21:02:58 +08:00
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#include <linux/kconfig.h>
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2013-10-18 01:21:36 +08:00
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struct gpio_desc;
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2013-11-25 17:34:24 +08:00
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struct of_phandle_args;
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struct device_node;
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2013-10-28 22:06:23 +08:00
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struct seq_file;
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2015-10-20 17:10:38 +08:00
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struct gpio_device;
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2013-10-18 01:21:36 +08:00
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2014-02-09 16:43:54 +08:00
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#ifdef CONFIG_GPIOLIB
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2013-10-18 01:21:36 +08:00
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/**
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* struct gpio_chip - abstract a GPIO controller
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2016-02-12 21:48:23 +08:00
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* @label: a functional name for the GPIO device, such as a part
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* number or the name of the SoC IP-block implementing it.
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2015-10-20 17:10:38 +08:00
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* @gpiodev: the internal state holder, opaque struct
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2015-11-04 16:56:26 +08:00
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* @parent: optional parent device providing the GPIOs
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2013-10-18 01:21:36 +08:00
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* @owner: helps prevent removal of modules exporting active GPIOs
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* @request: optional hook for chip-specific activation, such as
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* enabling module power and clock; may sleep
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* @free: optional hook for chip-specific deactivation, such as
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* disabling module power and clock; may sleep
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* @get_direction: returns direction for signal "offset", 0=out, 1=in,
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* (same as GPIOF_DIR_XXX), or negative error
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* @direction_input: configures signal "offset" as input, or returns error
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* @direction_output: configures signal "offset" as output, or returns error
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2015-12-22 22:37:28 +08:00
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* @get: returns value for signal "offset", 0=low, 1=high, or negative error
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2013-10-18 01:21:36 +08:00
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* @set: assigns output value for signal "offset"
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2014-11-05 00:12:06 +08:00
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* @set_multiple: assigns output values for multiple signals defined by "mask"
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2013-10-18 01:21:36 +08:00
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* @set_debounce: optional hook for setting debounce time for specified gpio in
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* interrupt triggered gpio chips
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* @to_irq: optional hook supporting non-static gpio_to_irq() mappings;
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* implementation may not sleep
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* @dbg_show: optional routine to show contents in debugfs; default code
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* will be used when this is omitted, but custom code can show extra
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* state (such as pullup/pulldown configuration).
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2015-05-13 19:03:21 +08:00
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* @base: identifies the first GPIO number handled by this chip;
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* or, if negative during registration, requests dynamic ID allocation.
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* DEPRECATION: providing anything non-negative and nailing the base
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2015-06-15 19:31:33 +08:00
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* offset of GPIO chips is deprecated. Please pass -1 as base to
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2015-05-13 19:03:21 +08:00
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* let gpiolib select the chip base in all possible cases. We want to
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* get rid of the static GPIO number space in the long run.
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2013-10-18 01:21:36 +08:00
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* @ngpio: the number of GPIOs handled by this controller; the last GPIO
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* handled is (base + ngpio - 1).
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* @names: if set, must be an array of strings to use as alternative
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* names for the GPIOs in this chip. Any entry in the array
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* may be NULL if there is no alias for the GPIO, however the
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* array must be @ngpio entries long. A name can include a single printk
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* format specifier for an unsigned int. It is substituted by the actual
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* number of the gpio.
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2013-12-04 21:42:46 +08:00
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* @can_sleep: flag must be set iff get()/set() methods sleep, as they
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2014-04-09 19:34:39 +08:00
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* must while accessing GPIO expander chips over I2C or SPI. This
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* implies that if the chip supports IRQs, these IRQs need to be threaded
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* as the chip access may sleep when e.g. reading out the IRQ status
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* registers.
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2014-09-20 04:22:44 +08:00
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* @irq_not_threaded: flag must be set if @can_sleep is set but the
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* IRQs don't need to be threaded
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2015-12-04 21:02:58 +08:00
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* @read_reg: reader function for generic GPIO
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* @write_reg: writer function for generic GPIO
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* @pin2mask: some generic GPIO controllers work with the big-endian bits
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* notation, e.g. in a 8-bits register, GPIO7 is the least significant
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* bit. This callback assigns the right bit mask.
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* @reg_dat: data (in) register for generic GPIO
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* @reg_set: output set register (out=high) for generic GPIO
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* @reg_clk: output clear register (out=low) for generic GPIO
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* @reg_dir: direction setting register for generic GPIO
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* @bgpio_bits: number of register bits used for a generic GPIO i.e.
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* <register width> * 8
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* @bgpio_lock: used to lock chip->bgpio_data. Also, this is needed to keep
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* shadowed and real data registers writes together.
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* @bgpio_data: shadowed data register for generic GPIO to clear/set bits
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* safely.
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* @bgpio_dir: shadowed direction register for generic GPIO to clear/set
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* direction safely.
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2015-08-17 20:35:24 +08:00
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* @irqchip: GPIO IRQ chip impl, provided by GPIO driver
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* @irqdomain: Interrupt translation domain; responsible for mapping
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* between GPIO hwirq number and linux irq number
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* @irq_base: first linux IRQ number assigned to GPIO IRQ chip (deprecated)
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* @irq_handler: the irq handler to use (often a predefined irq core function)
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* for GPIO IRQs, provided by GPIO driver
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* @irq_default_type: default IRQ triggering type applied during GPIO driver
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* initialization, provided by GPIO driver
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* @irq_parent: GPIO IRQ chip parent/bank linux irq number,
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* provided by GPIO driver
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* @lock_key: per GPIO IRQ chip lockdep class
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2013-10-18 01:21:36 +08:00
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*
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* A gpio_chip can help platforms abstract various sources of GPIOs so
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* they can all be accessed through a common programing interface.
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* Example sources would be SOC controllers, FPGAs, multifunction
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* chips, dedicated GPIO expanders, and so on.
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*
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* Each chip controls a number of signals, identified in method calls
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* by "offset" values in the range 0..(@ngpio - 1). When those signals
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* are referenced through calls like gpio_get_value(gpio), the offset
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* is calculated by subtracting @base from the gpio number.
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*/
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struct gpio_chip {
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const char *label;
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2015-10-20 17:10:38 +08:00
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struct gpio_device *gpiodev;
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2015-11-04 16:56:26 +08:00
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struct device *parent;
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2013-10-18 01:21:36 +08:00
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struct module *owner;
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int (*request)(struct gpio_chip *chip,
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unsigned offset);
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void (*free)(struct gpio_chip *chip,
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unsigned offset);
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int (*get_direction)(struct gpio_chip *chip,
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unsigned offset);
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int (*direction_input)(struct gpio_chip *chip,
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unsigned offset);
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int (*direction_output)(struct gpio_chip *chip,
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unsigned offset, int value);
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int (*get)(struct gpio_chip *chip,
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unsigned offset);
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void (*set)(struct gpio_chip *chip,
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unsigned offset, int value);
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2014-11-05 00:12:06 +08:00
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void (*set_multiple)(struct gpio_chip *chip,
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unsigned long *mask,
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unsigned long *bits);
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2013-10-18 01:21:36 +08:00
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int (*set_debounce)(struct gpio_chip *chip,
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unsigned offset,
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unsigned debounce);
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int (*to_irq)(struct gpio_chip *chip,
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unsigned offset);
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void (*dbg_show)(struct seq_file *s,
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struct gpio_chip *chip);
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int base;
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u16 ngpio;
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const char *const *names;
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2013-12-04 21:42:46 +08:00
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bool can_sleep;
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2014-09-20 04:22:44 +08:00
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bool irq_not_threaded;
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2013-10-18 01:21:36 +08:00
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2015-12-04 21:02:58 +08:00
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#if IS_ENABLED(CONFIG_GPIO_GENERIC)
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unsigned long (*read_reg)(void __iomem *reg);
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void (*write_reg)(void __iomem *reg, unsigned long data);
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unsigned long (*pin2mask)(struct gpio_chip *gc, unsigned int pin);
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void __iomem *reg_dat;
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void __iomem *reg_set;
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void __iomem *reg_clr;
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void __iomem *reg_dir;
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int bgpio_bits;
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spinlock_t bgpio_lock;
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unsigned long bgpio_data;
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unsigned long bgpio_dir;
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#endif
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2014-03-25 17:40:18 +08:00
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#ifdef CONFIG_GPIOLIB_IRQCHIP
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/*
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2014-09-05 19:09:25 +08:00
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* With CONFIG_GPIOLIB_IRQCHIP we get an irqchip inside the gpiolib
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2014-03-25 17:40:18 +08:00
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* to handle IRQs for most practical cases.
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*/
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struct irq_chip *irqchip;
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struct irq_domain *irqdomain;
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2014-03-29 03:42:01 +08:00
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unsigned int irq_base;
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2014-03-25 17:40:18 +08:00
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irq_flow_handler_t irq_handler;
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unsigned int irq_default_type;
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2015-05-13 01:12:23 +08:00
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int irq_parent;
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gpiolib: irqchip: use different lockdep class for each gpio irqchip
Since IRQ chip helpers were introduced drivers lose ability to
register separate lockdep classes for each registered GPIO IRQ
chip and the gpiolib now is using shared lockdep class for
all GPIO IRQ chips (gpiochip_irq_lock_class).
As result, lockdep will produce warning when there are min two
stacked GPIO chips and all of them are interrupt controllers.
HW configuration which generates lockdep warning (TI dra7-evm):
[SOC GPIO bankA.gpioX]
<- irq - [pcf875x.gpioY]
<- irq - DevZ.enable_irq_wake(pcf_gpioY_irq);
The issue was reported in [1] and discussed [2].
=============================================
[ INFO: possible recursive locking detected ]
4.2.0-rc6-00013-g5d050ed-dirty #55 Not tainted
---------------------------------------------
sh/63 is trying to acquire lock:
(class){......}, at: [<c009b91c>] __irq_get_desc_lock+0x50/0x94
but task is already holding lock:
(class){......}, at: [<c009b91c>] __irq_get_desc_lock+0x50/0x94
other info that might help us debug this:
Possible unsafe locking scenario:
CPU0
----
lock(class);
lock(class);
*** DEADLOCK ***
May be due to missing lock nesting notation
7 locks held by sh/63:
#0: (sb_writers#4){.+.+.+}, at: [<c016bbb8>] vfs_write+0x13c/0x164
#1: (&of->mutex){+.+.+.}, at: [<c01debf4>] kernfs_fop_write+0x4c/0x1a0
#2: (s_active#36){.+.+.+}, at: [<c01debfc>] kernfs_fop_write+0x54/0x1a0
#3: (pm_mutex){+.+.+.}, at: [<c009758c>] pm_suspend+0xec/0x4c4
#4: (&dev->mutex){......}, at: [<c03f77f8>] __device_suspend+0xd4/0x398
#5: (&gpio->lock){+.+.+.}, at: [<c009b940>] __irq_get_desc_lock+0x74/0x94
#6: (class){......}, at: [<c009b91c>] __irq_get_desc_lock+0x50/0x94
stack backtrace:
CPU: 0 PID: 63 Comm: sh Not tainted 4.2.0-rc6-00013-g5d050ed-dirty #55
Hardware name: Generic DRA74X (Flattened Device Tree)
[<c0016e24>] (unwind_backtrace) from [<c0013338>] (show_stack+0x10/0x14)
[<c0013338>] (show_stack) from [<c05f6b24>] (dump_stack+0x84/0x9c)
[<c05f6b24>] (dump_stack) from [<c00903f4>] (__lock_acquire+0x19c0/0x1e20)
[<c00903f4>] (__lock_acquire) from [<c0091098>] (lock_acquire+0xa8/0x128)
[<c0091098>] (lock_acquire) from [<c05fd61c>] (_raw_spin_lock_irqsave+0x38/0x4c)
[<c05fd61c>] (_raw_spin_lock_irqsave) from [<c009b91c>] (__irq_get_desc_lock+0x50/0x94)
[<c009b91c>] (__irq_get_desc_lock) from [<c009c4f4>] (irq_set_irq_wake+0x20/0xfc)
[<c009c4f4>] (irq_set_irq_wake) from [<c0393ac4>] (pcf857x_irq_set_wake+0x24/0x54)
[<c0393ac4>] (pcf857x_irq_set_wake) from [<c009c560>] (irq_set_irq_wake+0x8c/0xfc)
[<c009c560>] (irq_set_irq_wake) from [<c04a02ac>] (gpio_keys_suspend+0x70/0xd4)
[<c04a02ac>] (gpio_keys_suspend) from [<c03f6a00>] (dpm_run_callback+0x50/0x124)
[<c03f6a00>] (dpm_run_callback) from [<c03f7830>] (__device_suspend+0x10c/0x398)
[<c03f7830>] (__device_suspend) from [<c03f90f0>] (dpm_suspend+0x134/0x2f4)
[<c03f90f0>] (dpm_suspend) from [<c0096e20>] (suspend_devices_and_enter+0xa8/0x728)
[<c0096e20>] (suspend_devices_and_enter) from [<c00977cc>] (pm_suspend+0x32c/0x4c4)
[<c00977cc>] (pm_suspend) from [<c0096060>] (state_store+0x64/0xb8)
[<c0096060>] (state_store) from [<c01dec64>] (kernfs_fop_write+0xbc/0x1a0)
[<c01dec64>] (kernfs_fop_write) from [<c016b280>] (__vfs_write+0x20/0xd8)
[<c016b280>] (__vfs_write) from [<c016bb0c>] (vfs_write+0x90/0x164)
[<c016bb0c>] (vfs_write) from [<c016c330>] (SyS_write+0x44/0x9c)
[<c016c330>] (SyS_write) from [<c000f500>] (ret_fast_syscall+0x0/0x54)
Lets fix it by using separate lockdep class for each registered GPIO
IRQ Chip. This is done by wrapping gpiochip_irqchip_add call into macros.
The implementation of this patch inspired by solution done by Nicolas
Boichat for regmap [3]
[1] http://www.spinics.net/lists/linux-gpio/msg05844.html
[2] http://www.spinics.net/lists/linux-gpio/msg06021.html
[3] http://www.spinics.net/lists/arm-kernel/msg429834.html
Cc: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: Roger Quadros <rogerq@ti.com>
Reported-by: Roger Quadros <rogerq@ti.com>
Tested-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-08-17 20:35:23 +08:00
|
|
|
struct lock_class_key *lock_key;
|
2014-03-25 17:40:18 +08:00
|
|
|
#endif
|
|
|
|
|
2013-10-18 01:21:36 +08:00
|
|
|
#if defined(CONFIG_OF_GPIO)
|
|
|
|
/*
|
|
|
|
* If CONFIG_OF is enabled, then all GPIO controllers described in the
|
|
|
|
* device tree automatically may have an OF translation
|
|
|
|
*/
|
|
|
|
struct device_node *of_node;
|
|
|
|
int of_gpio_n_cells;
|
|
|
|
int (*of_xlate)(struct gpio_chip *gc,
|
|
|
|
const struct of_phandle_args *gpiospec, u32 *flags);
|
|
|
|
#endif
|
|
|
|
};
|
|
|
|
|
|
|
|
extern const char *gpiochip_is_requested(struct gpio_chip *chip,
|
|
|
|
unsigned offset);
|
|
|
|
|
|
|
|
/* add/remove chips */
|
2015-12-03 22:14:13 +08:00
|
|
|
extern int gpiochip_add_data(struct gpio_chip *chip, void *data);
|
|
|
|
static inline int gpiochip_add(struct gpio_chip *chip)
|
|
|
|
{
|
|
|
|
return gpiochip_add_data(chip, NULL);
|
|
|
|
}
|
2014-07-06 00:28:50 +08:00
|
|
|
extern void gpiochip_remove(struct gpio_chip *chip);
|
2016-02-15 19:02:09 +08:00
|
|
|
extern int devm_gpiochip_add_data(struct device *dev, struct gpio_chip *chip,
|
|
|
|
void *data);
|
|
|
|
extern void devm_gpiochip_remove(struct device *dev, struct gpio_chip *chip);
|
|
|
|
|
2013-10-18 01:21:36 +08:00
|
|
|
extern struct gpio_chip *gpiochip_find(void *data,
|
|
|
|
int (*match)(struct gpio_chip *chip, void *data));
|
|
|
|
|
|
|
|
/* lock/unlock as IRQ */
|
2014-10-23 16:27:07 +08:00
|
|
|
int gpiochip_lock_as_irq(struct gpio_chip *chip, unsigned int offset);
|
|
|
|
void gpiochip_unlock_as_irq(struct gpio_chip *chip, unsigned int offset);
|
2016-02-12 03:16:45 +08:00
|
|
|
bool gpiochip_line_is_irq(struct gpio_chip *chip, unsigned int offset);
|
2013-10-18 01:21:36 +08:00
|
|
|
|
2016-02-16 22:41:42 +08:00
|
|
|
/* Line status inquiry for drivers */
|
|
|
|
bool gpiochip_line_is_open_drain(struct gpio_chip *chip, unsigned int offset);
|
|
|
|
bool gpiochip_line_is_open_source(struct gpio_chip *chip, unsigned int offset);
|
|
|
|
|
2015-12-03 22:14:13 +08:00
|
|
|
/* get driver data */
|
2016-02-11 18:37:48 +08:00
|
|
|
void *gpiochip_get_data(struct gpio_chip *chip);
|
2015-12-03 22:14:13 +08:00
|
|
|
|
2014-02-09 16:43:54 +08:00
|
|
|
struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc);
|
|
|
|
|
2015-12-04 21:02:58 +08:00
|
|
|
struct bgpio_pdata {
|
|
|
|
const char *label;
|
|
|
|
int base;
|
|
|
|
int ngpio;
|
|
|
|
};
|
|
|
|
|
2016-01-10 05:16:42 +08:00
|
|
|
#if IS_ENABLED(CONFIG_GPIO_GENERIC)
|
|
|
|
|
2015-12-04 21:02:58 +08:00
|
|
|
int bgpio_init(struct gpio_chip *gc, struct device *dev,
|
|
|
|
unsigned long sz, void __iomem *dat, void __iomem *set,
|
|
|
|
void __iomem *clr, void __iomem *dirout, void __iomem *dirin,
|
|
|
|
unsigned long flags);
|
|
|
|
|
|
|
|
#define BGPIOF_BIG_ENDIAN BIT(0)
|
|
|
|
#define BGPIOF_UNREADABLE_REG_SET BIT(1) /* reg_set is unreadable */
|
|
|
|
#define BGPIOF_UNREADABLE_REG_DIR BIT(2) /* reg_dir is unreadable */
|
|
|
|
#define BGPIOF_BIG_ENDIAN_BYTE_ORDER BIT(3)
|
|
|
|
#define BGPIOF_READ_OUTPUT_REG_SET BIT(4) /* reg_set stores output value */
|
|
|
|
#define BGPIOF_NO_OUTPUT BIT(5) /* only input */
|
|
|
|
|
|
|
|
#endif
|
|
|
|
|
2014-03-25 17:40:18 +08:00
|
|
|
#ifdef CONFIG_GPIOLIB_IRQCHIP
|
|
|
|
|
|
|
|
void gpiochip_set_chained_irqchip(struct gpio_chip *gpiochip,
|
|
|
|
struct irq_chip *irqchip,
|
|
|
|
int parent_irq,
|
|
|
|
irq_flow_handler_t parent_handler);
|
|
|
|
|
gpiolib: irqchip: use different lockdep class for each gpio irqchip
Since IRQ chip helpers were introduced drivers lose ability to
register separate lockdep classes for each registered GPIO IRQ
chip and the gpiolib now is using shared lockdep class for
all GPIO IRQ chips (gpiochip_irq_lock_class).
As result, lockdep will produce warning when there are min two
stacked GPIO chips and all of them are interrupt controllers.
HW configuration which generates lockdep warning (TI dra7-evm):
[SOC GPIO bankA.gpioX]
<- irq - [pcf875x.gpioY]
<- irq - DevZ.enable_irq_wake(pcf_gpioY_irq);
The issue was reported in [1] and discussed [2].
=============================================
[ INFO: possible recursive locking detected ]
4.2.0-rc6-00013-g5d050ed-dirty #55 Not tainted
---------------------------------------------
sh/63 is trying to acquire lock:
(class){......}, at: [<c009b91c>] __irq_get_desc_lock+0x50/0x94
but task is already holding lock:
(class){......}, at: [<c009b91c>] __irq_get_desc_lock+0x50/0x94
other info that might help us debug this:
Possible unsafe locking scenario:
CPU0
----
lock(class);
lock(class);
*** DEADLOCK ***
May be due to missing lock nesting notation
7 locks held by sh/63:
#0: (sb_writers#4){.+.+.+}, at: [<c016bbb8>] vfs_write+0x13c/0x164
#1: (&of->mutex){+.+.+.}, at: [<c01debf4>] kernfs_fop_write+0x4c/0x1a0
#2: (s_active#36){.+.+.+}, at: [<c01debfc>] kernfs_fop_write+0x54/0x1a0
#3: (pm_mutex){+.+.+.}, at: [<c009758c>] pm_suspend+0xec/0x4c4
#4: (&dev->mutex){......}, at: [<c03f77f8>] __device_suspend+0xd4/0x398
#5: (&gpio->lock){+.+.+.}, at: [<c009b940>] __irq_get_desc_lock+0x74/0x94
#6: (class){......}, at: [<c009b91c>] __irq_get_desc_lock+0x50/0x94
stack backtrace:
CPU: 0 PID: 63 Comm: sh Not tainted 4.2.0-rc6-00013-g5d050ed-dirty #55
Hardware name: Generic DRA74X (Flattened Device Tree)
[<c0016e24>] (unwind_backtrace) from [<c0013338>] (show_stack+0x10/0x14)
[<c0013338>] (show_stack) from [<c05f6b24>] (dump_stack+0x84/0x9c)
[<c05f6b24>] (dump_stack) from [<c00903f4>] (__lock_acquire+0x19c0/0x1e20)
[<c00903f4>] (__lock_acquire) from [<c0091098>] (lock_acquire+0xa8/0x128)
[<c0091098>] (lock_acquire) from [<c05fd61c>] (_raw_spin_lock_irqsave+0x38/0x4c)
[<c05fd61c>] (_raw_spin_lock_irqsave) from [<c009b91c>] (__irq_get_desc_lock+0x50/0x94)
[<c009b91c>] (__irq_get_desc_lock) from [<c009c4f4>] (irq_set_irq_wake+0x20/0xfc)
[<c009c4f4>] (irq_set_irq_wake) from [<c0393ac4>] (pcf857x_irq_set_wake+0x24/0x54)
[<c0393ac4>] (pcf857x_irq_set_wake) from [<c009c560>] (irq_set_irq_wake+0x8c/0xfc)
[<c009c560>] (irq_set_irq_wake) from [<c04a02ac>] (gpio_keys_suspend+0x70/0xd4)
[<c04a02ac>] (gpio_keys_suspend) from [<c03f6a00>] (dpm_run_callback+0x50/0x124)
[<c03f6a00>] (dpm_run_callback) from [<c03f7830>] (__device_suspend+0x10c/0x398)
[<c03f7830>] (__device_suspend) from [<c03f90f0>] (dpm_suspend+0x134/0x2f4)
[<c03f90f0>] (dpm_suspend) from [<c0096e20>] (suspend_devices_and_enter+0xa8/0x728)
[<c0096e20>] (suspend_devices_and_enter) from [<c00977cc>] (pm_suspend+0x32c/0x4c4)
[<c00977cc>] (pm_suspend) from [<c0096060>] (state_store+0x64/0xb8)
[<c0096060>] (state_store) from [<c01dec64>] (kernfs_fop_write+0xbc/0x1a0)
[<c01dec64>] (kernfs_fop_write) from [<c016b280>] (__vfs_write+0x20/0xd8)
[<c016b280>] (__vfs_write) from [<c016bb0c>] (vfs_write+0x90/0x164)
[<c016bb0c>] (vfs_write) from [<c016c330>] (SyS_write+0x44/0x9c)
[<c016c330>] (SyS_write) from [<c000f500>] (ret_fast_syscall+0x0/0x54)
Lets fix it by using separate lockdep class for each registered GPIO
IRQ Chip. This is done by wrapping gpiochip_irqchip_add call into macros.
The implementation of this patch inspired by solution done by Nicolas
Boichat for regmap [3]
[1] http://www.spinics.net/lists/linux-gpio/msg05844.html
[2] http://www.spinics.net/lists/linux-gpio/msg06021.html
[3] http://www.spinics.net/lists/arm-kernel/msg429834.html
Cc: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: Roger Quadros <rogerq@ti.com>
Reported-by: Roger Quadros <rogerq@ti.com>
Tested-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-08-17 20:35:23 +08:00
|
|
|
int _gpiochip_irqchip_add(struct gpio_chip *gpiochip,
|
|
|
|
struct irq_chip *irqchip,
|
|
|
|
unsigned int first_irq,
|
|
|
|
irq_flow_handler_t handler,
|
|
|
|
unsigned int type,
|
|
|
|
struct lock_class_key *lock_key);
|
|
|
|
|
|
|
|
#ifdef CONFIG_LOCKDEP
|
|
|
|
#define gpiochip_irqchip_add(...) \
|
|
|
|
( \
|
|
|
|
({ \
|
|
|
|
static struct lock_class_key _key; \
|
|
|
|
_gpiochip_irqchip_add(__VA_ARGS__, &_key); \
|
|
|
|
}) \
|
|
|
|
)
|
|
|
|
#else
|
|
|
|
#define gpiochip_irqchip_add(...) \
|
|
|
|
_gpiochip_irqchip_add(__VA_ARGS__, NULL)
|
|
|
|
#endif
|
2014-03-25 17:40:18 +08:00
|
|
|
|
2014-09-05 19:09:25 +08:00
|
|
|
#endif /* CONFIG_GPIOLIB_IRQCHIP */
|
2014-03-25 17:40:18 +08:00
|
|
|
|
2015-10-11 23:34:15 +08:00
|
|
|
int gpiochip_generic_request(struct gpio_chip *chip, unsigned offset);
|
|
|
|
void gpiochip_generic_free(struct gpio_chip *chip, unsigned offset);
|
|
|
|
|
2015-03-18 08:56:17 +08:00
|
|
|
#ifdef CONFIG_PINCTRL
|
|
|
|
|
|
|
|
/**
|
|
|
|
* struct gpio_pin_range - pin range controlled by a gpio chip
|
|
|
|
* @head: list for maintaining set of pin ranges, used internally
|
|
|
|
* @pctldev: pinctrl device which handles corresponding pins
|
|
|
|
* @range: actual range of pins controlled by a gpio controller
|
|
|
|
*/
|
|
|
|
|
|
|
|
struct gpio_pin_range {
|
|
|
|
struct list_head node;
|
|
|
|
struct pinctrl_dev *pctldev;
|
|
|
|
struct pinctrl_gpio_range range;
|
|
|
|
};
|
|
|
|
|
|
|
|
int gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name,
|
|
|
|
unsigned int gpio_offset, unsigned int pin_offset,
|
|
|
|
unsigned int npins);
|
|
|
|
int gpiochip_add_pingroup_range(struct gpio_chip *chip,
|
|
|
|
struct pinctrl_dev *pctldev,
|
|
|
|
unsigned int gpio_offset, const char *pin_group);
|
|
|
|
void gpiochip_remove_pin_ranges(struct gpio_chip *chip);
|
|
|
|
|
|
|
|
#else
|
|
|
|
|
|
|
|
static inline int
|
|
|
|
gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name,
|
|
|
|
unsigned int gpio_offset, unsigned int pin_offset,
|
|
|
|
unsigned int npins)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
static inline int
|
|
|
|
gpiochip_add_pingroup_range(struct gpio_chip *chip,
|
|
|
|
struct pinctrl_dev *pctldev,
|
|
|
|
unsigned int gpio_offset, const char *pin_group)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void
|
|
|
|
gpiochip_remove_pin_ranges(struct gpio_chip *chip)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
|
|
|
#endif /* CONFIG_PINCTRL */
|
|
|
|
|
2014-08-20 01:06:09 +08:00
|
|
|
struct gpio_desc *gpiochip_request_own_desc(struct gpio_chip *chip, u16 hwnum,
|
|
|
|
const char *label);
|
2014-07-22 23:01:01 +08:00
|
|
|
void gpiochip_free_own_desc(struct gpio_desc *desc);
|
|
|
|
|
2014-02-09 16:43:54 +08:00
|
|
|
#else /* CONFIG_GPIOLIB */
|
|
|
|
|
|
|
|
static inline struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc)
|
|
|
|
{
|
|
|
|
/* GPIO can never have been requested */
|
|
|
|
WARN_ON(1);
|
|
|
|
return ERR_PTR(-ENODEV);
|
|
|
|
}
|
|
|
|
|
|
|
|
#endif /* CONFIG_GPIOLIB */
|
|
|
|
|
2013-10-18 01:21:36 +08:00
|
|
|
#endif
|